xref: /kernel/linux/linux-6.6/scripts/dtc/include-prefixes/arm64/qcom/sm6350.dtsi

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com>
 */

#include <dt-bindings/clock/qcom,dispcc-sm6350.h>
#include <dt-bindings/clock/qcom,gcc-sm6350.h>
#include <dt-bindings/clock/qcom,gpucc-sm6350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sm6350-camcc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm6350.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>

/ {
	interrupt-parent = <&intc>;
	#address-cells = <2>;
	#size-cells = <2>;

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <76800000>;
			clock-output-names = "xo_board";
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			clock-frequency = <32764>;
			#clock-cells = <0>;
		};
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo560";
			reg = <0x0 0x0>;
			clocks = <&cpufreq_hw 0>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&L2_0>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			operating-points-v2 = <&cpu0_opp_table>;
			interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
					 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
			power-domains = <&CPU_PD0>;
			power-domain-names = "psci";
			#cooling-cells = <2>;
			L2_0: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
				L3_0: l3-cache {
					compatible = "cache";
					cache-level = <3>;
					cache-unified;
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo560";
			reg = <0x0 0x100>;
			clocks = <&cpufreq_hw 0>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&L2_100>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			operating-points-v2 = <&cpu0_opp_table>;
			interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
					 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
			power-domains = <&CPU_PD1>;
			power-domain-names = "psci";
			#cooling-cells = <2>;
			L2_100: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,kryo560";
			reg = <0x0 0x200>;
			clocks = <&cpufreq_hw 0>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&L2_200>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			operating-points-v2 = <&cpu0_opp_table>;
			interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
					 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
			power-domains = <&CPU_PD2>;
			power-domain-names = "psci";
			#cooling-cells = <2>;
			L2_200: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "qcom,kryo560";
			reg = <0x0 0x300>;
			clocks = <&cpufreq_hw 0>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&L2_300>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			operating-points-v2 = <&cpu0_opp_table>;
			interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
					 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
			power-domains = <&CPU_PD3>;
			power-domain-names = "psci";
			#cooling-cells = <2>;
			L2_300: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "qcom,kryo560";
			reg = <0x0 0x400>;
			clocks = <&cpufreq_hw 0>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&L2_400>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			operating-points-v2 = <&cpu0_opp_table>;
			interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
					 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
			power-domains = <&CPU_PD4>;
			power-domain-names = "psci";
			#cooling-cells = <2>;
			L2_400: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "qcom,kryo560";
			reg = <0x0 0x500>;
			clocks = <&cpufreq_hw 0>;
			enable-method = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			next-level-cache = <&L2_500>;
			qcom,freq-domain = <&cpufreq_hw 0>;
			operating-points-v2 = <&cpu0_opp_table>;
			interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
					 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
			power-domains = <&CPU_PD5>;
			power-domain-names = "psci";
			#cooling-cells = <2>;
			L2_500: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "qcom,kryo560";
			reg = <0x0 0x600>;
			clocks = <&cpufreq_hw 1>;
			enable-method = "psci";
			capacity-dmips-mhz = <1894>;
			dynamic-power-coefficient = <703>;
			next-level-cache = <&L2_600>;
			qcom,freq-domain = <&cpufreq_hw 1>;
			operating-points-v2 = <&cpu6_opp_table>;
			interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
					 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
			power-domains = <&CPU_PD6>;
			power-domain-names = "psci";
			#cooling-cells = <2>;
			L2_600: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "qcom,kryo560";
			reg = <0x0 0x700>;
			clocks = <&cpufreq_hw 1>;
			enable-method = "psci";
			capacity-dmips-mhz = <1894>;
			dynamic-power-coefficient = <703>;
			next-level-cache = <&L2_700>;
			qcom,freq-domain = <&cpufreq_hw 1>;
			operating-points-v2 = <&cpu6_opp_table>;
			interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
					 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
					<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
			power-domains = <&CPU_PD7>;
			power-domain-names = "psci";
			#cooling-cells = <2>;
			L2_700: l2-cache {
				compatible = "cache";
				cache-level = <2>;
				cache-unified;
				next-level-cache = <&L3_0>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};

				core4 {
					cpu = <&CPU4>;
				};

				core5 {
					cpu = <&CPU5>;
				};

				core6 {
					cpu = <&CPU6>;
				};

				core7 {
					cpu = <&CPU7>;
				};
			};
		};

		domain-idle-states {
			CLUSTER_SLEEP_PC: cluster-sleep-0 {
				compatible = "domain-idle-state";
				arm,psci-suspend-param = <0x41000044>;
				entry-latency-us = <2752>;
				exit-latency-us = <3048>;
				min-residency-us = <6118>;
			};

			CLUSTER_SLEEP_CX_RET: cluster-sleep-1 {
				compatible = "domain-idle-state";
				arm,psci-suspend-param = <0x41001244>;
				entry-latency-us = <3638>;
				exit-latency-us = <4562>;
				min-residency-us = <8467>;
			};

			CLUSTER_AOSS_SLEEP: cluster-sleep-2 {
				compatible = "domain-idle-state";
				arm,psci-suspend-param = <0x4100b244>;
				entry-latency-us = <3263>;
				exit-latency-us = <6562>;
				min-residency-us = <9987>;
			};
		};

		cpu_idle_states: idle-states {
			entry-method = "psci";

			LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
				compatible = "arm,idle-state";
				idle-state-name = "little-power-collapse";
				arm,psci-suspend-param = <0x40000003>;
				entry-latency-us = <549>;
				exit-latency-us = <901>;
				min-residency-us = <1774>;
				local-timer-stop;
			};

			LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
				compatible = "arm,idle-state";
				idle-state-name = "little-rail-power-collapse";
				arm,psci-suspend-param = <0x40000004>;
				entry-latency-us = <702>;
				exit-latency-us = <915>;
				min-residency-us = <4001>;
				local-timer-stop;
			};

			BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
				compatible = "arm,idle-state";
				idle-state-name = "big-power-collapse";
				arm,psci-suspend-param = <0x40000003>;
				entry-latency-us = <523>;
				exit-latency-us = <1244>;
				min-residency-us = <2207>;
				local-timer-stop;
			};

			BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
				compatible = "arm,idle-state";
				idle-state-name = "big-rail-power-collapse";
				arm,psci-suspend-param = <0x40000004>;
				entry-latency-us = <526>;
				exit-latency-us = <1854>;
				min-residency-us = <5555>;
				local-timer-stop;
			};
		};
	};

	firmware {
		scm: scm {
			compatible = "qcom,scm-sm6350", "qcom,scm";
			#reset-cells = <1>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		/* We expect the bootloader to fill in the size */
		reg = <0x0 0x80000000 0x0 0x0>;
	};

	cpu0_opp_table: opp-table-cpu0 {
		compatible = "operating-points-v2";
		opp-shared;

		opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			/* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */
			opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
		};

		opp-576000000 {
			opp-hz = /bits/ 64 <576000000>;
			opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>;
		};

		opp-768000000 {
			opp-hz = /bits/ 64 <768000000>;
			opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
		};

		opp-1017600000 {
			opp-hz = /bits/ 64 <1017600000>;
			opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
		};

		opp-1248000000 {
			opp-hz = /bits/ 64 <1248000000>;
			opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
		};

		opp-1324800000 {
			opp-hz = /bits/ 64 <1324800000>;
			opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>;
		};

		opp-1516800000 {
			opp-hz = /bits/ 64 <1516800000>;
			opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
		};

		opp-1612800000 {
			opp-hz = /bits/ 64 <1612800000>;
			opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
		};

		opp-1708800000 {
			opp-hz = /bits/ 64 <1708800000>;
			opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
		};
	};

	cpu6_opp_table: opp-table-cpu6 {
		compatible = "operating-points-v2";
		opp-shared;

		opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
		};

		opp-787200000 {
			opp-hz = /bits/ 64 <787200000>;
			opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
		};

		opp-979200000 {
			opp-hz = /bits/ 64 <979200000>;
			opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>;
		};

		opp-1036800000 {
			opp-hz = /bits/ 64 <1036800000>;
			opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
		};

		opp-1248000000 {
			opp-hz = /bits/ 64 <1248000000>;
			opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
		};

		opp-1401600000 {
			opp-hz = /bits/ 64 <1401600000>;
			opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>;
		};

		opp-1555200000 {
			opp-hz = /bits/ 64 <1555200000>;
			opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
		};

		opp-1766400000 {
			opp-hz = /bits/ 64 <1766400000>;
			opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
		};

		opp-1900800000 {
			opp-hz = /bits/ 64 <1900800000>;
			opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
		};

		opp-2073600000 {
			opp-hz = /bits/ 64 <2073600000>;
			opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
		};
	};

	qup_opp_table: opp-table-qup {
		compatible = "operating-points-v2";

		opp-75000000 {
			opp-hz = /bits/ 64 <75000000>;
			required-opps = <&rpmhpd_opp_low_svs>;
		};

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			required-opps = <&rpmhpd_opp_svs>;
		};

		opp-128000000 {
			opp-hz = /bits/ 64 <128000000>;
			required-opps = <&rpmhpd_opp_nom>;
		};
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";

		CPU_PD0: power-domain-cpu0 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
		};

		CPU_PD1: power-domain-cpu1 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
		};

		CPU_PD2: power-domain-cpu2 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
		};

		CPU_PD3: power-domain-cpu3 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
		};

		CPU_PD4: power-domain-cpu4 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
		};

		CPU_PD5: power-domain-cpu5 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
		};

		CPU_PD6: power-domain-cpu6 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
		};

		CPU_PD7: power-domain-cpu7 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
			domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
		};

		CLUSTER_PD: power-domain-cpu-cluster0 {
			#power-domain-cells = <0>;
			domain-idle-states = <&CLUSTER_SLEEP_PC
					      &CLUSTER_SLEEP_CX_RET
					      &CLUSTER_AOSS_SLEEP>;
		};
	};

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		hyp_mem: memory@80000000 {
			reg = <0 0x80000000 0 0x600000>;
			no-map;
		};

		xbl_aop_mem: memory@80700000 {
			reg = <0 0x80700000 0 0x160000>;
			no-map;
		};

		cmd_db: memory@80860000 {
			compatible = "qcom,cmd-db";
			reg = <0 0x80860000 0 0x20000>;
			no-map;
		};

		sec_apps_mem: memory@808ff000 {
			reg = <0 0x808ff000 0 0x1000>;
			no-map;
		};

		smem_mem: memory@80900000 {
			reg = <0 0x80900000 0 0x200000>;
			no-map;
		};

		cdsp_sec_mem: memory@80b00000 {
			reg = <0 0x80b00000 0 0x1e00000>;
			no-map;
		};

		pil_camera_mem: memory@86000000 {
			reg = <0 0x86000000 0 0x500000>;
			no-map;
		};

		pil_npu_mem: memory@86500000 {
			reg = <0 0x86500000 0 0x500000>;
			no-map;
		};

		pil_video_mem: memory@86a00000 {
			reg = <0 0x86a00000 0 0x500000>;
			no-map;
		};

		pil_cdsp_mem: memory@86f00000 {
			reg = <0 0x86f00000 0 0x1e00000>;
			no-map;
		};

		pil_adsp_mem: memory@88d00000 {
			reg = <0 0x88d00000 0 0x2800000>;
			no-map;
		};

		wlan_fw_mem: memory@8b500000 {
			reg = <0 0x8b500000 0 0x200000>;
			no-map;
		};

		pil_ipa_fw_mem: memory@8b700000 {
			reg = <0 0x8b700000 0 0x10000>;
			no-map;
		};

		pil_ipa_gsi_mem: memory@8b710000 {
			reg = <0 0x8b710000 0 0x5400>;
			no-map;
		};

		pil_modem_mem: memory@8b800000 {
			reg = <0 0x8b800000 0 0xf800000>;
			no-map;
		};

		cont_splash_memory: memory@a0000000 {
			reg = <0 0xa0000000 0 0x2300000>;
			no-map;
		};

		dfps_data_memory: memory@a2300000 {
			reg = <0 0xa2300000 0 0x100000>;
			no-map;
		};

		removed_region: memory@c0000000 {
			reg = <0 0xc0000000 0 0x3900000>;
			no-map;
		};

		pil_gpu_mem: memory@f0d00000 {
			reg = <0 0xf0d00000 0 0x1000>;
			no-map;
		};

		debug_region: memory@ffb00000 {
			reg = <0 0xffb00000 0 0xc0000>;
			no-map;
		};

		last_log_region: memory@ffbc0000 {
			reg = <0 0xffbc0000 0 0x40000>;
			no-map;
		};

		ramoops: ramoops@ffc00000 {
			compatible = "ramoops";
			reg = <0 0xffc00000 0 0x100000>;
			record-size = <0x1000>;
			console-size = <0x40000>;
			pmsg-size = <0x20000>;
			ecc-size = <16>;
			no-map;
		};

		cmdline_region: memory@ffd00000 {
			reg = <0 0xffd00000 0 0x1000>;
			no-map;
		};
	};

	smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		hwlocks = <&tcsr_mutex 3>;
	};

	smp2p-adsp {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;
		interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
					     IPCC_MPROC_SIGNAL_SMP2P
					     IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc IPCC_CLIENT_LPASS
				IPCC_MPROC_SIGNAL_SMP2P>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		smp2p_adsp_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_adsp_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-cdsp {
		compatible = "qcom,smp2p";
		qcom,smem = <94>, <432>;
		interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
					     IPCC_MPROC_SIGNAL_SMP2P
					     IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc IPCC_CLIENT_CDSP
				IPCC_MPROC_SIGNAL_SMP2P>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <5>;

		smp2p_cdsp_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_cdsp_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-mpss {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;

		interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
					     IPCC_MPROC_SIGNAL_SMP2P
					     IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc IPCC_CLIENT_MPSS
				IPCC_MPROC_SIGNAL_SMP2P>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		ipa_smp2p_out: ipa-ap-to-modem {
			qcom,entry-name = "ipa";
			#qcom,smem-state-cells = <1>;
		};

		ipa_smp2p_in: ipa-modem-to-ap {
			qcom,entry-name = "ipa";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	soc: soc@0 {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0 0 0 0 0x10 0>;
		dma-ranges = <0 0 0 0 0x10 0>;
		compatible = "simple-bus";

		gcc: clock-controller@100000 {
			compatible = "qcom,gcc-sm6350";
			reg = <0 0x00100000 0 0x1f0000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			clock-names = "bi_tcxo",
				      "bi_tcxo_ao",
				      "sleep_clk";
			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&rpmhcc RPMH_CXO_CLK_A>,
				 <&sleep_clk>;
		};

		ipcc: mailbox@408000 {
			compatible = "qcom,sm6350-ipcc", "qcom,ipcc";
			reg = <0 0x00408000 0 0x1000>;
			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <3>;
			#mbox-cells = <2>;
		};

		qfprom: qfprom@784000 {
			compatible = "qcom,sm6350-qfprom", "qcom,qfprom";
			reg = <0 0x00784000 0 0x3000>;
			#address-cells = <1>;
			#size-cells = <1>;

			gpu_speed_bin: gpu-speed-bin@2015 {
				reg = <0x2015 0x1>;
				bits = <0 8>;
			};
		};

		rng: rng@793000 {
			compatible = "qcom,prng-ee";
			reg = <0 0x00793000 0 0x1000>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};

		sdhc_1: mmc@7c4000 {
			compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
			reg = <0 0x007c4000 0 0x1000>,
				<0 0x007c5000 0 0x1000>,
				<0 0x007c8000 0 0x8000>;
			reg-names = "hc", "cqhci", "ice";

			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			iommus = <&apps_smmu 0x60 0x0>;

			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
				 <&gcc GCC_SDCC1_APPS_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "iface", "core", "xo";
			resets = <&gcc GCC_SDCC1_BCR>;
			qcom,dll-config = <0x000f642c>;
			qcom,ddr-config = <0x80040868>;
			power-domains = <&rpmhpd SM6350_CX>;
			operating-points-v2 = <&sdhc1_opp_table>;
			bus-width = <8>;
			non-removable;
			supports-cqe;

			status = "disabled";

			sdhc1_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-19200000 {
					opp-hz = /bits/ 64 <19200000>;
					required-opps = <&rpmhpd_opp_min_svs>;
				};

				opp-100000000 {
					opp-hz = /bits/ 64 <100000000>;
					required-opps = <&rpmhpd_opp_low_svs>;
				};

				opp-384000000 {
					opp-hz = /bits/ 64 <384000000>;
					required-opps = <&rpmhpd_opp_svs_l1>;
				};
			};
		};

		gpi_dma0: dma-controller@800000 {
			compatible = "qcom,sm6350-gpi-dma";
			reg = <0 0x00800000 0 0x60000>;
			interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
			dma-channels = <10>;
			dma-channel-mask = <0x1f>;
			iommus = <&apps_smmu 0x56 0x0>;
			#dma-cells = <3>;
			status = "disabled";
		};

		qupv3_id_0: geniqup@8c0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0x0 0x008c0000 0x0 0x2000>;
			clock-names = "m-ahb", "s-ahb";
			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
			#address-cells = <2>;
			#size-cells = <2>;
			iommus = <&apps_smmu 0x43 0x0>;
			ranges;
			status = "disabled";

			i2c0: i2c@880000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00880000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c0_default>;
				interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
						<&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				status = "disabled";
			};

			uart1: serial@884000 {
				compatible = "qcom,geni-uart";
				reg = <0 0x00884000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
				interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
				power-domains = <&rpmhpd SM6350_CX>;
				operating-points-v2 = <&qup_opp_table>;
				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
						<&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
				interconnect-names = "qup-core", "qup-config";
				status = "disabled";
			};

			i2c2: i2c@888000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00888000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c2_default>;
				interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
						<&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				status = "disabled";
			};
		};

		gpi_dma1: dma-controller@900000 {
			compatible = "qcom,sm6350-gpi-dma";
			reg = <0 0x00900000 0 0x60000>;
			interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>;
			dma-channels = <10>;
			dma-channel-mask = <0x3f>;
			iommus = <&apps_smmu 0x4d6 0x0>;
			#dma-cells = <3>;
			status = "disabled";
		};

		qupv3_id_1: geniqup@9c0000 {
			compatible = "qcom,geni-se-qup";
			reg = <0x0 0x009c0000 0x0 0x2000>;
			clock-names = "m-ahb", "s-ahb";
			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
			#address-cells = <2>;
			#size-cells = <2>;
			iommus = <&apps_smmu 0x4c3 0x0>;
			ranges;
			status = "disabled";

			i2c6: i2c@980000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00980000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c6_default>;
				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
						<&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				status = "disabled";
			};

			i2c7: i2c@984000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00984000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c7_default>;
				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
						<&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				status = "disabled";
			};

			i2c8: i2c@988000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00988000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c8_default>;
				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
						<&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				status = "disabled";
			};

			uart9: serial@98c000 {
				compatible = "qcom,geni-debug-uart";
				reg = <0 0x0098c000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_uart9_default>;
				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
				interconnect-names = "qup-core", "qup-config";
				status = "disabled";
			};

			i2c10: i2c@990000 {
				compatible = "qcom,geni-i2c";
				reg = <0 0x00990000 0 0x4000>;
				clock-names = "se";
				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
				pinctrl-names = "default";
				pinctrl-0 = <&qup_i2c10_default>;
				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
				dma-names = "tx", "rx";
				#address-cells = <1>;
				#size-cells = <0>;
				interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
						<&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>;
				interconnect-names = "qup-core", "qup-config", "qup-memory";
				status = "disabled";
			};
		};

		config_noc: interconnect@1500000 {
			compatible = "qcom,sm6350-config-noc";
			reg = <0 0x01500000 0 0x28000>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		system_noc: interconnect@1620000 {
			compatible = "qcom,sm6350-system-noc";
			reg = <0 0x01620000 0 0x17080>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;

			clk_virt: interconnect-clk-virt {
				compatible = "qcom,sm6350-clk-virt";
				#interconnect-cells = <2>;
				qcom,bcm-voters = <&apps_bcm_voter>;
			};
		};

		aggre1_noc: interconnect@16e0000 {
			compatible = "qcom,sm6350-aggre1-noc";
			reg = <0 0x016e0000 0 0x15080>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		aggre2_noc: interconnect@1700000 {
			compatible = "qcom,sm6350-aggre2-noc";
			reg = <0 0x01700000 0 0x1f880>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;

			compute_noc: interconnect-compute-noc {
				compatible = "qcom,sm6350-compute-noc";
				#interconnect-cells = <2>;
				qcom,bcm-voters = <&apps_bcm_voter>;
			};
		};

		mmss_noc: interconnect@1740000 {
			compatible = "qcom,sm6350-mmss-noc";
			reg = <0 0x01740000 0 0x1c100>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		ufs_mem_hc: ufs@1d84000 {
			compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
				     "jedec,ufs-2.0";
			reg = <0 0x01d84000 0 0x3000>,
			      <0 0x01d90000 0 0x8000>;
			reg-names = "std", "ice";
			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
			phys = <&ufs_mem_phy_lanes>;
			phy-names = "ufsphy";
			lanes-per-direction = <2>;
			#reset-cells = <1>;
			resets = <&gcc GCC_UFS_PHY_BCR>;
			reset-names = "rst";

			power-domains = <&gcc UFS_PHY_GDSC>;

			iommus = <&apps_smmu 0x80 0x0>;

			clock-names = "core_clk",
				      "bus_aggr_clk",
				      "iface_clk",
				      "core_clk_unipro",
				      "ref_clk",
				      "tx_lane0_sync_clk",
				      "rx_lane0_sync_clk",
				      "rx_lane1_sync_clk",
				      "ice_core_clk";
			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
				 <&gcc GCC_UFS_PHY_AHB_CLK>,
				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
				 <&rpmhcc RPMH_QLINK_CLK>,
				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
				 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
				 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
			freq-table-hz =
				<50000000 200000000>,
				<0 0>,
				<0 0>,
				<37500000 150000000>,
				<75000000 300000000>,
				<0 0>,
				<0 0>,
				<0 0>,
				<0 0>;

			status = "disabled";
		};

		ufs_mem_phy: phy@1d87000 {
			compatible = "qcom,sm6350-qmp-ufs-phy";
			reg = <0 0x01d87000 0 0x18c>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			clock-names = "ref",
				      "ref_aux";
			clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;

			resets = <&ufs_mem_hc 0>;
			reset-names = "ufsphy";

			status = "disabled";

			ufs_mem_phy_lanes: phy@1d87400 {
				reg = <0 0x01d87400 0 0x128>,
				      <0 0x01d87600 0 0x1fc>,
				      <0 0x01d87c00 0 0x1dc>,
				      <0 0x01d87800 0 0x128>,
				      <0 0x01d87a00 0 0x1fc>;
				#phy-cells = <0>;
			};
		};

		ipa: ipa@1e40000 {
			compatible = "qcom,sm6350-ipa";

			iommus = <&apps_smmu 0x440 0x0>,
				 <&apps_smmu 0x442 0x0>;
			reg = <0 0x01e40000 0 0x8000>,
			      <0 0x01e50000 0 0x3000>,
			      <0 0x01e04000 0 0x23000>;
			reg-names = "ipa-reg",
				    "ipa-shared",
				    "gsi";

			interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
					      <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
					      <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "ipa",
					  "gsi",
					  "ipa-clock-query",
					  "ipa-setup-ready";

			clocks = <&rpmhcc RPMH_IPA_CLK>;
			clock-names = "core";

			interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>,
					<&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>,
					<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>;
			interconnect-names = "memory", "imem", "config";

			qcom,smem-states = <&ipa_smp2p_out 0>,
					   <&ipa_smp2p_out 1>;
			qcom,smem-state-names = "ipa-clock-enabled-valid",
						"ipa-clock-enabled";

			status = "disabled";
		};

		tcsr_mutex: hwlock@1f40000 {
			compatible = "qcom,tcsr-mutex";
			reg = <0x0 0x01f40000 0x0 0x40000>;
			#hwlock-cells = <1>;
		};

		adsp: remoteproc@3000000 {
			compatible = "qcom,sm6350-adsp-pas";
			reg = <0 0x03000000 0 0x100>;

			interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready",
					  "handover", "stop-ack";

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "xo";

			power-domains = <&rpmhpd SM6350_LCX>,
					<&rpmhpd SM6350_LMX>;
			power-domain-names = "lcx", "lmx";

			memory-region = <&pil_adsp_mem>;

			qcom,qmp = <&aoss_qmp>;

			qcom,smem-states = <&smp2p_adsp_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			glink-edge {
				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
							     IPCC_MPROC_SIGNAL_GLINK_QMP
							     IRQ_TYPE_EDGE_RISING>;
				mboxes = <&ipcc IPCC_CLIENT_LPASS
						IPCC_MPROC_SIGNAL_GLINK_QMP>;

				label = "lpass";
				qcom,remote-pid = <2>;

				fastrpc {
					compatible = "qcom,fastrpc";
					qcom,glink-channels = "fastrpcglink-apps-dsp";
					label = "adsp";
					#address-cells = <1>;
					#size-cells = <0>;

					compute-cb@3 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <3>;
						iommus = <&apps_smmu 0x1003 0x0>;
					};

					compute-cb@4 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <4>;
						iommus = <&apps_smmu 0x1004 0x0>;
					};

					compute-cb@5 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <5>;
						iommus = <&apps_smmu 0x1005 0x0>;
						qcom,nsessions = <5>;
					};
				};
			};
		};

		gpu: gpu@3d00000 {
			compatible = "qcom,adreno-619.0", "qcom,adreno";
			reg = <0 0x03d00000 0 0x40000>,
			      <0 0x03d9e000 0 0x1000>;
			reg-names = "kgsl_3d0_reg_memory",
				    "cx_mem";
			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;

			iommus = <&adreno_smmu 0>;
			operating-points-v2 = <&gpu_opp_table>;
			qcom,gmu = <&gmu>;
			nvmem-cells = <&gpu_speed_bin>;
			nvmem-cell-names = "speed_bin";

			status = "disabled";

			zap-shader {
				memory-region = <&pil_gpu_mem>;
			};

			gpu_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-850000000 {
					opp-hz = /bits/ 64 <850000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
					opp-supported-hw = <0x02>;
				};

				opp-800000000 {
					opp-hz = /bits/ 64 <800000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
					opp-supported-hw = <0x04>;
				};

				opp-650000000 {
					opp-hz = /bits/ 64 <650000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
					opp-supported-hw = <0x08>;
				};

				opp-565000000 {
					opp-hz = /bits/ 64 <565000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
					opp-supported-hw = <0x10>;
				};

				opp-430000000 {
					opp-hz = /bits/ 64 <430000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
					opp-supported-hw = <0xff>;
				};

				opp-355000000 {
					opp-hz = /bits/ 64 <355000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
					opp-supported-hw = <0xff>;
				};

				opp-253000000 {
					opp-hz = /bits/ 64 <253000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
					opp-supported-hw = <0xff>;
				};
			};
		};

		adreno_smmu: iommu@3d40000 {
			compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
			reg = <0 0x03d40000 0 0x10000>;
			#iommu-cells = <1>;
			#global-interrupts = <2>;
			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gpucc GPU_CC_AHB_CLK>,
				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
			clock-names = "ahb",
				      "bus",
				      "iface";

			power-domains = <&gpucc GPU_CX_GDSC>;
		};

		gmu: gmu@3d6a000 {
			compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
			reg = <0 0x03d6a000 0 0x31000>,
			      <0 0x0b290000 0 0x10000>,
			      <0 0x0b490000 0 0x10000>;
			reg-names = "gmu",
				    "gmu_pdc",
				    "gmu_pdc_seq";

			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hfi",
					  "gmu";

			clocks = <&gpucc GPU_CC_AHB_CLK>,
				 <&gpucc GPU_CC_CX_GMU_CLK>,
				 <&gpucc GPU_CC_CXO_CLK>,
				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
			clock-names = "ahb",
				      "gmu",
				      "cxo",
				      "axi",
				      "memnoc";

			power-domains = <&gpucc GPU_CX_GDSC>,
					<&gpucc GPU_GX_GDSC>;
			power-domain-names = "cx",
					     "gx";

			iommus = <&adreno_smmu 5>;

			operating-points-v2 = <&gmu_opp_table>;

			status = "disabled";

			gmu_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-200000000 {
					opp-hz = /bits/ 64 <200000000>;
					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
				};
			};
		};

		gpucc: clock-controller@3d90000 {
			compatible = "qcom,sm6350-gpucc";
			reg = <0 0x03d90000 0 0x9000>;
			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_GPU_GPLL0_CLK>,
				 <&gcc GCC_GPU_GPLL0_DIV_CLK>;
			clock-names = "bi_tcxo",
				      "gcc_gpu_gpll0_clk_src",
				      "gcc_gpu_gpll0_div_clk_src";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		mpss: remoteproc@4080000 {
			compatible = "qcom,sm6350-mpss-pas";
			reg = <0x0 0x04080000 0x0 0x4040>;

			interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
					      <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
					      <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready", "handover",
					  "stop-ack", "shutdown-ack";

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "xo";

			power-domains = <&rpmhpd SM6350_CX>,
					<&rpmhpd SM6350_MSS>;
			power-domain-names = "cx", "mss";

			memory-region = <&pil_modem_mem>;

			qcom,qmp = <&aoss_qmp>;

			qcom,smem-states = <&modem_smp2p_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			glink-edge {
				interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
							     IPCC_MPROC_SIGNAL_GLINK_QMP
							     IRQ_TYPE_EDGE_RISING>;
				mboxes = <&ipcc IPCC_CLIENT_MPSS
						IPCC_MPROC_SIGNAL_GLINK_QMP>;
				label = "modem";
				qcom,remote-pid = <1>;
			};
		};

		cdsp: remoteproc@8300000 {
			compatible = "qcom,sm6350-cdsp-pas";
			reg = <0 0x08300000 0 0x10000>;

			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready",
					  "handover", "stop-ack";

			clocks = <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "xo";

			power-domains = <&rpmhpd SM6350_CX>,
					<&rpmhpd SM6350_MX>;
			power-domain-names = "cx", "mx";

			memory-region = <&pil_cdsp_mem>;

			qcom,qmp = <&aoss_qmp>;

			qcom,smem-states = <&smp2p_cdsp_out 0>;
			qcom,smem-state-names = "stop";

			status = "disabled";

			glink-edge {
				interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
							     IPCC_MPROC_SIGNAL_GLINK_QMP
							     IRQ_TYPE_EDGE_RISING>;
				mboxes = <&ipcc IPCC_CLIENT_CDSP
						IPCC_MPROC_SIGNAL_GLINK_QMP>;

				label = "cdsp";
				qcom,remote-pid = <5>;

				fastrpc {
					compatible = "qcom,fastrpc";
					qcom,glink-channels = "fastrpcglink-apps-dsp";
					label = "cdsp";
					#address-cells = <1>;
					#size-cells = <0>;

					compute-cb@1 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <1>;
						iommus = <&apps_smmu 0x1401 0x20>;
					};

					compute-cb@2 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <2>;
						iommus = <&apps_smmu 0x1402 0x20>;
					};

					compute-cb@3 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <3>;
						iommus = <&apps_smmu 0x1403 0x20>;
					};

					compute-cb@4 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <4>;
						iommus = <&apps_smmu 0x1404 0x20>;
					};

					compute-cb@5 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <5>;
						iommus = <&apps_smmu 0x1405 0x20>;
					};

					compute-cb@6 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <6>;
						iommus = <&apps_smmu 0x1406 0x20>;
					};

					compute-cb@7 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <7>;
						iommus = <&apps_smmu 0x1407 0x20>;
					};

					compute-cb@8 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <8>;
						iommus = <&apps_smmu 0x1408 0x20>;
					};

					/* note: secure cb9 in downstream */
				};
			};
		};

		sdhc_2: mmc@8804000 {
			compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
			reg = <0 0x08804000 0 0x1000>;

			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			iommus = <&apps_smmu 0x560 0x0>;

			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
				 <&gcc GCC_SDCC2_APPS_CLK>,
				 <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "iface", "core", "xo";
			resets = <&gcc GCC_SDCC2_BCR>;
			interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>,
					<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
			interconnect-names = "sdhc-ddr", "cpu-sdhc";

			pinctrl-0 = <&sdc2_on_state>;
			pinctrl-1 = <&sdc2_off_state>;
			pinctrl-names = "default", "sleep";

			qcom,dll-config = <0x0007642c>;
			qcom,ddr-config = <0x80040868>;
			power-domains = <&rpmhpd SM6350_CX>;
			operating-points-v2 = <&sdhc2_opp_table>;
			bus-width = <4>;

			status = "disabled";

			sdhc2_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-100000000 {
					opp-hz = /bits/ 64 <100000000>;
					required-opps = <&rpmhpd_opp_svs_l1>;
					opp-peak-kBps = <790000 131000>;
					opp-avg-kBps = <50000 50000>;
				};

				opp-202000000 {
					opp-hz = /bits/ 64 <202000000>;
					required-opps = <&rpmhpd_opp_nom>;
					opp-peak-kBps = <3190000 294000>;
					opp-avg-kBps = <261438 300000>;
				};
			};
		};

		usb_1_hsphy: phy@88e3000 {
			compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
			reg = <0 0x088e3000 0 0x400>;
			status = "disabled";
			#phy-cells = <0>;

			clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>;
			clock-names = "cfg_ahb", "ref";

			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
		};

		usb_1_qmpphy: phy@88e8000 {
			compatible = "qcom,sm6350-qmp-usb3-dp-phy";
			reg = <0 0x088e8000 0 0x3000>;

			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
			clock-names = "aux", "ref", "com_aux", "usb3_pipe";

			power-domains = <&gcc USB30_PRIM_GDSC>;

			resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
				 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
			reset-names = "phy", "common";

			#clock-cells = <1>;
			#phy-cells = <1>;

			status = "disabled";
		};

		dc_noc: interconnect@9160000 {
			compatible = "qcom,sm6350-dc-noc";
			reg = <0 0x09160000 0 0x3200>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		system-cache-controller@9200000 {
			compatible = "qcom,sm6350-llcc";
			reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
			reg-names = "llcc0_base", "llcc_broadcast_base";
		};

		gem_noc: interconnect@9680000 {
			compatible = "qcom,sm6350-gem-noc";
			reg = <0 0x09680000 0 0x3e200>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		npu_noc: interconnect@9990000 {
			compatible = "qcom,sm6350-npu-noc";
			reg = <0 0x09990000 0 0x1600>;
			#interconnect-cells = <2>;
			qcom,bcm-voters = <&apps_bcm_voter>;
		};

		pmu@90b6300 {
			compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon";
			reg = <0x0 0x090b6300 0x0 0x600>;
			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;

			operating-points-v2 = <&llcc_bwmon_opp_table>;
			interconnects = <&clk_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
					 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>;

			llcc_bwmon_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-0 {
					opp-peak-kBps = <2288000>;
				};

				opp-1 {
					opp-peak-kBps = <4577000>;
				};

				opp-2 {
					opp-peak-kBps = <7110000>;
				};

				opp-3 {
					opp-peak-kBps = <9155000>;
				};

				opp-4 {
					opp-peak-kBps = <12298000>;
				};

				opp-5 {
					opp-peak-kBps = <14236000>;
				};

			};
		};

		pmu@90cd000 {
			compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon";
			reg = <0x0 0x090cd000 0x0 0x1000>;
			interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;

			operating-points-v2 = <&cpu_bwmon_opp_table>;
			interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
					 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>;

			cpu_bwmon_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-0 {
					opp-peak-kBps = <762000>;
				};

				opp-1 {
					opp-peak-kBps = <1144000>;
				};

				opp-2 {
					opp-peak-kBps = <1720000>;
				};

				opp-3 {
					opp-peak-kBps = <2086000>;
				};

				opp-4 {
					opp-peak-kBps = <2597000>;
				};

				opp-5 {
					opp-peak-kBps = <2929000>;
				};

				opp-6 {
					opp-peak-kBps = <3879000>;
				};

				opp-7 {
					opp-peak-kBps = <5161000>;
				};

				opp-8 {
					opp-peak-kBps = <5931000>;
				};

				opp-9 {
					opp-peak-kBps = <6881000>;
				};

				opp-10 {
					opp-peak-kBps = <7980000>;
				};
			};
		};

		usb_1: usb@a6f8800 {
			compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
			reg = <0 0x0a6f8800 0 0x400>;
			status = "disabled";
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
			clock-names = "cfg_noc",
				      "core",
				      "iface",
				      "sleep",
				      "mock_utmi";

			interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
					      <&pdc 14 IRQ_TYPE_EDGE_BOTH>;

			interrupt-names = "hs_phy_irq", "ss_phy_irq",
					  "dm_hs_phy_irq", "dp_hs_phy_irq";

			power-domains = <&gcc USB30_PRIM_GDSC>;

			resets = <&gcc GCC_USB30_PRIM_BCR>;

			interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>,
					<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
			interconnect-names = "usb-ddr", "apps-usb";

			usb_1_dwc3: usb@a600000 {
				compatible = "snps,dwc3";
				reg = <0 0x0a600000 0 0xcd00>;
				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
				iommus = <&apps_smmu 0x540 0x0>;
				snps,dis_u2_susphy_quirk;
				snps,dis_enblslpm_quirk;
				snps,has-lpm-erratum;
				snps,hird-threshold = /bits/ 8 <0x10>;
				phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
				phy-names = "usb2-phy", "usb3-phy";
			};
		};

		cci0: cci@ac4a000 {
			compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
			reg = <0 0x0ac4a000 0 0x1000>;
			interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>;
			power-domains = <&camcc TITAN_TOP_GDSC>;

			clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
				 <&camcc CAMCC_SOC_AHB_CLK>,
				 <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
				 <&camcc CAMCC_CPAS_AHB_CLK>,
				 <&camcc CAMCC_CCI_0_CLK>,
				 <&camcc CAMCC_CCI_0_CLK_SRC>;
			clock-names = "camnoc_axi",
				      "soc_ahb",
				      "slow_ahb_src",
				      "cpas_ahb",
				      "cci",
				      "cci_src";

			assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
					  <&camcc CAMCC_CCI_0_CLK>;
			assigned-clock-rates = <80000000>, <37500000>;

			pinctrl-0 = <&cci0_default &cci1_default>;
			pinctrl-1 = <&cci0_sleep &cci1_sleep>;
			pinctrl-names = "default", "sleep";

			#address-cells = <1>;
			#size-cells = <0>;

			status = "disabled";

			cci0_i2c0: i2c-bus@0 {
				reg = <0>;
				clock-frequency = <1000000>;
				#address-cells = <1>;
				#size-cells = <0>;
			};

			cci0_i2c1: i2c-bus@1 {
				reg = <1>;
				clock-frequency = <1000000>;
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		cci1: cci@ac4b000 {
			compatible = "qcom,sm6350-cci", "qcom,msm8996-cci";
			reg = <0 0x0ac4b000 0 0x1000>;
			interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>;
			power-domains = <&camcc TITAN_TOP_GDSC>;

			clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
				 <&camcc CAMCC_SOC_AHB_CLK>,
				 <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
				 <&camcc CAMCC_CPAS_AHB_CLK>,
				 <&camcc CAMCC_CCI_1_CLK>,
				 <&camcc CAMCC_CCI_1_CLK_SRC>;
			clock-names = "camnoc_axi",
				      "soc_ahb",
				      "slow_ahb_src",
				      "cpas_ahb",
				      "cci",
				      "cci_src";

			assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
					  <&camcc CAMCC_CCI_1_CLK>;
			assigned-clock-rates = <80000000>, <37500000>;

			pinctrl-0 = <&cci2_default>;
			pinctrl-1 = <&cci2_sleep>;
			pinctrl-names = "default", "sleep";

			#address-cells = <1>;
			#size-cells = <0>;

			status = "disabled";

			cci1_i2c0: i2c-bus@0 {
				reg = <0>;
				clock-frequency = <1000000>;
				#address-cells = <1>;
				#size-cells = <0>;
			};

			/* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */
		};

		camcc: clock-controller@ad00000 {
			compatible = "qcom,sm6350-camcc";
			reg = <0 0x0ad00000 0 0x16000>;
			clocks = <&rpmhcc RPMH_CXO_CLK>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		mdss: display-subsystem@ae00000 {
			compatible = "qcom,sm6350-mdss";
			reg = <0 0x0ae00000 0 0x1000>;
			reg-names = "mdss";

			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <1>;

			clocks = <&gcc GCC_DISP_AHB_CLK>,
				 <&gcc GCC_DISP_AXI_CLK>,
				 <&dispcc DISP_CC_MDSS_MDP_CLK>;
			clock-names = "iface",
				      "bus",
				      "core";

			power-domains = <&dispcc MDSS_GDSC>;
			iommus = <&apps_smmu 0x800 0x2>;

			#address-cells = <2>;
			#size-cells = <2>;
			ranges;

			status = "disabled";

			mdss_mdp: display-controller@ae01000 {
				compatible = "qcom,sm6350-dpu";
				reg = <0 0x0ae01000 0 0x8f000>,
				      <0 0x0aeb0000 0 0x2008>;
				reg-names = "mdp", "vbif";

				interrupt-parent = <&mdss>;
				interrupts = <0>;

				clocks = <&gcc GCC_DISP_AXI_CLK>,
					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
					 <&dispcc DISP_CC_MDSS_ROT_CLK>,
					 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
					 <&dispcc DISP_CC_MDSS_MDP_CLK>,
					 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
				clock-names = "bus",
					      "iface",
					      "rot",
					      "lut",
					      "core",
					      "vsync";

				assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
				assigned-clock-rates = <19200000>;

				operating-points-v2 = <&mdp_opp_table>;
				power-domains = <&rpmhpd SM6350_CX>;

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;

						dpu_intf1_out: endpoint {
							remote-endpoint = <&mdss_dsi0_in>;
						};
					};
				};

				mdp_opp_table: opp-table {
					compatible = "operating-points-v2";

					opp-19200000 {
						opp-hz = /bits/ 64 <19200000>;
						required-opps = <&rpmhpd_opp_min_svs>;
					};

					opp-200000000 {
						opp-hz = /bits/ 64 <200000000>;
						required-opps = <&rpmhpd_opp_low_svs>;
					};

					opp-300000000 {
						opp-hz = /bits/ 64 <300000000>;
						required-opps = <&rpmhpd_opp_svs>;
					};

					opp-373333333 {
						opp-hz = /bits/ 64 <373333333>;
						required-opps = <&rpmhpd_opp_svs_l1>;
					};

					opp-448000000 {
						opp-hz = /bits/ 64 <448000000>;
						required-opps = <&rpmhpd_opp_nom>;
					};

					opp-560000000 {
						opp-hz = /bits/ 64 <560000000>;
						required-opps = <&rpmhpd_opp_turbo>;
					};
				};
			};

			mdss_dsi0: dsi@ae94000 {
				compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
				reg = <0 0x0ae94000 0 0x400>;
				reg-names = "dsi_ctrl";

				interrupt-parent = <&mdss>;
				interrupts = <4>;

				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
					 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
					 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
					 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
					 <&gcc GCC_DISP_AXI_CLK>;
				clock-names = "byte",
					      "byte_intf",
					      "pixel",
					      "core",
					      "iface",
					      "bus";

				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
						  <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
				assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;

				operating-points-v2 = <&mdss_dsi_opp_table>;
				power-domains = <&rpmhpd SM6350_MX>;

				phys = <&mdss_dsi0_phy>;
				phy-names = "dsi";

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;

						mdss_dsi0_in: endpoint {
							remote-endpoint = <&dpu_intf1_out>;
						};
					};

					port@1 {
						reg = <1>;

						mdss_dsi0_out: endpoint {
						};
					};
				};

				mdss_dsi_opp_table: opp-table {
					compatible = "operating-points-v2";

					opp-187500000 {
						opp-hz = /bits/ 64 <187500000>;
						required-opps = <&rpmhpd_opp_low_svs>;
					};

					opp-300000000 {
						opp-hz = /bits/ 64 <300000000>;
						required-opps = <&rpmhpd_opp_svs>;
					};

					opp-358000000 {
						opp-hz = /bits/ 64 <358000000>;
						required-opps = <&rpmhpd_opp_svs_l1>;
					};
				};
			};

			mdss_dsi0_phy: phy@ae94400 {
				compatible = "qcom,dsi-phy-10nm";
				reg = <0 0x0ae94400 0 0x200>,
				      <0 0x0ae94600 0 0x280>,
				      <0 0x0ae94a00 0 0x1e0>;
				reg-names = "dsi_phy",
					    "dsi_phy_lane",
					    "dsi_pll";

				#clock-cells = <1>;
				#phy-cells = <0>;

				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
					 <&rpmhcc RPMH_CXO_CLK>;
				clock-names = "iface", "ref";

				status = "disabled";
			};
		};

		dispcc: clock-controller@af00000 {
			compatible = "qcom,sm6350-dispcc";
			reg = <0 0x0af00000 0 0x20000>;
			clocks = <&rpmhcc RPMH_CXO_CLK>,
				 <&gcc GCC_DISP_GPLL0_CLK>,
				 <&mdss_dsi0_phy 0>,
				 <&mdss_dsi0_phy 1>,
				 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
				 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
			clock-names = "bi_tcxo",
				      "gcc_disp_gpll0_clk",
				      "dsi0_phy_pll_out_byteclk",
				      "dsi0_phy_pll_out_dsiclk",
				      "dp_phy_pll_link_clk",
				      "dp_phy_pll_vco_div_clk";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
		};

		pdc: interrupt-controller@b220000 {
			compatible = "qcom,sm6350-pdc", "qcom,pdc";
			reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
			qcom,pdc-ranges = <0 480 94>, <94 609 31>,
					  <125 63 1>, <126 655 12>, <138 139 15>;
			#interrupt-cells = <2>;
			interrupt-parent = <&intc>;
			interrupt-controller;
		};

		tsens0: thermal-sensor@c263000 {
			compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
			reg = <0 0x0c263000 0 0x1ff>, /* TM */
			      <0 0x0c222000 0 0x8>; /* SROT */
			#qcom,sensors = <16>;
			interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
				     <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "uplow", "critical";
			#thermal-sensor-cells = <1>;
		};

		tsens1: thermal-sensor@c265000 {
			compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
			reg = <0 0x0c265000 0 0x1ff>, /* TM */
			      <0 0x0c223000 0 0x8>; /* SROT */
			#qcom,sensors = <16>;
			interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
				     <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "uplow", "critical";
			#thermal-sensor-cells = <1>;
		};

		aoss_qmp: power-management@c300000 {
			compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp";
			reg = <0 0x0c300000 0 0x1000>;
			interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
						     IRQ_TYPE_EDGE_RISING>;
			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;

			#clock-cells = <0>;
		};

		spmi_bus: spmi@c440000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0 0x0c440000 0 0x1100>,
			      <0 0x0c600000 0 0x2000000>,
			      <0 0x0e600000 0 0x100000>,
			      <0 0x0e700000 0 0xa0000>,
			      <0 0x0c40a000 0 0x26000>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};

		tlmm: pinctrl@f100000 {
			compatible = "qcom,sm6350-tlmm";
			reg = <0 0x0f100000 0 0x300000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&tlmm 0 0 157>;
			wakeup-parent = <&pdc>;

			cci0_default: cci0-default-state {
				pins = "gpio39", "gpio40";
				function = "cci_i2c";
				drive-strength = <2>;
				bias-pull-up;
			};

			cci0_sleep: cci0-sleep-state {
				pins = "gpio39", "gpio40";
				function = "cci_i2c";
				drive-strength = <2>;
				bias-pull-down;
			};

			cci1_default: cci1-default-state {
				pins = "gpio41", "gpio42";
				function = "cci_i2c";
				drive-strength = <2>;
				bias-pull-up;
			};

			cci1_sleep: cci1-sleep-state {
				pins = "gpio41", "gpio42";
				function = "cci_i2c";
				drive-strength = <2>;
				bias-pull-down;
			};

			cci2_default: cci2-default-state {
				pins = "gpio43", "gpio44";
				function = "cci_i2c";
				drive-strength = <2>;
				bias-pull-up;
			};

			cci2_sleep: cci2-sleep-state {
				pins = "gpio43", "gpio44";
				function = "cci_i2c";
				drive-strength = <2>;
				bias-pull-down;
			};

			sdc2_off_state: sdc2-off-state {
				clk-pins {
					pins = "sdc2_clk";
					drive-strength = <2>;
					bias-disable;
				};

				cmd-pins {
					pins = "sdc2_cmd";
					drive-strength = <2>;
					bias-pull-up;
				};

				data-pins {
					pins = "sdc2_data";
					drive-strength = <2>;
					bias-pull-up;
				};
			};

			sdc2_on_state: sdc2-on-state {
				clk-pins {
					pins = "sdc2_clk";
					drive-strength = <16>;
					bias-disable;
				};

				cmd-pins {
					pins = "sdc2_cmd";
					drive-strength = <10>;
					bias-pull-up;
				};

				data-pins {
					pins = "sdc2_data";
					drive-strength = <10>;
					bias-pull-up;
				};
			};

			qup_uart9_default: qup-uart9-default-state {
				pins = "gpio25", "gpio26";
				function = "qup13_f2";
				drive-strength = <2>;
				bias-disable;
			};

			qup_i2c0_default: qup-i2c0-default-state {
				pins = "gpio0", "gpio1";
				function = "qup00";
				drive-strength = <2>;
				bias-pull-up;
			};

			qup_i2c2_default: qup-i2c2-default-state {
				pins = "gpio45", "gpio46";
				function = "qup02";
				drive-strength = <2>;
				bias-pull-up;
			};

			qup_i2c6_default: qup-i2c6-default-state {
				pins = "gpio13", "gpio14";
				function = "qup10";
				drive-strength = <2>;
				bias-pull-up;
			};

			qup_i2c7_default: qup-i2c7-default-state {
				pins = "gpio27", "gpio28";
				function = "qup11";
				drive-strength = <2>;
				bias-pull-up;
			};

			qup_i2c8_default: qup-i2c8-default-state {
				pins = "gpio19", "gpio20";
				function = "qup12";
				drive-strength = <2>;
				bias-pull-up;
			};

			qup_i2c10_default: qup-i2c10-default-state {
				pins = "gpio4", "gpio5";
				function = "qup14";
				drive-strength = <2>;
				bias-pull-up;
			};

			qup_uart1_cts: qup-uart1-cts-default-state {
				pins = "gpio61";
				function = "qup01";
				drive-strength = <2>;
				bias-disable;
			};

			qup_uart1_rts: qup-uart1-rts-default-state {
				pins = "gpio62";
				function = "qup01";
				drive-strength = <2>;
				bias-pull-down;
			};

			qup_uart1_rx: qup-uart1-rx-default-state {
				pins = "gpio64";
				function = "qup01";
				drive-strength = <2>;
				bias-disable;
			};

			qup_uart1_tx: qup-uart1-tx-default-state {
				pins = "gpio63";
				function = "qup01";
				drive-strength = <2>;
				bias-pull-up;
			};
		};

		apps_smmu: iommu@15000000 {
			compatible = "qcom,sm6350-smmu-500", "arm,mmu-500";
			reg = <0 0x15000000 0 0x100000>;
			#iommu-cells = <2>;
			#global-interrupts = <1>;
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
		};

		intc: interrupt-controller@17a00000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
			      <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
			interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
		};

		watchdog@17c10000 {
			compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt";
			reg = <0 0x17c10000 0 0x1000>;
			clocks = <&sleep_clk>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
		};

		timer@17c20000 {
			compatible = "arm,armv7-timer-mem";
			reg = <0x0 0x17c20000 0x0 0x1000>;
			clock-frequency = <19200000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0 0 0x20000000>;

			frame@17c21000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17c21000 0x1000>,
				      <0x17c22000 0x1000>;
			};

			frame@17c23000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17c23000 0x1000>;
				status = "disabled";
			};

			frame@17c25000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17c25000 0x1000>;
				status = "disabled";
			};

			frame@17c27000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17c27000 0x1000>;
				status = "disabled";
			};

			frame@17c29000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17c29000 0x1000>;
				status = "disabled";
			};

			frame@17c2b000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17c2b000 0x1000>;
				status = "disabled";
			};

			frame@17c2d000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x17c2d000 0x1000>;
				status = "disabled";
			};
		};

		apps_rsc: rsc@18200000 {
			compatible = "qcom,rpmh-rsc";
			label = "apps_rsc";
			reg = <0x0 0x18200000 0x0 0x10000>,
				<0x0 0x18210000 0x0 0x10000>,
				<0x0 0x18220000 0x0 0x10000>;
			reg-names = "drv-0", "drv-1", "drv-2";
			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			qcom,tcs-offset = <0xd00>;
			qcom,drv-id = <2>;
			qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
					  <WAKE_TCS 3>, <CONTROL_TCS 1>;
			power-domains = <&CLUSTER_PD>;

			rpmhcc: clock-controller {
				compatible = "qcom,sm6350-rpmh-clk";
				#clock-cells = <1>;
				clock-names = "xo";
				clocks = <&xo_board>;
			};

			rpmhpd: power-controller {
				compatible = "qcom,sm6350-rpmhpd";
				#power-domain-cells = <1>;
				operating-points-v2 = <&rpmhpd_opp_table>;

				rpmhpd_opp_table: opp-table {
					compatible = "operating-points-v2";

					rpmhpd_opp_ret: opp1 {
						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
					};

					rpmhpd_opp_min_svs: opp2 {
						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
					};

					rpmhpd_opp_low_svs: opp3 {
						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
					};

					rpmhpd_opp_svs: opp4 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
					};

					rpmhpd_opp_svs_l1: opp5 {
						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
					};

					rpmhpd_opp_nom: opp6 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
					};

					rpmhpd_opp_nom_l1: opp7 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
					};

					rpmhpd_opp_nom_l2: opp8 {
						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
					};

					rpmhpd_opp_turbo: opp9 {
						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
					};

					rpmhpd_opp_turbo_l1: opp10 {
						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
					};
				};
			};

			apps_bcm_voter: bcm-voter {
				compatible = "qcom,bcm-voter";
			};
		};

		osm_l3: interconnect@18321000 {
			compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3";
			reg = <0x0 0x18321000 0x0 0x1000>;

			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
			clock-names = "xo", "alternate";

			#interconnect-cells = <1>;
		};

		cpufreq_hw: cpufreq@18323000 {
			compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw";
			reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
			reg-names = "freq-domain0", "freq-domain1";
			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
			clock-names = "xo", "alternate";

			#freq-domain-cells = <1>;
			#clock-cells = <1>;
		};

		wifi: wifi@18800000 {
			compatible = "qcom,wcn3990-wifi";
			reg = <0 0x18800000 0 0x800000>;
			reg-names = "membase";
			memory-region = <&wlan_fw_mem>;
			interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
			iommus = <&apps_smmu 0x20 0x1>;
			qcom,msa-fixed-perm;
			status = "disabled";
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		clock-frequency = <19200000>;
		interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
	};
};