162306a36Sopenharmony_ci/* 262306a36Sopenharmony_ci * ARM Ltd. 362306a36Sopenharmony_ci * 462306a36Sopenharmony_ci * ARMv8 Foundation model DTS (GICv3 configuration) 562306a36Sopenharmony_ci */ 662306a36Sopenharmony_ci 762306a36Sopenharmony_ci/ { 862306a36Sopenharmony_ci gic: interrupt-controller@2f000000 { 962306a36Sopenharmony_ci compatible = "arm,gic-v3"; 1062306a36Sopenharmony_ci #interrupt-cells = <3>; 1162306a36Sopenharmony_ci #address-cells = <1>; 1262306a36Sopenharmony_ci #size-cells = <1>; 1362306a36Sopenharmony_ci ranges = <0x0 0x0 0x2f000000 0x100000>; 1462306a36Sopenharmony_ci interrupt-controller; 1562306a36Sopenharmony_ci reg = <0x0 0x2f000000 0x0 0x10000>, 1662306a36Sopenharmony_ci <0x0 0x2f100000 0x0 0x200000>, 1762306a36Sopenharmony_ci <0x0 0x2c000000 0x0 0x2000>, 1862306a36Sopenharmony_ci <0x0 0x2c010000 0x0 0x2000>, 1962306a36Sopenharmony_ci <0x0 0x2c02f000 0x0 0x2000>; 2062306a36Sopenharmony_ci interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2162306a36Sopenharmony_ci 2262306a36Sopenharmony_ci its: msi-controller@2f020000 { 2362306a36Sopenharmony_ci compatible = "arm,gic-v3-its"; 2462306a36Sopenharmony_ci msi-controller; 2562306a36Sopenharmony_ci #msi-cells = <1>; 2662306a36Sopenharmony_ci reg = <0x20000 0x20000>; 2762306a36Sopenharmony_ci }; 2862306a36Sopenharmony_ci }; 2962306a36Sopenharmony_ci}; 30