162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright (C) 2020 Marek Vasut <marex@denx.de> 462306a36Sopenharmony_ci */ 562306a36Sopenharmony_ci 662306a36Sopenharmony_ci#include <dt-bindings/input/input.h> 762306a36Sopenharmony_ci#include <dt-bindings/pwm/pwm.h> 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci/ { 1062306a36Sopenharmony_ci aliases { 1162306a36Sopenharmony_ci serial0 = &uart4; 1262306a36Sopenharmony_ci serial1 = &usart3; 1362306a36Sopenharmony_ci serial2 = &uart8; 1462306a36Sopenharmony_ci }; 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci chosen { 1762306a36Sopenharmony_ci stdout-path = "serial0:115200n8"; 1862306a36Sopenharmony_ci }; 1962306a36Sopenharmony_ci}; 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ci&adc { 2262306a36Sopenharmony_ci status = "disabled"; 2362306a36Sopenharmony_ci}; 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ci&dac { 2662306a36Sopenharmony_ci status = "disabled"; 2762306a36Sopenharmony_ci}; 2862306a36Sopenharmony_ci 2962306a36Sopenharmony_ci&gpiob { 3062306a36Sopenharmony_ci /* 3162306a36Sopenharmony_ci * NOTE: On DRC02, the RS485_RX_En is controlled by a separate 3262306a36Sopenharmony_ci * GPIO line, however the STM32 UART driver assumes RX happens 3362306a36Sopenharmony_ci * during TX anyway and that it only controls drive enable DE 3462306a36Sopenharmony_ci * line. Hence, the RX is always enabled here. 3562306a36Sopenharmony_ci */ 3662306a36Sopenharmony_ci rs485-rx-en-hog { 3762306a36Sopenharmony_ci gpio-hog; 3862306a36Sopenharmony_ci gpios = <8 0>; 3962306a36Sopenharmony_ci output-low; 4062306a36Sopenharmony_ci line-name = "rs485-rx-en"; 4162306a36Sopenharmony_ci }; 4262306a36Sopenharmony_ci}; 4362306a36Sopenharmony_ci 4462306a36Sopenharmony_ci&gpiod { 4562306a36Sopenharmony_ci gpio-line-names = "", "", "", "", 4662306a36Sopenharmony_ci "", "", "DHCOM-B", "", 4762306a36Sopenharmony_ci "", "", "", "DRC02-Out1", 4862306a36Sopenharmony_ci "DRC02-Out2", "", "", ""; 4962306a36Sopenharmony_ci}; 5062306a36Sopenharmony_ci 5162306a36Sopenharmony_ci&gpioi { 5262306a36Sopenharmony_ci gpio-line-names = "DRC02-In1", "DHCOM-O", "DHCOM-H", "DHCOM-I", 5362306a36Sopenharmony_ci "DHCOM-R", "DHCOM-M", "", "", 5462306a36Sopenharmony_ci "DRC02-In2", "", "", "", 5562306a36Sopenharmony_ci "", "", "", ""; 5662306a36Sopenharmony_ci 5762306a36Sopenharmony_ci /* 5862306a36Sopenharmony_ci * NOTE: The USB Hub on the DRC02 needs a reset signal to be 5962306a36Sopenharmony_ci * pulled high in order to be detected by the USB Controller. 6062306a36Sopenharmony_ci * This signal should be handled by USB power sequencing in 6162306a36Sopenharmony_ci * order to reset the Hub when USB bus is powered down, but 6262306a36Sopenharmony_ci * so far there is no such functionality. 6362306a36Sopenharmony_ci */ 6462306a36Sopenharmony_ci usb-hub-hog { 6562306a36Sopenharmony_ci gpio-hog; 6662306a36Sopenharmony_ci gpios = <2 0>; 6762306a36Sopenharmony_ci output-high; 6862306a36Sopenharmony_ci line-name = "usb-hub-reset"; 6962306a36Sopenharmony_ci }; 7062306a36Sopenharmony_ci}; 7162306a36Sopenharmony_ci 7262306a36Sopenharmony_ci&i2c2 { 7362306a36Sopenharmony_ci pinctrl-names = "default"; 7462306a36Sopenharmony_ci pinctrl-0 = <&i2c2_pins_a>; 7562306a36Sopenharmony_ci i2c-scl-rising-time-ns = <185>; 7662306a36Sopenharmony_ci i2c-scl-falling-time-ns = <20>; 7762306a36Sopenharmony_ci status = "okay"; 7862306a36Sopenharmony_ci /* spare dmas for other usage */ 7962306a36Sopenharmony_ci /delete-property/dmas; 8062306a36Sopenharmony_ci /delete-property/dma-names; 8162306a36Sopenharmony_ci status = "okay"; 8262306a36Sopenharmony_ci 8362306a36Sopenharmony_ci eeprom@50 { 8462306a36Sopenharmony_ci compatible = "atmel,24c04"; 8562306a36Sopenharmony_ci reg = <0x50>; 8662306a36Sopenharmony_ci pagesize = <16>; 8762306a36Sopenharmony_ci }; 8862306a36Sopenharmony_ci}; 8962306a36Sopenharmony_ci 9062306a36Sopenharmony_ci&i2c4 { 9162306a36Sopenharmony_ci touchscreen@49 { 9262306a36Sopenharmony_ci status = "disabled"; 9362306a36Sopenharmony_ci }; 9462306a36Sopenharmony_ci}; 9562306a36Sopenharmony_ci 9662306a36Sopenharmony_ci&i2c5 { /* TP7/TP8 */ 9762306a36Sopenharmony_ci pinctrl-names = "default"; 9862306a36Sopenharmony_ci pinctrl-0 = <&i2c5_pins_a>; 9962306a36Sopenharmony_ci i2c-scl-rising-time-ns = <185>; 10062306a36Sopenharmony_ci i2c-scl-falling-time-ns = <20>; 10162306a36Sopenharmony_ci status = "okay"; 10262306a36Sopenharmony_ci /* spare dmas for other usage */ 10362306a36Sopenharmony_ci /delete-property/dmas; 10462306a36Sopenharmony_ci /delete-property/dma-names; 10562306a36Sopenharmony_ci}; 10662306a36Sopenharmony_ci 10762306a36Sopenharmony_ci&sdmmc3 { 10862306a36Sopenharmony_ci /* 10962306a36Sopenharmony_ci * On DRC02, the SoM does not have SDIO WiFi. The pins 11062306a36Sopenharmony_ci * are used for on-board microSD slot instead. 11162306a36Sopenharmony_ci */ 11262306a36Sopenharmony_ci /delete-property/broken-cd; 11362306a36Sopenharmony_ci cd-gpios = <&gpioi 10 GPIO_ACTIVE_HIGH>; 11462306a36Sopenharmony_ci disable-wp; 11562306a36Sopenharmony_ci}; 11662306a36Sopenharmony_ci 11762306a36Sopenharmony_ci&spi1 { 11862306a36Sopenharmony_ci pinctrl-names = "default"; 11962306a36Sopenharmony_ci pinctrl-0 = <&spi1_pins_a>; 12062306a36Sopenharmony_ci cs-gpios = <&gpioz 3 0>; 12162306a36Sopenharmony_ci /* Use PIO for the display */ 12262306a36Sopenharmony_ci /delete-property/dmas; 12362306a36Sopenharmony_ci /delete-property/dma-names; 12462306a36Sopenharmony_ci status = "disabled"; /* Enable once there is display driver */ 12562306a36Sopenharmony_ci /* 12662306a36Sopenharmony_ci * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are 12762306a36Sopenharmony_ci * also connected to the display board connector. 12862306a36Sopenharmony_ci */ 12962306a36Sopenharmony_ci}; 13062306a36Sopenharmony_ci 13162306a36Sopenharmony_ci&usart3 { 13262306a36Sopenharmony_ci pinctrl-names = "default"; 13362306a36Sopenharmony_ci pinctrl-0 = <&usart3_pins_a>; 13462306a36Sopenharmony_ci /delete-property/dmas; 13562306a36Sopenharmony_ci /delete-property/dma-names; 13662306a36Sopenharmony_ci status = "okay"; 13762306a36Sopenharmony_ci}; 13862306a36Sopenharmony_ci 13962306a36Sopenharmony_ci/* 14062306a36Sopenharmony_ci * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1), 14162306a36Sopenharmony_ci * however the STM32MP1 pinmux cannot map them to UART4 . 14262306a36Sopenharmony_ci */ 14362306a36Sopenharmony_ci 14462306a36Sopenharmony_ci&uart8 { /* RS485 */ 14562306a36Sopenharmony_ci linux,rs485-enabled-at-boot-time; 14662306a36Sopenharmony_ci pinctrl-names = "default"; 14762306a36Sopenharmony_ci pinctrl-0 = <&uart8_pins_a>; 14862306a36Sopenharmony_ci rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>; 14962306a36Sopenharmony_ci /delete-property/dmas; 15062306a36Sopenharmony_ci /delete-property/dma-names; 15162306a36Sopenharmony_ci status = "okay"; 15262306a36Sopenharmony_ci}; 15362306a36Sopenharmony_ci 15462306a36Sopenharmony_ci&usbh_ehci { 15562306a36Sopenharmony_ci phys = <&usbphyc_port0>; 15662306a36Sopenharmony_ci status = "okay"; 15762306a36Sopenharmony_ci}; 15862306a36Sopenharmony_ci 15962306a36Sopenharmony_ci&usbphyc { 16062306a36Sopenharmony_ci status = "okay"; 16162306a36Sopenharmony_ci}; 16262306a36Sopenharmony_ci 16362306a36Sopenharmony_ci&usbphyc_port0 { 16462306a36Sopenharmony_ci phy-supply = <&vdd_usb>; 16562306a36Sopenharmony_ci}; 16662306a36Sopenharmony_ci 16762306a36Sopenharmony_ci&usbphyc_port1 { 16862306a36Sopenharmony_ci phy-supply = <&vdd_usb>; 16962306a36Sopenharmony_ci}; 170