162306a36Sopenharmony_ci// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright 2018-2022 TQ-Systems GmbH 462306a36Sopenharmony_ci * Author: Markus Niebel <Markus.Niebel@tq-group.com> 562306a36Sopenharmony_ci */ 662306a36Sopenharmony_ci 762306a36Sopenharmony_ci#include "imx6ul.dtsi" 862306a36Sopenharmony_ci#include "imx6ul-tqma6ul-common.dtsi" 962306a36Sopenharmony_ci#include "imx6ul-tqma6ulxl-common.dtsi" 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci/ { 1262306a36Sopenharmony_ci model = "TQ-Systems TQMa6UL2L SoM"; 1362306a36Sopenharmony_ci compatible = "tq,imx6ul-tqma6ul2l", "fsl,imx6ul"; 1462306a36Sopenharmony_ci}; 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci&usdhc2 { 1762306a36Sopenharmony_ci fsl,tuning-step = <6>; 1862306a36Sopenharmony_ci}; 1962306a36Sopenharmony_ci 2062306a36Sopenharmony_ci&iomuxc { 2162306a36Sopenharmony_ci pinctrl_usdhc2: usdhc2grp { 2262306a36Sopenharmony_ci fsl,pins = < 2362306a36Sopenharmony_ci MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x00017051 2462306a36Sopenharmony_ci MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x00017051 2562306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x00017051 2662306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x00017051 2762306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x00017051 2862306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x00017051 2962306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x00017051 3062306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x00017051 3162306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x00017051 3262306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x00017051 3362306a36Sopenharmony_ci /* rst */ 3462306a36Sopenharmony_ci MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 3562306a36Sopenharmony_ci >; 3662306a36Sopenharmony_ci }; 3762306a36Sopenharmony_ci 3862306a36Sopenharmony_ci pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 3962306a36Sopenharmony_ci fsl,pins = < 4062306a36Sopenharmony_ci MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170e1 4162306a36Sopenharmony_ci MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 4262306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 4362306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 4462306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 4562306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 4662306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 4762306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 4862306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 4962306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 5062306a36Sopenharmony_ci /* rst */ 5162306a36Sopenharmony_ci MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 5262306a36Sopenharmony_ci >; 5362306a36Sopenharmony_ci }; 5462306a36Sopenharmony_ci 5562306a36Sopenharmony_ci pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 5662306a36Sopenharmony_ci fsl,pins = < 5762306a36Sopenharmony_ci MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x000170f9 5862306a36Sopenharmony_ci MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x000170f1 5962306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x000170f1 6062306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x000170f1 6162306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x000170f1 6262306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x000170f1 6362306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x000170f1 6462306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x000170f1 6562306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x000170f1 6662306a36Sopenharmony_ci MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x000170f1 6762306a36Sopenharmony_ci /* rst */ 6862306a36Sopenharmony_ci MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x0001b051 6962306a36Sopenharmony_ci >; 7062306a36Sopenharmony_ci }; 7162306a36Sopenharmony_ci}; 72