xref: /kernel/linux/linux-6.6/scripts/dtc/include-prefixes/arm/nxp/imx/imx6qdl-phytec-mira-peb-av-02.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2018 PHYTEC Messtechnik
 * Author: Christian Hemp <c.hemp@phytec.de>
 */

/ {
	display: display0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,imx-parallel-display";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_disp0>;
		interface-pix-fmt = "rgb24";
		status = "disabled";

		port@0 {
			reg = <0>;

			display0_in: endpoint {
				remote-endpoint = <&ipu1_di0_disp0>;
			};
		};

		port@1 {
			reg = <1>;

			display0_out: endpoint {
				remote-endpoint = <&peb_panel_lcd_in>;
			};
		};
	};

	panel-lcd {
		compatible = "edt,etm0700g0edh6";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_disp0_pwr>;
		power-supply = <&reg_display>;
		enable-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
		backlight = <&backlight>;
		status = "disabled";

		port {
			peb_panel_lcd_in: endpoint {
				remote-endpoint = <&display0_out>;
			};
		};
	};

	reg_display: regulator-peb-display {
		compatible = "regulator-fixed";
		regulator-name = "peb-display";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

&i2c1 {
	edt_ft5x06: touchscreen@38 {
		compatible = "edt,edt-ft5406";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_edt_ft5x06>;
		reg = <0x38>;
		interrupt-parent = <&gpio3>;
		interrupts = <2 IRQ_TYPE_NONE>;
		status = "disabled";
	};
};

&ipu1_di0_disp0 {
	remote-endpoint = <&display0_in>;
};

&iomuxc {
	pinctrl_disp0: disp0grp {
		fsl,pins = <
			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	0x10
			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02		0x10
			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03		0x10
			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0x1b080
			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00	0x10
			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01	0x10
			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02	0x10
			MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03	0x10
			MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04	0x10
			MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05	0x10
			MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06	0x10
			MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07	0x10
			MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08	0x10
			MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09	0x10
			MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10	0x10
			MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11	0x10
			MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12	0x10
			MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13	0x10
			MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14	0x10
			MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15	0x10
			MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16	0x10
			MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17	0x10
			MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18	0x10
			MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19	0x10
			MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20	0x10
			MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21	0x10
			MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22	0x10
			MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23	0x10
		>;
	};

	pinctrl_disp0_pwr: disp0pwrgrp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D22__GPIO3_IO22			0x1b0b0
		>;
	};

	pinctrl_edt_ft5x06: edtft5x06grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_DA2__GPIO3_IO02			0xb0b1
		>;
	};
};