162306a36Sopenharmony_ci// SPDX-License-Identifier: ISC 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Device Tree include file for Intel reference designs for the 462306a36Sopenharmony_ci * XScale Network Processors in the IXP 4xx series. Common device 562306a36Sopenharmony_ci * set-up for IXDP425, IXCDP1100, KIXRP435 and IXDP465. 662306a36Sopenharmony_ci */ 762306a36Sopenharmony_ci 862306a36Sopenharmony_ci/ { 962306a36Sopenharmony_ci memory@0 { 1062306a36Sopenharmony_ci /* 1162306a36Sopenharmony_ci * The board supports up to 256 MB of memory. Here we put in 1262306a36Sopenharmony_ci * 64 MB and this may be modified by the boot loader. 1362306a36Sopenharmony_ci */ 1462306a36Sopenharmony_ci device_type = "memory"; 1562306a36Sopenharmony_ci reg = <0x00000000 0x4000000>; 1662306a36Sopenharmony_ci }; 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ci chosen { 1962306a36Sopenharmony_ci bootargs = "console=ttyS0,115200n8"; 2062306a36Sopenharmony_ci stdout-path = "uart0:115200n8"; 2162306a36Sopenharmony_ci }; 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ci aliases { 2462306a36Sopenharmony_ci serial0 = &uart0; 2562306a36Sopenharmony_ci }; 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_ci i2c { 2862306a36Sopenharmony_ci compatible = "i2c-gpio"; 2962306a36Sopenharmony_ci sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; 3062306a36Sopenharmony_ci scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; 3162306a36Sopenharmony_ci #address-cells = <1>; 3262306a36Sopenharmony_ci #size-cells = <0>; 3362306a36Sopenharmony_ci 3462306a36Sopenharmony_ci eeprom@50 { 3562306a36Sopenharmony_ci /* 3662306a36Sopenharmony_ci * Philips PCF8582C-2T/03 512byte I2C EEPROM 3762306a36Sopenharmony_ci * should behave like an Atmel 24c04. 3862306a36Sopenharmony_ci */ 3962306a36Sopenharmony_ci compatible = "atmel,24c04"; 4062306a36Sopenharmony_ci reg = <0x50>; 4162306a36Sopenharmony_ci pagesize = <16>; 4262306a36Sopenharmony_ci size = <512>; 4362306a36Sopenharmony_ci read-only; 4462306a36Sopenharmony_ci }; 4562306a36Sopenharmony_ci }; 4662306a36Sopenharmony_ci 4762306a36Sopenharmony_ci soc { 4862306a36Sopenharmony_ci bus@c4000000 { 4962306a36Sopenharmony_ci /* Flash memory defined per-variant */ 5062306a36Sopenharmony_ci nand-controller@3,0 { 5162306a36Sopenharmony_ci /* Some designs have a NAND on CS3 enable it here if present */ 5262306a36Sopenharmony_ci status = "disabled"; 5362306a36Sopenharmony_ci 5462306a36Sopenharmony_ci /* 5562306a36Sopenharmony_ci * gen_nand needs to be extended and documented to get 5662306a36Sopenharmony_ci * command byte = 1 and address byte = 2 from the device 5762306a36Sopenharmony_ci * tree. 5862306a36Sopenharmony_ci */ 5962306a36Sopenharmony_ci compatible = "gen_nand"; 6062306a36Sopenharmony_ci 6162306a36Sopenharmony_ci /* Expansion bus set-up */ 6262306a36Sopenharmony_ci intel,ixp4xx-eb-t1 = <0>; 6362306a36Sopenharmony_ci intel,ixp4xx-eb-t2 = <0>; 6462306a36Sopenharmony_ci intel,ixp4xx-eb-t3 = <1>; // 1 cycle extra strobe phase 6562306a36Sopenharmony_ci intel,ixp4xx-eb-t4 = <0>; 6662306a36Sopenharmony_ci intel,ixp4xx-eb-t5 = <0>; 6762306a36Sopenharmony_ci intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type 6862306a36Sopenharmony_ci intel,ixp4xx-eb-byte-access-on-halfword = <0>; 6962306a36Sopenharmony_ci intel,ixp4xx-eb-mux-address-and-data = <0>; 7062306a36Sopenharmony_ci intel,ixp4xx-eb-ahb-split-transfers = <0>; 7162306a36Sopenharmony_ci intel,ixp4xx-eb-write-enable = <1>; 7262306a36Sopenharmony_ci intel,ixp4xx-eb-byte-access = <1>; 7362306a36Sopenharmony_ci 7462306a36Sopenharmony_ci /* 512 bytes memory window */ 7562306a36Sopenharmony_ci reg = <3 0x00000000 0x200>; 7662306a36Sopenharmony_ci nand-on-flash-bbt; 7762306a36Sopenharmony_ci nand-ecc-mode = "soft_bch"; 7862306a36Sopenharmony_ci nand-ecc-step-size = <512>; 7962306a36Sopenharmony_ci nand-ecc-strength = <4>; 8062306a36Sopenharmony_ci nce-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* NCE */ 8162306a36Sopenharmony_ci 8262306a36Sopenharmony_ci label = "ixp400 NAND"; 8362306a36Sopenharmony_ci 8462306a36Sopenharmony_ci partitions { 8562306a36Sopenharmony_ci compatible = "fixed-partitions"; 8662306a36Sopenharmony_ci #address-cells = <1>; 8762306a36Sopenharmony_ci #size-cells = <1>; 8862306a36Sopenharmony_ci 8962306a36Sopenharmony_ci fs@0 { 9062306a36Sopenharmony_ci label = "ixp400 NAND FS 0"; 9162306a36Sopenharmony_ci reg = <0x0 0x800000>; 9262306a36Sopenharmony_ci }; 9362306a36Sopenharmony_ci fs@800000 { 9462306a36Sopenharmony_ci label = "ixp400 NAND FS 1"; 9562306a36Sopenharmony_ci reg = <0x800000 0x0>; 9662306a36Sopenharmony_ci }; 9762306a36Sopenharmony_ci }; 9862306a36Sopenharmony_ci }; 9962306a36Sopenharmony_ci }; 10062306a36Sopenharmony_ci 10162306a36Sopenharmony_ci pci@c0000000 { 10262306a36Sopenharmony_ci status = "okay"; 10362306a36Sopenharmony_ci 10462306a36Sopenharmony_ci /* 10562306a36Sopenharmony_ci * Taken from IXDP425 PCI boardfile. 10662306a36Sopenharmony_ci * PCI slots on the BIXMB425BD base card. 10762306a36Sopenharmony_ci * We have up to 4 slots (IDSEL) with 4 swizzled IRQs. 10862306a36Sopenharmony_ci */ 10962306a36Sopenharmony_ci #interrupt-cells = <1>; 11062306a36Sopenharmony_ci interrupt-map-mask = <0xf800 0 0 7>; 11162306a36Sopenharmony_ci interrupt-map = 11262306a36Sopenharmony_ci /* IDSEL 1 */ 11362306a36Sopenharmony_ci <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ 11462306a36Sopenharmony_ci <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */ 11562306a36Sopenharmony_ci <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */ 11662306a36Sopenharmony_ci <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ 11762306a36Sopenharmony_ci /* IDSEL 2 */ 11862306a36Sopenharmony_ci <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ 11962306a36Sopenharmony_ci <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ 12062306a36Sopenharmony_ci <0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */ 12162306a36Sopenharmony_ci <0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */ 12262306a36Sopenharmony_ci /* IDSEL 3 */ 12362306a36Sopenharmony_ci <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */ 12462306a36Sopenharmony_ci <0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */ 12562306a36Sopenharmony_ci <0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */ 12662306a36Sopenharmony_ci <0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */ 12762306a36Sopenharmony_ci /* IDSEL 4 */ 12862306a36Sopenharmony_ci <0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */ 12962306a36Sopenharmony_ci <0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */ 13062306a36Sopenharmony_ci <0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */ 13162306a36Sopenharmony_ci <0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */ 13262306a36Sopenharmony_ci }; 13362306a36Sopenharmony_ci }; 13462306a36Sopenharmony_ci}; 135