162306a36Sopenharmony_ci#include "bcm283x.dtsi" 262306a36Sopenharmony_ci#include "bcm2835-common.dtsi" 362306a36Sopenharmony_ci 462306a36Sopenharmony_ci/ { 562306a36Sopenharmony_ci compatible = "brcm,bcm2837"; 662306a36Sopenharmony_ci 762306a36Sopenharmony_ci soc { 862306a36Sopenharmony_ci ranges = <0x7e000000 0x3f000000 0x1000000>, 962306a36Sopenharmony_ci <0x40000000 0x40000000 0x00001000>; 1062306a36Sopenharmony_ci dma-ranges = <0xc0000000 0x00000000 0x3f000000>; 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci local_intc: local_intc@40000000 { 1362306a36Sopenharmony_ci compatible = "brcm,bcm2836-l1-intc"; 1462306a36Sopenharmony_ci reg = <0x40000000 0x100>; 1562306a36Sopenharmony_ci interrupt-controller; 1662306a36Sopenharmony_ci #interrupt-cells = <2>; 1762306a36Sopenharmony_ci interrupt-parent = <&local_intc>; 1862306a36Sopenharmony_ci }; 1962306a36Sopenharmony_ci }; 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ci arm-pmu { 2262306a36Sopenharmony_ci compatible = "arm,cortex-a53-pmu"; 2362306a36Sopenharmony_ci interrupt-parent = <&local_intc>; 2462306a36Sopenharmony_ci interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 2562306a36Sopenharmony_ci }; 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_ci timer { 2862306a36Sopenharmony_ci compatible = "arm,armv7-timer"; 2962306a36Sopenharmony_ci interrupt-parent = <&local_intc>; 3062306a36Sopenharmony_ci interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI 3162306a36Sopenharmony_ci <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI 3262306a36Sopenharmony_ci <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI 3362306a36Sopenharmony_ci <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI 3462306a36Sopenharmony_ci always-on; 3562306a36Sopenharmony_ci }; 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ci cpus: cpus { 3862306a36Sopenharmony_ci #address-cells = <1>; 3962306a36Sopenharmony_ci #size-cells = <0>; 4062306a36Sopenharmony_ci enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit 4162306a36Sopenharmony_ci 4262306a36Sopenharmony_ci /* Source for d/i-cache-line-size and d/i-cache-sets 4362306a36Sopenharmony_ci * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system 4462306a36Sopenharmony_ci * /about-the-l1-memory-system?lang=en 4562306a36Sopenharmony_ci * 4662306a36Sopenharmony_ci * Source for d/i-cache-size 4762306a36Sopenharmony_ci * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks 4862306a36Sopenharmony_ci */ 4962306a36Sopenharmony_ci cpu0: cpu@0 { 5062306a36Sopenharmony_ci device_type = "cpu"; 5162306a36Sopenharmony_ci compatible = "arm,cortex-a53"; 5262306a36Sopenharmony_ci reg = <0>; 5362306a36Sopenharmony_ci enable-method = "spin-table"; 5462306a36Sopenharmony_ci cpu-release-addr = <0x0 0x000000d8>; 5562306a36Sopenharmony_ci d-cache-size = <0x8000>; 5662306a36Sopenharmony_ci d-cache-line-size = <64>; 5762306a36Sopenharmony_ci d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 5862306a36Sopenharmony_ci i-cache-size = <0x8000>; 5962306a36Sopenharmony_ci i-cache-line-size = <64>; 6062306a36Sopenharmony_ci i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 6162306a36Sopenharmony_ci next-level-cache = <&l2>; 6262306a36Sopenharmony_ci }; 6362306a36Sopenharmony_ci 6462306a36Sopenharmony_ci cpu1: cpu@1 { 6562306a36Sopenharmony_ci device_type = "cpu"; 6662306a36Sopenharmony_ci compatible = "arm,cortex-a53"; 6762306a36Sopenharmony_ci reg = <1>; 6862306a36Sopenharmony_ci enable-method = "spin-table"; 6962306a36Sopenharmony_ci cpu-release-addr = <0x0 0x000000e0>; 7062306a36Sopenharmony_ci d-cache-size = <0x8000>; 7162306a36Sopenharmony_ci d-cache-line-size = <64>; 7262306a36Sopenharmony_ci d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 7362306a36Sopenharmony_ci i-cache-size = <0x8000>; 7462306a36Sopenharmony_ci i-cache-line-size = <64>; 7562306a36Sopenharmony_ci i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 7662306a36Sopenharmony_ci next-level-cache = <&l2>; 7762306a36Sopenharmony_ci }; 7862306a36Sopenharmony_ci 7962306a36Sopenharmony_ci cpu2: cpu@2 { 8062306a36Sopenharmony_ci device_type = "cpu"; 8162306a36Sopenharmony_ci compatible = "arm,cortex-a53"; 8262306a36Sopenharmony_ci reg = <2>; 8362306a36Sopenharmony_ci enable-method = "spin-table"; 8462306a36Sopenharmony_ci cpu-release-addr = <0x0 0x000000e8>; 8562306a36Sopenharmony_ci d-cache-size = <0x8000>; 8662306a36Sopenharmony_ci d-cache-line-size = <64>; 8762306a36Sopenharmony_ci d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 8862306a36Sopenharmony_ci i-cache-size = <0x8000>; 8962306a36Sopenharmony_ci i-cache-line-size = <64>; 9062306a36Sopenharmony_ci i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 9162306a36Sopenharmony_ci next-level-cache = <&l2>; 9262306a36Sopenharmony_ci }; 9362306a36Sopenharmony_ci 9462306a36Sopenharmony_ci cpu3: cpu@3 { 9562306a36Sopenharmony_ci device_type = "cpu"; 9662306a36Sopenharmony_ci compatible = "arm,cortex-a53"; 9762306a36Sopenharmony_ci reg = <3>; 9862306a36Sopenharmony_ci enable-method = "spin-table"; 9962306a36Sopenharmony_ci cpu-release-addr = <0x0 0x000000f0>; 10062306a36Sopenharmony_ci d-cache-size = <0x8000>; 10162306a36Sopenharmony_ci d-cache-line-size = <64>; 10262306a36Sopenharmony_ci d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set 10362306a36Sopenharmony_ci i-cache-size = <0x8000>; 10462306a36Sopenharmony_ci i-cache-line-size = <64>; 10562306a36Sopenharmony_ci i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set 10662306a36Sopenharmony_ci next-level-cache = <&l2>; 10762306a36Sopenharmony_ci }; 10862306a36Sopenharmony_ci 10962306a36Sopenharmony_ci /* Source for cache-line-size + cache-sets 11062306a36Sopenharmony_ci * https://developer.arm.com/documentation/ddi0500 11162306a36Sopenharmony_ci * /e/level-2-memory-system/about-the-l2-memory-system?lang=en 11262306a36Sopenharmony_ci * Source for cache-size 11362306a36Sopenharmony_ci * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf 11462306a36Sopenharmony_ci */ 11562306a36Sopenharmony_ci l2: l2-cache0 { 11662306a36Sopenharmony_ci compatible = "cache"; 11762306a36Sopenharmony_ci cache-unified; 11862306a36Sopenharmony_ci cache-size = <0x80000>; 11962306a36Sopenharmony_ci cache-line-size = <64>; 12062306a36Sopenharmony_ci cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set 12162306a36Sopenharmony_ci cache-level = <2>; 12262306a36Sopenharmony_ci }; 12362306a36Sopenharmony_ci }; 12462306a36Sopenharmony_ci}; 12562306a36Sopenharmony_ci 12662306a36Sopenharmony_ci/* Make the BCM2835-style global interrupt controller be a child of the 12762306a36Sopenharmony_ci * CPU-local interrupt controller. 12862306a36Sopenharmony_ci */ 12962306a36Sopenharmony_ci&intc { 13062306a36Sopenharmony_ci compatible = "brcm,bcm2836-armctrl-ic"; 13162306a36Sopenharmony_ci reg = <0x7e00b200 0x200>; 13262306a36Sopenharmony_ci interrupt-parent = <&local_intc>; 13362306a36Sopenharmony_ci interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 13462306a36Sopenharmony_ci}; 13562306a36Sopenharmony_ci 13662306a36Sopenharmony_ci&cpu_thermal { 13762306a36Sopenharmony_ci coefficients = <(-538) 412000>; 13862306a36Sopenharmony_ci}; 13962306a36Sopenharmony_ci 14062306a36Sopenharmony_ci/* enable thermal sensor with the correct compatible property set */ 14162306a36Sopenharmony_ci&thermal { 14262306a36Sopenharmony_ci compatible = "brcm,bcm2837-thermal"; 14362306a36Sopenharmony_ci status = "okay"; 14462306a36Sopenharmony_ci}; 145