1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2/* 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * Copyright(c) 2022 Intel Corporation. All rights reserved. 7 */ 8 9#ifndef __INCLUDE_SOUND_SOF_IPC4_HEADER_H__ 10#define __INCLUDE_SOUND_SOF_IPC4_HEADER_H__ 11 12#include <linux/types.h> 13#include <uapi/sound/sof/abi.h> 14 15/* maximum message size for mailbox Tx/Rx */ 16#define SOF_IPC4_MSG_MAX_SIZE 4096 17 18/** \addtogroup sof_uapi uAPI 19 * SOF uAPI specification. 20 * @{ 21 */ 22 23/** 24 * struct sof_ipc4_msg - Placeholder of an IPC4 message 25 * @header_u64: IPC4 header as single u64 number 26 * @primary: Primary, mandatory part of the header 27 * @extension: Extended part of the header, if not used it should be 28 * set to 0 29 * @data_size: Size of data in bytes pointed by @data_ptr 30 * @data_ptr: Pointer to the optional payload of a message 31 */ 32struct sof_ipc4_msg { 33 union { 34 u64 header_u64; 35 struct { 36 u32 primary; 37 u32 extension; 38 }; 39 }; 40 41 size_t data_size; 42 void *data_ptr; 43}; 44 45/** 46 * struct sof_ipc4_tuple - Generic type/ID and parameter tuple 47 * @type: type/ID 48 * @size: size of the @value array in bytes 49 * @value: value for the given type 50 */ 51struct sof_ipc4_tuple { 52 uint32_t type; 53 uint32_t size; 54 uint32_t value[]; 55} __packed; 56 57/* 58 * IPC4 messages have two 32 bit identifier made up as follows :- 59 * 60 * header - msg type, msg id, msg direction ... 61 * extension - extra params such as msg data size in mailbox 62 * 63 * These are sent at the start of the IPC message in the mailbox. Messages 64 * should not be sent in the doorbell (special exceptions for firmware). 65 */ 66 67/* 68 * IPC4 primary header bit allocation for messages 69 * bit 0-23: message type specific 70 * bit 24-28: type: enum sof_ipc4_global_msg if target is SOF_IPC4_FW_GEN_MSG 71 * enum sof_ipc4_module_type if target is SOF_IPC4_MODULE_MSG 72 * bit 29: response - sof_ipc4_msg_dir 73 * bit 30: target - enum sof_ipc4_msg_target 74 * bit 31: reserved, unused 75 */ 76 77/* Value of target field - must fit into 1 bit */ 78enum sof_ipc4_msg_target { 79 /* Global FW message */ 80 SOF_IPC4_FW_GEN_MSG, 81 82 /* Module message */ 83 SOF_IPC4_MODULE_MSG 84}; 85 86/* Value of type field - must fit into 5 bits */ 87enum sof_ipc4_global_msg { 88 SOF_IPC4_GLB_BOOT_CONFIG, 89 SOF_IPC4_GLB_ROM_CONTROL, 90 SOF_IPC4_GLB_IPCGATEWAY_CMD, 91 92 /* 3 .. 12: RESERVED - do not use */ 93 94 SOF_IPC4_GLB_PERF_MEASUREMENTS_CMD = 13, 95 SOF_IPC4_GLB_CHAIN_DMA, 96 97 SOF_IPC4_GLB_LOAD_MULTIPLE_MODULES, 98 SOF_IPC4_GLB_UNLOAD_MULTIPLE_MODULES, 99 100 /* pipeline settings */ 101 SOF_IPC4_GLB_CREATE_PIPELINE, 102 SOF_IPC4_GLB_DELETE_PIPELINE, 103 SOF_IPC4_GLB_SET_PIPELINE_STATE, 104 SOF_IPC4_GLB_GET_PIPELINE_STATE, 105 SOF_IPC4_GLB_GET_PIPELINE_CONTEXT_SIZE, 106 SOF_IPC4_GLB_SAVE_PIPELINE, 107 SOF_IPC4_GLB_RESTORE_PIPELINE, 108 109 /* Loads library (using Code Load or HD/A Host Output DMA) */ 110 SOF_IPC4_GLB_LOAD_LIBRARY, 111 112 /* 25: RESERVED - do not use */ 113 114 SOF_IPC4_GLB_INTERNAL_MESSAGE = 26, 115 116 /* Notification (FW to SW driver) */ 117 SOF_IPC4_GLB_NOTIFICATION, 118 119 /* 28 .. 31: RESERVED - do not use */ 120 121 SOF_IPC4_GLB_TYPE_LAST, 122}; 123 124/* Value of response field - must fit into 1 bit */ 125enum sof_ipc4_msg_dir { 126 SOF_IPC4_MSG_REQUEST, 127 SOF_IPC4_MSG_REPLY, 128}; 129 130enum sof_ipc4_pipeline_state { 131 SOF_IPC4_PIPE_INVALID_STATE, 132 SOF_IPC4_PIPE_UNINITIALIZED, 133 SOF_IPC4_PIPE_RESET, 134 SOF_IPC4_PIPE_PAUSED, 135 SOF_IPC4_PIPE_RUNNING, 136 SOF_IPC4_PIPE_EOS 137}; 138 139/* Generic message fields (bit 24-30) */ 140 141/* encoded to header's msg_tgt field */ 142#define SOF_IPC4_MSG_TARGET_SHIFT 30 143#define SOF_IPC4_MSG_TARGET_MASK BIT(30) 144#define SOF_IPC4_MSG_TARGET(x) ((x) << SOF_IPC4_MSG_TARGET_SHIFT) 145#define SOF_IPC4_MSG_IS_MODULE_MSG(x) ((x) & SOF_IPC4_MSG_TARGET_MASK ? 1 : 0) 146 147/* encoded to header's rsp field */ 148#define SOF_IPC4_MSG_DIR_SHIFT 29 149#define SOF_IPC4_MSG_DIR_MASK BIT(29) 150#define SOF_IPC4_MSG_DIR(x) ((x) << SOF_IPC4_MSG_DIR_SHIFT) 151 152/* encoded to header's type field */ 153#define SOF_IPC4_MSG_TYPE_SHIFT 24 154#define SOF_IPC4_MSG_TYPE_MASK GENMASK(28, 24) 155#define SOF_IPC4_MSG_TYPE_SET(x) (((x) << SOF_IPC4_MSG_TYPE_SHIFT) & \ 156 SOF_IPC4_MSG_TYPE_MASK) 157#define SOF_IPC4_MSG_TYPE_GET(x) (((x) & SOF_IPC4_MSG_TYPE_MASK) >> \ 158 SOF_IPC4_MSG_TYPE_SHIFT) 159 160/* Global message type specific field definitions */ 161 162/* pipeline creation ipc msg */ 163#define SOF_IPC4_GLB_PIPE_INSTANCE_SHIFT 16 164#define SOF_IPC4_GLB_PIPE_INSTANCE_MASK GENMASK(23, 16) 165#define SOF_IPC4_GLB_PIPE_INSTANCE_ID(x) ((x) << SOF_IPC4_GLB_PIPE_INSTANCE_SHIFT) 166 167#define SOF_IPC4_GLB_PIPE_PRIORITY_SHIFT 11 168#define SOF_IPC4_GLB_PIPE_PRIORITY_MASK GENMASK(15, 11) 169#define SOF_IPC4_GLB_PIPE_PRIORITY(x) ((x) << SOF_IPC4_GLB_PIPE_PRIORITY_SHIFT) 170 171#define SOF_IPC4_GLB_PIPE_MEM_SIZE_SHIFT 0 172#define SOF_IPC4_GLB_PIPE_MEM_SIZE_MASK GENMASK(10, 0) 173#define SOF_IPC4_GLB_PIPE_MEM_SIZE(x) ((x) << SOF_IPC4_GLB_PIPE_MEM_SIZE_SHIFT) 174 175#define SOF_IPC4_GLB_PIPE_EXT_LP_SHIFT 0 176#define SOF_IPC4_GLB_PIPE_EXT_LP_MASK BIT(0) 177#define SOF_IPC4_GLB_PIPE_EXT_LP(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_LP_SHIFT) 178 179#define SOF_IPC4_GLB_PIPE_EXT_CORE_ID_SHIFT 20 180#define SOF_IPC4_GLB_PIPE_EXT_CORE_ID_MASK GENMASK(23, 20) 181#define SOF_IPC4_GLB_PIPE_EXT_CORE_ID(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_CORE_ID_SHIFT) 182 183/* pipeline set state ipc msg */ 184#define SOF_IPC4_GLB_PIPE_STATE_ID_SHIFT 16 185#define SOF_IPC4_GLB_PIPE_STATE_ID_MASK GENMASK(23, 16) 186#define SOF_IPC4_GLB_PIPE_STATE_ID(x) ((x) << SOF_IPC4_GLB_PIPE_STATE_ID_SHIFT) 187 188#define SOF_IPC4_GLB_PIPE_STATE_SHIFT 0 189#define SOF_IPC4_GLB_PIPE_STATE_MASK GENMASK(15, 0) 190#define SOF_IPC4_GLB_PIPE_STATE(x) ((x) << SOF_IPC4_GLB_PIPE_STATE_SHIFT) 191 192/* pipeline set state IPC msg extension */ 193#define SOF_IPC4_GLB_PIPE_STATE_EXT_MULTI BIT(0) 194 195/* load library ipc msg */ 196#define SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID_SHIFT 16 197#define SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID(x) ((x) << SOF_IPC4_GLB_LOAD_LIBRARY_LIB_ID_SHIFT) 198 199/* chain dma ipc message */ 200#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_SHIFT 0 201#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_MASK GENMASK(4, 0) 202#define SOF_IPC4_GLB_CHAIN_DMA_HOST_ID(x) (((x) << SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_SHIFT) & \ 203 SOF_IPC4_GLB_CHAIN_DMA_HOST_ID_MASK) 204 205#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_SHIFT 8 206#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_MASK GENMASK(12, 8) 207#define SOF_IPC4_GLB_CHAIN_DMA_LINK_ID(x) (((x) << SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_SHIFT) & \ 208 SOF_IPC4_GLB_CHAIN_DMA_LINK_ID_MASK) 209 210#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_SHIFT 16 211#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_MASK BIT(16) 212#define SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_SHIFT) 213 214#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE_SHIFT 17 215#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE_MASK BIT(17) 216#define SOF_IPC4_GLB_CHAIN_DMA_ENABLE(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_ENABLE_SHIFT) 217 218#define SOF_IPC4_GLB_CHAIN_DMA_SCS_SHIFT 18 219#define SOF_IPC4_GLB_CHAIN_DMA_SCS_MASK BIT(18) 220#define SOF_IPC4_GLB_CHAIN_DMA_SCS(x) (((x) & 1) << SOF_IPC4_GLB_CHAIN_DMA_SCS_SHIFT) 221 222#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_SHIFT 0 223#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_MASK GENMASK(24, 0) 224#define SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE(x) (((x) << \ 225 SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_SHIFT) & \ 226 SOF_IPC4_GLB_EXT_CHAIN_DMA_FIFO_SIZE_MASK) 227 228enum sof_ipc4_channel_config { 229 /* one channel only. */ 230 SOF_IPC4_CHANNEL_CONFIG_MONO, 231 /* L & R. */ 232 SOF_IPC4_CHANNEL_CONFIG_STEREO, 233 /* L, R & LFE; PCM only. */ 234 SOF_IPC4_CHANNEL_CONFIG_2_POINT_1, 235 /* L, C & R; MP3 & AAC only. */ 236 SOF_IPC4_CHANNEL_CONFIG_3_POINT_0, 237 /* L, C, R & LFE; PCM only. */ 238 SOF_IPC4_CHANNEL_CONFIG_3_POINT_1, 239 /* L, R, Ls & Rs; PCM only. */ 240 SOF_IPC4_CHANNEL_CONFIG_QUATRO, 241 /* L, C, R & Cs; MP3 & AAC only. */ 242 SOF_IPC4_CHANNEL_CONFIG_4_POINT_0, 243 /* L, C, R, Ls & Rs. */ 244 SOF_IPC4_CHANNEL_CONFIG_5_POINT_0, 245 /* L, C, R, Ls, Rs & LFE. */ 246 SOF_IPC4_CHANNEL_CONFIG_5_POINT_1, 247 /* one channel replicated in two. */ 248 SOF_IPC4_CHANNEL_CONFIG_DUAL_MONO, 249 /* Stereo (L,R) in 4 slots, 1st stream: [ L, R, -, - ] */ 250 SOF_IPC4_CHANNEL_CONFIG_I2S_DUAL_STEREO_0, 251 /* Stereo (L,R) in 4 slots, 2nd stream: [ -, -, L, R ] */ 252 SOF_IPC4_CHANNEL_CONFIG_I2S_DUAL_STEREO_1, 253 /* L, C, R, Ls, Rs & LFE., LS, RS */ 254 SOF_IPC4_CHANNEL_CONFIG_7_POINT_1, 255}; 256 257enum sof_ipc4_interleaved_style { 258 SOF_IPC4_CHANNELS_INTERLEAVED, 259 SOF_IPC4_CHANNELS_NONINTERLEAVED, 260}; 261 262enum sof_ipc4_sample_type { 263 SOF_IPC4_MSB_INTEGER, /* integer with Most Significant Byte first */ 264 SOF_IPC4_LSB_INTEGER, /* integer with Least Significant Byte first */ 265}; 266 267struct sof_ipc4_audio_format { 268 uint32_t sampling_frequency; 269 uint32_t bit_depth; 270 uint32_t ch_map; 271 uint32_t ch_cfg; /* sof_ipc4_channel_config */ 272 uint32_t interleaving_style; 273 uint32_t fmt_cfg; /* channels_count valid_bit_depth s_type */ 274} __packed __aligned(4); 275 276#define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_SHIFT 0 277#define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_MASK GENMASK(7, 0) 278#define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(x) \ 279 ((x) & SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_MASK) 280#define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_SHIFT 8 281#define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_MASK GENMASK(15, 8) 282#define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(x) \ 283 (((x) & SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_MASK) >> \ 284 SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_SHIFT) 285#define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_SHIFT 16 286#define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_MASK GENMASK(23, 16) 287#define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE(x) \ 288 (((x) & SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_MASK) >> \ 289 SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_SHIFT) 290 291/* Module message type specific field definitions */ 292 293enum sof_ipc4_module_type { 294 SOF_IPC4_MOD_INIT_INSTANCE, 295 SOF_IPC4_MOD_CONFIG_GET, 296 SOF_IPC4_MOD_CONFIG_SET, 297 SOF_IPC4_MOD_LARGE_CONFIG_GET, 298 SOF_IPC4_MOD_LARGE_CONFIG_SET, 299 SOF_IPC4_MOD_BIND, 300 SOF_IPC4_MOD_UNBIND, 301 SOF_IPC4_MOD_SET_DX, 302 SOF_IPC4_MOD_SET_D0IX, 303 SOF_IPC4_MOD_ENTER_MODULE_RESTORE, 304 SOF_IPC4_MOD_EXIT_MODULE_RESTORE, 305 SOF_IPC4_MOD_DELETE_INSTANCE, 306 307 SOF_IPC4_MOD_TYPE_LAST, 308}; 309 310struct sof_ipc4_base_module_cfg { 311 uint32_t cpc; /* the max count of Cycles Per Chunk processing */ 312 uint32_t ibs; /* input Buffer Size (in bytes) */ 313 uint32_t obs; /* output Buffer Size (in bytes) */ 314 uint32_t is_pages; /* number of physical pages used */ 315 struct sof_ipc4_audio_format audio_fmt; 316} __packed __aligned(4); 317 318/* common module ipc msg */ 319#define SOF_IPC4_MOD_INSTANCE_SHIFT 16 320#define SOF_IPC4_MOD_INSTANCE_MASK GENMASK(23, 16) 321#define SOF_IPC4_MOD_INSTANCE(x) ((x) << SOF_IPC4_MOD_INSTANCE_SHIFT) 322 323#define SOF_IPC4_MOD_ID_SHIFT 0 324#define SOF_IPC4_MOD_ID_MASK GENMASK(15, 0) 325#define SOF_IPC4_MOD_ID(x) ((x) << SOF_IPC4_MOD_ID_SHIFT) 326 327/* init module ipc msg */ 328#define SOF_IPC4_MOD_EXT_PARAM_SIZE_SHIFT 0 329#define SOF_IPC4_MOD_EXT_PARAM_SIZE_MASK GENMASK(15, 0) 330#define SOF_IPC4_MOD_EXT_PARAM_SIZE(x) ((x) << SOF_IPC4_MOD_EXT_PARAM_SIZE_SHIFT) 331 332#define SOF_IPC4_MOD_EXT_PPL_ID_SHIFT 16 333#define SOF_IPC4_MOD_EXT_PPL_ID_MASK GENMASK(23, 16) 334#define SOF_IPC4_MOD_EXT_PPL_ID(x) ((x) << SOF_IPC4_MOD_EXT_PPL_ID_SHIFT) 335 336#define SOF_IPC4_MOD_EXT_CORE_ID_SHIFT 24 337#define SOF_IPC4_MOD_EXT_CORE_ID_MASK GENMASK(27, 24) 338#define SOF_IPC4_MOD_EXT_CORE_ID(x) ((x) << SOF_IPC4_MOD_EXT_CORE_ID_SHIFT) 339 340#define SOF_IPC4_MOD_EXT_DOMAIN_SHIFT 28 341#define SOF_IPC4_MOD_EXT_DOMAIN_MASK BIT(28) 342#define SOF_IPC4_MOD_EXT_DOMAIN(x) ((x) << SOF_IPC4_MOD_EXT_DOMAIN_SHIFT) 343 344/* bind/unbind module ipc msg */ 345#define SOF_IPC4_MOD_EXT_DST_MOD_ID_SHIFT 0 346#define SOF_IPC4_MOD_EXT_DST_MOD_ID_MASK GENMASK(15, 0) 347#define SOF_IPC4_MOD_EXT_DST_MOD_ID(x) ((x) << SOF_IPC4_MOD_EXT_DST_MOD_ID_SHIFT) 348 349#define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_SHIFT 16 350#define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_MASK GENMASK(23, 16) 351#define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE(x) ((x) << SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_SHIFT) 352 353#define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_SHIFT 24 354#define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_MASK GENMASK(26, 24) 355#define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID(x) ((x) << SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_SHIFT) 356 357#define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_SHIFT 27 358#define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_MASK GENMASK(29, 27) 359#define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID(x) ((x) << SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_SHIFT) 360 361#define MOD_ENABLE_LOG 6 362#define MOD_SYSTEM_TIME 20 363 364/* set module large config */ 365#define SOF_IPC4_MOD_EXT_MSG_SIZE_SHIFT 0 366#define SOF_IPC4_MOD_EXT_MSG_SIZE_MASK GENMASK(19, 0) 367#define SOF_IPC4_MOD_EXT_MSG_SIZE(x) ((x) << SOF_IPC4_MOD_EXT_MSG_SIZE_SHIFT) 368 369#define SOF_IPC4_MOD_EXT_MSG_PARAM_ID_SHIFT 20 370#define SOF_IPC4_MOD_EXT_MSG_PARAM_ID_MASK GENMASK(27, 20) 371#define SOF_IPC4_MOD_EXT_MSG_PARAM_ID(x) ((x) << SOF_IPC4_MOD_EXT_MSG_PARAM_ID_SHIFT) 372 373#define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_SHIFT 28 374#define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_MASK BIT(28) 375#define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK(x) ((x) << SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_SHIFT) 376 377#define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_SHIFT 29 378#define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_MASK BIT(29) 379#define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK(x) ((x) << SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_SHIFT) 380 381/* Init instance messagees */ 382#define SOF_IPC4_MOD_INIT_BASEFW_MOD_ID 0 383#define SOF_IPC4_MOD_INIT_BASEFW_INSTANCE_ID 0 384 385enum sof_ipc4_base_fw_params { 386 SOF_IPC4_FW_PARAM_ENABLE_LOGS = 6, 387 SOF_IPC4_FW_PARAM_FW_CONFIG, 388 SOF_IPC4_FW_PARAM_HW_CONFIG_GET, 389 SOF_IPC4_FW_PARAM_MODULES_INFO_GET, 390 SOF_IPC4_FW_PARAM_LIBRARIES_INFO_GET = 16, 391 SOF_IPC4_FW_PARAM_SYSTEM_TIME = 20, 392}; 393 394enum sof_ipc4_fw_config_params { 395 SOF_IPC4_FW_CFG_FW_VERSION, 396 SOF_IPC4_FW_CFG_MEMORY_RECLAIMED, 397 SOF_IPC4_FW_CFG_SLOW_CLOCK_FREQ_HZ, 398 SOF_IPC4_FW_CFG_FAST_CLOCK_FREQ_HZ, 399 SOF_IPC4_FW_CFG_DMA_BUFFER_CONFIG, 400 SOF_IPC4_FW_CFG_ALH_SUPPORT_LEVEL, 401 SOF_IPC4_FW_CFG_DL_MAILBOX_BYTES, 402 SOF_IPC4_FW_CFG_UL_MAILBOX_BYTES, 403 SOF_IPC4_FW_CFG_TRACE_LOG_BYTES, 404 SOF_IPC4_FW_CFG_MAX_PPL_COUNT, 405 SOF_IPC4_FW_CFG_MAX_ASTATE_COUNT, 406 SOF_IPC4_FW_CFG_MAX_MODULE_PIN_COUNT, 407 SOF_IPC4_FW_CFG_MODULES_COUNT, 408 SOF_IPC4_FW_CFG_MAX_MOD_INST_COUNT, 409 SOF_IPC4_FW_CFG_MAX_LL_TASKS_PER_PRI_COUNT, 410 SOF_IPC4_FW_CFG_LL_PRI_COUNT, 411 SOF_IPC4_FW_CFG_MAX_DP_TASKS_COUNT, 412 SOF_IPC4_FW_CFG_MAX_LIBS_COUNT, 413 SOF_IPC4_FW_CFG_SCHEDULER_CONFIG, 414 SOF_IPC4_FW_CFG_XTAL_FREQ_HZ, 415 SOF_IPC4_FW_CFG_CLOCKS_CONFIG, 416 SOF_IPC4_FW_CFG_RESERVED, 417 SOF_IPC4_FW_CFG_POWER_GATING_POLICY, 418 SOF_IPC4_FW_CFG_ASSERT_MODE, 419}; 420 421struct sof_ipc4_fw_version { 422 uint16_t major; 423 uint16_t minor; 424 uint16_t hotfix; 425 uint16_t build; 426} __packed; 427 428/* Payload data for SOF_IPC4_MOD_SET_DX */ 429struct sof_ipc4_dx_state_info { 430 /* core(s) to apply the change */ 431 uint32_t core_mask; 432 /* core state: 0: put core_id to D3; 1: put core_id to D0 */ 433 uint32_t dx_mask; 434} __packed __aligned(4); 435 436/* Reply messages */ 437 438/* 439 * IPC4 primary header bit allocation for replies 440 * bit 0-23: status 441 * bit 24-28: type: enum sof_ipc4_global_msg if target is SOF_IPC4_FW_GEN_MSG 442 * enum sof_ipc4_module_type if target is SOF_IPC4_MODULE_MSG 443 * bit 29: response - sof_ipc4_msg_dir 444 * bit 30: target - enum sof_ipc4_msg_target 445 * bit 31: reserved, unused 446 */ 447 448#define SOF_IPC4_REPLY_STATUS GENMASK(23, 0) 449 450/* Notification messages */ 451 452/* 453 * IPC4 primary header bit allocation for notifications 454 * bit 0-15: notification type specific 455 * bit 16-23: enum sof_ipc4_notification_type 456 * bit 24-28: SOF_IPC4_GLB_NOTIFICATION 457 * bit 29: response - sof_ipc4_msg_dir 458 * bit 30: target - enum sof_ipc4_msg_target 459 * bit 31: reserved, unused 460 */ 461 462#define SOF_IPC4_MSG_IS_NOTIFICATION(x) (SOF_IPC4_MSG_TYPE_GET(x) == \ 463 SOF_IPC4_GLB_NOTIFICATION) 464 465#define SOF_IPC4_NOTIFICATION_TYPE_SHIFT 16 466#define SOF_IPC4_NOTIFICATION_TYPE_MASK GENMASK(23, 16) 467#define SOF_IPC4_NOTIFICATION_TYPE_GET(x) (((x) & SOF_IPC4_NOTIFICATION_TYPE_MASK) >> \ 468 SOF_IPC4_NOTIFICATION_TYPE_SHIFT) 469 470#define SOF_IPC4_LOG_CORE_SHIFT 12 471#define SOF_IPC4_LOG_CORE_MASK GENMASK(15, 12) 472#define SOF_IPC4_LOG_CORE_GET(x) (((x) & SOF_IPC4_LOG_CORE_MASK) >> \ 473 SOF_IPC4_LOG_CORE_SHIFT) 474 475/* Value of notification type field - must fit into 8 bits */ 476enum sof_ipc4_notification_type { 477 /* Phrase detected (notification from WoV module) */ 478 SOF_IPC4_NOTIFY_PHRASE_DETECTED = 4, 479 /* Event from a resource (pipeline or module instance) */ 480 SOF_IPC4_NOTIFY_RESOURCE_EVENT, 481 /* Debug log buffer status changed */ 482 SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS, 483 /* Timestamp captured at the link */ 484 SOF_IPC4_NOTIFY_TIMESTAMP_CAPTURED, 485 /* FW complete initialization */ 486 SOF_IPC4_NOTIFY_FW_READY, 487 /* Audio classifier result (ACA) */ 488 SOF_IPC4_NOTIFY_FW_AUD_CLASS_RESULT, 489 /* Exception caught by DSP FW */ 490 SOF_IPC4_NOTIFY_EXCEPTION_CAUGHT, 491 /* 11 is skipped by the existing cavs firmware */ 492 /* Custom module notification */ 493 SOF_IPC4_NOTIFY_MODULE_NOTIFICATION = 12, 494 /* 13 is reserved - do not use */ 495 /* Probe notify data available */ 496 SOF_IPC4_NOTIFY_PROBE_DATA_AVAILABLE = 14, 497 /* AM module notifications */ 498 SOF_IPC4_NOTIFY_ASYNC_MSG_SRVC_MESSAGE, 499 500 SOF_IPC4_NOTIFY_TYPE_LAST, 501}; 502 503struct sof_ipc4_notify_resource_data { 504 uint32_t resource_type; 505 uint32_t resource_id; 506 uint32_t event_type; 507 uint32_t reserved; 508 uint32_t data[6]; 509} __packed __aligned(4); 510 511/** @}*/ 512 513#endif 514