1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * HD-audio controller (Azalia) registers and helpers 4 * 5 * For traditional reasons, we still use azx_ prefix here 6 */ 7 8#ifndef __SOUND_HDA_REGISTER_H 9#define __SOUND_HDA_REGISTER_H 10 11#include <linux/io.h> 12#include <sound/hdaudio.h> 13 14#define AZX_REG_GCAP 0x00 15#define AZX_GCAP_64OK (1 << 0) /* 64bit address support */ 16#define AZX_GCAP_NSDO (3 << 1) /* # of serial data out signals */ 17#define AZX_GCAP_BSS (31 << 3) /* # of bidirectional streams */ 18#define AZX_GCAP_ISS (15 << 8) /* # of input streams */ 19#define AZX_GCAP_OSS (15 << 12) /* # of output streams */ 20#define AZX_REG_VMIN 0x02 21#define AZX_REG_VMAJ 0x03 22#define AZX_REG_OUTPAY 0x04 23#define AZX_REG_INPAY 0x06 24#define AZX_REG_GCTL 0x08 25#define AZX_GCTL_RESET (1 << 0) /* controller reset */ 26#define AZX_GCTL_FCNTRL (1 << 1) /* flush control */ 27#define AZX_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */ 28#define AZX_REG_WAKEEN 0x0c 29#define AZX_REG_STATESTS 0x0e 30#define AZX_REG_GSTS 0x10 31#define AZX_GSTS_FSTS (1 << 1) /* flush status */ 32#define AZX_REG_GCAP2 0x12 33#define AZX_REG_LLCH 0x14 34#define AZX_REG_OUTSTRMPAY 0x18 35#define AZX_REG_INSTRMPAY 0x1A 36#define AZX_REG_INTCTL 0x20 37#define AZX_REG_INTSTS 0x24 38#define AZX_REG_WALLCLK 0x30 /* 24Mhz source */ 39#define AZX_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */ 40#define AZX_REG_SSYNC 0x38 41#define AZX_REG_CORBLBASE 0x40 42#define AZX_REG_CORBUBASE 0x44 43#define AZX_REG_CORBWP 0x48 44#define AZX_REG_CORBRP 0x4a 45#define AZX_CORBRP_RST (1 << 15) /* read pointer reset */ 46#define AZX_REG_CORBCTL 0x4c 47#define AZX_CORBCTL_RUN (1 << 1) /* enable DMA */ 48#define AZX_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */ 49#define AZX_REG_CORBSTS 0x4d 50#define AZX_CORBSTS_CMEI (1 << 0) /* memory error indication */ 51#define AZX_REG_CORBSIZE 0x4e 52 53#define AZX_REG_RIRBLBASE 0x50 54#define AZX_REG_RIRBUBASE 0x54 55#define AZX_REG_RIRBWP 0x58 56#define AZX_RIRBWP_RST (1 << 15) /* write pointer reset */ 57#define AZX_REG_RINTCNT 0x5a 58#define AZX_REG_RIRBCTL 0x5c 59#define AZX_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */ 60#define AZX_RBCTL_DMA_EN (1 << 1) /* enable DMA */ 61#define AZX_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */ 62#define AZX_REG_RIRBSTS 0x5d 63#define AZX_RBSTS_IRQ (1 << 0) /* response irq */ 64#define AZX_RBSTS_OVERRUN (1 << 2) /* overrun irq */ 65#define AZX_REG_RIRBSIZE 0x5e 66 67#define AZX_REG_IC 0x60 68#define AZX_REG_IR 0x64 69#define AZX_REG_IRS 0x68 70#define AZX_IRS_VALID (1<<1) 71#define AZX_IRS_BUSY (1<<0) 72 73#define AZX_REG_DPLBASE 0x70 74#define AZX_REG_DPUBASE 0x74 75#define AZX_DPLBASE_ENABLE 0x1 /* Enable position buffer */ 76 77/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ 78enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; 79 80/* stream register offsets from stream base */ 81#define AZX_REG_SD_CTL 0x00 82#define AZX_REG_SD_CTL_3B 0x02 /* 3rd byte of SD_CTL register */ 83#define AZX_REG_SD_STS 0x03 84#define AZX_REG_SD_LPIB 0x04 85#define AZX_REG_SD_CBL 0x08 86#define AZX_REG_SD_LVI 0x0c 87#define AZX_REG_SD_FIFOW 0x0e 88#define AZX_REG_SD_FIFOSIZE 0x10 89#define AZX_REG_SD_FORMAT 0x12 90#define AZX_REG_SD_FIFOL 0x14 91#define AZX_REG_SD_BDLPL 0x18 92#define AZX_REG_SD_BDLPU 0x1c 93 94/* GTS registers */ 95#define AZX_REG_LLCH 0x14 96 97#define AZX_REG_GTS_BASE 0x520 98 99#define AZX_REG_GTSCC (AZX_REG_GTS_BASE + 0x00) 100#define AZX_REG_WALFCC (AZX_REG_GTS_BASE + 0x04) 101#define AZX_REG_TSCCL (AZX_REG_GTS_BASE + 0x08) 102#define AZX_REG_TSCCU (AZX_REG_GTS_BASE + 0x0C) 103#define AZX_REG_LLPFOC (AZX_REG_GTS_BASE + 0x14) 104#define AZX_REG_LLPCL (AZX_REG_GTS_BASE + 0x18) 105#define AZX_REG_LLPCU (AZX_REG_GTS_BASE + 0x1C) 106 107/* Haswell/Broadwell display HD-A controller Extended Mode registers */ 108#define AZX_REG_HSW_EM4 0x100c 109#define AZX_REG_HSW_EM5 0x1010 110 111/* Skylake/Broxton vendor-specific registers */ 112#define AZX_REG_VS_EM1 0x1000 113#define AZX_REG_VS_INRC 0x1004 114#define AZX_REG_VS_OUTRC 0x1008 115#define AZX_REG_VS_FIFOTRK 0x100C 116#define AZX_REG_VS_FIFOTRK2 0x1010 117#define AZX_REG_VS_EM2 0x1030 118#define AZX_REG_VS_EM3L 0x1038 119#define AZX_REG_VS_EM3U 0x103C 120#define AZX_REG_VS_EM4L 0x1040 121#define AZX_REG_VS_EM4U 0x1044 122#define AZX_REG_VS_LTRP 0x1048 123#define AZX_REG_VS_D0I3C 0x104A 124#define AZX_REG_VS_PCE 0x104B 125#define AZX_REG_VS_L2MAGC 0x1050 126#define AZX_REG_VS_L2LAHPT 0x1054 127#define AZX_REG_VS_SDXDPIB_XBASE 0x1084 128#define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20 129#define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094 130#define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20 131 132/* PCI space */ 133#define AZX_PCIREG_TCSEL 0x44 134 135/* 136 * other constants 137 */ 138 139/* max number of fragments - we may use more if allocating more pages for BDL */ 140#define BDL_SIZE 4096 141#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) 142#define AZX_MAX_FRAG 32 143/* 144 * max buffer size - artificial 4MB limit per stream to avoid big allocations 145 * In theory it can be really big, but as it is per stream on systems with many streams memory could 146 * be quickly saturated if userspace requests maximum buffer size for each of them. 147 */ 148#define AZX_MAX_BUF_SIZE (4*1024*1024) 149 150/* RIRB int mask: overrun[2], response[0] */ 151#define RIRB_INT_RESPONSE 0x01 152#define RIRB_INT_OVERRUN 0x04 153#define RIRB_INT_MASK 0x05 154 155/* STATESTS int mask: S3,SD2,SD1,SD0 */ 156#define STATESTS_INT_MASK ((1 << HDA_MAX_CODECS) - 1) 157 158/* SD_CTL bits */ 159#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ 160#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ 161#define SD_CTL_STRIPE (3 << 16) /* stripe control */ 162#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */ 163#define SD_CTL_DIR (1 << 19) /* bi-directional stream */ 164#define SD_CTL_STREAM_TAG_MASK (0xf << 20) 165#define SD_CTL_STREAM_TAG_SHIFT 20 166 167/* SD_CTL and SD_STS */ 168#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ 169#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ 170#define SD_INT_COMPLETE 0x04 /* completion interrupt */ 171#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ 172 SD_INT_COMPLETE) 173#define SD_CTL_STRIPE_MASK 0x3 /* stripe control mask */ 174 175/* SD_STS */ 176#define SD_STS_FIFO_READY 0x20 /* FIFO ready */ 177 178/* INTCTL and INTSTS */ 179#define AZX_INT_ALL_STREAM 0xff /* all stream interrupts */ 180#define AZX_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ 181#define AZX_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ 182 183/* below are so far hardcoded - should read registers in future */ 184#define AZX_MAX_CORB_ENTRIES 256 185#define AZX_MAX_RIRB_ENTRIES 256 186 187/* Capability header Structure */ 188#define AZX_REG_CAP_HDR 0x0 189#define AZX_CAP_HDR_VER_OFF 28 190#define AZX_CAP_HDR_VER_MASK (0xF << AZX_CAP_HDR_VER_OFF) 191#define AZX_CAP_HDR_ID_OFF 16 192#define AZX_CAP_HDR_ID_MASK (0xFFF << AZX_CAP_HDR_ID_OFF) 193#define AZX_CAP_HDR_NXT_PTR_MASK 0xFFFF 194 195/* registers of Software Position Based FIFO Capability Structure */ 196#define AZX_SPB_CAP_ID 0x4 197#define AZX_REG_SPB_BASE_ADDR 0x700 198#define AZX_REG_SPB_SPBFCH 0x00 199#define AZX_REG_SPB_SPBFCCTL 0x04 200/* Base used to calculate the iterating register offset */ 201#define AZX_SPB_BASE 0x08 202/* Interval used to calculate the iterating register offset */ 203#define AZX_SPB_INTERVAL 0x08 204/* SPIB base */ 205#define AZX_SPB_SPIB 0x00 206/* SPIB MAXFIFO base*/ 207#define AZX_SPB_MAXFIFO 0x04 208 209/* registers of Global Time Synchronization Capability Structure */ 210#define AZX_GTS_CAP_ID 0x1 211#define AZX_REG_GTS_GTSCH 0x00 212#define AZX_REG_GTS_GTSCD 0x04 213#define AZX_REG_GTS_GTSCTLAC 0x0C 214#define AZX_GTS_BASE 0x20 215#define AZX_GTS_INTERVAL 0x20 216 217/* registers for Processing Pipe Capability Structure */ 218#define AZX_PP_CAP_ID 0x3 219#define AZX_REG_PP_PPCH 0x10 220#define AZX_REG_PP_PPCTL 0x04 221#define AZX_PPCTL_PIE (1<<31) 222#define AZX_PPCTL_GPROCEN (1<<30) 223/* _X_ = dma engine # and cannot * exceed 29 (per spec max 30 dma engines) */ 224#define AZX_PPCTL_PROCEN(_X_) (1<<(_X_)) 225 226#define AZX_REG_PP_PPSTS 0x08 227 228#define AZX_PPHC_BASE 0x10 229#define AZX_PPHC_INTERVAL 0x10 230 231#define AZX_REG_PPHCLLPL 0x0 232#define AZX_REG_PPHCLLPU 0x4 233#define AZX_REG_PPHCLDPL 0x8 234#define AZX_REG_PPHCLDPU 0xC 235 236#define AZX_PPLC_BASE 0x10 237#define AZX_PPLC_MULTI 0x10 238#define AZX_PPLC_INTERVAL 0x10 239 240#define AZX_REG_PPLCCTL 0x0 241#define AZX_PPLCCTL_STRM_BITS 4 242#define AZX_PPLCCTL_STRM_SHIFT 20 243#define AZX_REG_MASK(bit_num, offset) \ 244 (((1 << (bit_num)) - 1) << (offset)) 245#define AZX_PPLCCTL_STRM_MASK \ 246 AZX_REG_MASK(AZX_PPLCCTL_STRM_BITS, AZX_PPLCCTL_STRM_SHIFT) 247#define AZX_PPLCCTL_RUN (1<<1) 248#define AZX_PPLCCTL_STRST (1<<0) 249 250#define AZX_REG_PPLCFMT 0x4 251#define AZX_REG_PPLCLLPL 0x8 252#define AZX_REG_PPLCLLPU 0xC 253 254/* registers for Multiple Links Capability Structure */ 255#define AZX_ML_CAP_ID 0x2 256#define AZX_REG_ML_MLCH 0x00 257#define AZX_REG_ML_MLCD 0x04 258#define AZX_ML_BASE 0x40 259#define AZX_ML_INTERVAL 0x40 260 261/* HDaudio registers valid for HDaudio and HDaudio extended links */ 262#define AZX_REG_ML_LCAP 0x00 263 264#define AZX_ML_HDA_LCAP_ALT BIT(28) 265#define AZX_ML_HDA_LCAP_ALT_HDA 0x0 266#define AZX_ML_HDA_LCAP_ALT_HDA_EXT 0x1 267 268#define AZX_ML_HDA_LCAP_INTC BIT(27) /* only used if ALT == 1 */ 269#define AZX_ML_HDA_LCAP_OFLS BIT(26) /* only used if ALT == 1 */ 270#define AZX_ML_HDA_LCAP_LSS BIT(23) /* only used if ALT == 1 */ 271#define AZX_ML_HDA_LCAP_SLCOUNT GENMASK(22, 20) /* only used if ALT == 1 */ 272 273#define AZX_REG_ML_LCTL 0x04 274#define AZX_ML_LCTL_INTSTS BIT(31) /* only used if ALT == 1 */ 275#define AZX_ML_LCTL_CPA BIT(23) 276#define AZX_ML_LCTL_CPA_SHIFT 23 277#define AZX_ML_LCTL_SPA BIT(16) 278#define AZX_ML_LCTL_SPA_SHIFT 16 279#define AZX_ML_LCTL_INTEN BIT(5) /* only used if ALT == 1 */ 280#define AZX_ML_LCTL_OFLEN BIT(4) /* only used if ALT == 1 */ 281#define AZX_ML_LCTL_SCF GENMASK(3, 0) /* only used if ALT == 0 */ 282 283#define AZX_REG_ML_LOSIDV 0x08 284 285/* bit0 is reserved, with BIT(1) mapping to stream1 */ 286#define AZX_ML_LOSIDV_STREAM_MASK 0xFFFE 287 288#define AZX_REG_ML_LSDIID 0x0C 289#define AZX_REG_ML_LSDIID_OFFSET(x) (0x0C + (x) * 0x02) /* only used if ALT == 1 */ 290 291/* HDaudio registers only valid if LCAP.ALT == 0 */ 292#define AZX_REG_ML_LPSOO 0x10 293#define AZX_REG_ML_LPSIO 0x12 294#define AZX_REG_ML_LWALFC 0x18 295#define AZX_REG_ML_LOUTPAY 0x20 296#define AZX_REG_ML_LINPAY 0x30 297 298/* HDaudio Extended link registers only valid if LCAP.ALT == 1 */ 299#define AZX_REG_ML_LSYNC 0x1C 300 301#define AZX_REG_ML_LSYNC_CMDSYNC BIT(24) 302#define AZX_REG_ML_LSYNC_CMDSYNC_SHIFT 24 303#define AZX_REG_ML_LSYNC_SYNCGO BIT(23) 304#define AZX_REG_ML_LSYNC_SYNCPU BIT(20) 305#define AZX_REG_ML_LSYNC_SYNCPRD GENMASK(19, 0) 306 307#define AZX_REG_ML_LEPTR 0x20 308 309#define AZX_REG_ML_LEPTR_ID GENMASK(31, 24) 310#define AZX_REG_ML_LEPTR_ID_SHIFT 24 311#define AZX_REG_ML_LEPTR_ID_SDW 0x00 312#define AZX_REG_ML_LEPTR_ID_INTEL_SSP 0xC0 313#define AZX_REG_ML_LEPTR_ID_INTEL_DMIC 0xC1 314#define AZX_REG_ML_LEPTR_ID_INTEL_UAOL 0xC2 315#define AZX_REG_ML_LEPTR_VER GENMASK(23, 20) 316#define AZX_REG_ML_LEPTR_PTR GENMASK(19, 0) 317 318/* registers for DMA Resume Capability Structure */ 319#define AZX_DRSM_CAP_ID 0x5 320#define AZX_REG_DRSM_CTL 0x4 321/* Base used to calculate the iterating register offset */ 322#define AZX_DRSM_BASE 0x08 323/* Interval used to calculate the iterating register offset */ 324#define AZX_DRSM_INTERVAL 0x08 325 326/* Global time synchronization registers */ 327#define GTSCC_TSCCD_MASK 0x80000000 328#define GTSCC_TSCCD_SHIFT BIT(31) 329#define GTSCC_TSCCI_MASK 0x20 330#define GTSCC_CDMAS_DMA_DIR_SHIFT 4 331 332#define WALFCC_CIF_MASK 0x1FF 333#define WALFCC_FN_SHIFT 9 334#define HDA_CLK_CYCLES_PER_FRAME 512 335 336/* 337 * An error occurs near frame "rollover". The clocks in frame value indicates 338 * whether this error may have occurred. Here we use the value of 10. Please 339 * see the errata for the right number [<10] 340 */ 341#define HDA_MAX_CYCLE_VALUE 499 342#define HDA_MAX_CYCLE_OFFSET 10 343#define HDA_MAX_CYCLE_READ_RETRY 10 344 345#define TSCCU_CCU_SHIFT 32 346#define LLPC_CCU_SHIFT 32 347 348 349/* 350 * helpers to read the stream position 351 */ 352static inline unsigned int 353snd_hdac_stream_get_pos_lpib(struct hdac_stream *stream) 354{ 355 return snd_hdac_stream_readl(stream, SD_LPIB); 356} 357 358static inline unsigned int 359snd_hdac_stream_get_pos_posbuf(struct hdac_stream *stream) 360{ 361 return le32_to_cpu(*stream->posbuf); 362} 363 364#endif /* __SOUND_HDA_REGISTER_H */ 365