162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-or-later */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Definitions for CS4271 ASoC codec driver 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru> 662306a36Sopenharmony_ci */ 762306a36Sopenharmony_ci 862306a36Sopenharmony_ci#ifndef __CS4271_H 962306a36Sopenharmony_ci#define __CS4271_H 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_cistruct cs4271_platform_data { 1262306a36Sopenharmony_ci int gpio_nreset; /* GPIO driving Reset pin, if any */ 1362306a36Sopenharmony_ci bool amutec_eq_bmutec; /* flag to enable AMUTEC=BMUTEC */ 1462306a36Sopenharmony_ci 1562306a36Sopenharmony_ci /* 1662306a36Sopenharmony_ci * The CS4271 requires its LRCLK and MCLK to be stable before its RESET 1762306a36Sopenharmony_ci * line is de-asserted. That also means that clocks cannot be changed 1862306a36Sopenharmony_ci * without putting the chip back into hardware reset, which also requires 1962306a36Sopenharmony_ci * a complete re-initialization of all registers. 2062306a36Sopenharmony_ci * 2162306a36Sopenharmony_ci * One (undocumented) workaround is to assert and de-assert the PDN bit 2262306a36Sopenharmony_ci * in the MODE2 register. This workaround can be enabled with the 2362306a36Sopenharmony_ci * following flag. 2462306a36Sopenharmony_ci * 2562306a36Sopenharmony_ci * Note that this is not needed in case the clocks are stable 2662306a36Sopenharmony_ci * throughout the entire runtime of the codec. 2762306a36Sopenharmony_ci */ 2862306a36Sopenharmony_ci bool enable_soft_reset; 2962306a36Sopenharmony_ci}; 3062306a36Sopenharmony_ci 3162306a36Sopenharmony_ci#endif /* __CS4271_H */ 32