162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Functions and macros to control the flowcontroller
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
662306a36Sopenharmony_ci */
762306a36Sopenharmony_ci
862306a36Sopenharmony_ci#ifndef __SOC_TEGRA_FLOWCTRL_H__
962306a36Sopenharmony_ci#define __SOC_TEGRA_FLOWCTRL_H__
1062306a36Sopenharmony_ci
1162306a36Sopenharmony_ci#define FLOW_CTRL_HALT_CPU0_EVENTS	0x0
1262306a36Sopenharmony_ci#define FLOW_CTRL_WAITEVENT		(2 << 29)
1362306a36Sopenharmony_ci#define FLOW_CTRL_WAIT_FOR_INTERRUPT	(4 << 29)
1462306a36Sopenharmony_ci#define FLOW_CTRL_JTAG_RESUME		(1 << 28)
1562306a36Sopenharmony_ci#define FLOW_CTRL_SCLK_RESUME		(1 << 27)
1662306a36Sopenharmony_ci#define FLOW_CTRL_HALT_CPU_IRQ		(1 << 10)
1762306a36Sopenharmony_ci#define	FLOW_CTRL_HALT_CPU_FIQ		(1 << 8)
1862306a36Sopenharmony_ci#define FLOW_CTRL_HALT_LIC_IRQ		(1 << 11)
1962306a36Sopenharmony_ci#define FLOW_CTRL_HALT_LIC_FIQ		(1 << 10)
2062306a36Sopenharmony_ci#define FLOW_CTRL_HALT_GIC_IRQ		(1 << 9)
2162306a36Sopenharmony_ci#define FLOW_CTRL_HALT_GIC_FIQ		(1 << 8)
2262306a36Sopenharmony_ci#define FLOW_CTRL_CPU0_CSR		0x8
2362306a36Sopenharmony_ci#define	FLOW_CTRL_CSR_INTR_FLAG		(1 << 15)
2462306a36Sopenharmony_ci#define FLOW_CTRL_CSR_EVENT_FLAG	(1 << 14)
2562306a36Sopenharmony_ci#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL	(1 << 13)
2662306a36Sopenharmony_ci#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU	(1 << 12)
2762306a36Sopenharmony_ci#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \
2862306a36Sopenharmony_ci		FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
2962306a36Sopenharmony_ci		FLOW_CTRL_CSR_ENABLE_EXT_CRAIL)
3062306a36Sopenharmony_ci#define FLOW_CTRL_CSR_ENABLE		(1 << 0)
3162306a36Sopenharmony_ci#define FLOW_CTRL_HALT_CPU1_EVENTS	0x14
3262306a36Sopenharmony_ci#define FLOW_CTRL_CPU1_CSR		0x18
3362306a36Sopenharmony_ci
3462306a36Sopenharmony_ci#define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0		(1 << 4)
3562306a36Sopenharmony_ci#define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP	(3 << 4)
3662306a36Sopenharmony_ci#define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP	0
3762306a36Sopenharmony_ci
3862306a36Sopenharmony_ci#define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0		(1 << 8)
3962306a36Sopenharmony_ci#define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP	(0xF << 4)
4062306a36Sopenharmony_ci#define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP	(0xF << 8)
4162306a36Sopenharmony_ci
4262306a36Sopenharmony_ci#ifndef __ASSEMBLY__
4362306a36Sopenharmony_ci#ifdef CONFIG_SOC_TEGRA_FLOWCTRL
4462306a36Sopenharmony_ciu32 flowctrl_read_cpu_csr(unsigned int cpuid);
4562306a36Sopenharmony_civoid flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
4662306a36Sopenharmony_civoid flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
4762306a36Sopenharmony_ci
4862306a36Sopenharmony_civoid flowctrl_cpu_suspend_enter(unsigned int cpuid);
4962306a36Sopenharmony_civoid flowctrl_cpu_suspend_exit(unsigned int cpuid);
5062306a36Sopenharmony_ci#else
5162306a36Sopenharmony_cistatic inline u32 flowctrl_read_cpu_csr(unsigned int cpuid)
5262306a36Sopenharmony_ci{
5362306a36Sopenharmony_ci	return 0;
5462306a36Sopenharmony_ci}
5562306a36Sopenharmony_ci
5662306a36Sopenharmony_cistatic inline void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
5762306a36Sopenharmony_ci{
5862306a36Sopenharmony_ci}
5962306a36Sopenharmony_ci
6062306a36Sopenharmony_cistatic inline void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) {}
6162306a36Sopenharmony_ci
6262306a36Sopenharmony_cistatic inline void flowctrl_cpu_suspend_enter(unsigned int cpuid)
6362306a36Sopenharmony_ci{
6462306a36Sopenharmony_ci}
6562306a36Sopenharmony_ci
6662306a36Sopenharmony_cistatic inline void flowctrl_cpu_suspend_exit(unsigned int cpuid)
6762306a36Sopenharmony_ci{
6862306a36Sopenharmony_ci}
6962306a36Sopenharmony_ci#endif /* CONFIG_SOC_TEGRA_FLOWCTRL */
7062306a36Sopenharmony_ci#endif /* __ASSEMBLY */
7162306a36Sopenharmony_ci#endif /* __SOC_TEGRA_FLOWCTRL_H__ */
72