1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7
8#ifndef _MSCC_OCELOT_DEV_H_
9#define _MSCC_OCELOT_DEV_H_
10
11#define DEV_CLOCK_CFG_MAC_TX_RST                          BIT(7)
12#define DEV_CLOCK_CFG_MAC_RX_RST                          BIT(6)
13#define DEV_CLOCK_CFG_PCS_TX_RST                          BIT(5)
14#define DEV_CLOCK_CFG_PCS_RX_RST                          BIT(4)
15#define DEV_CLOCK_CFG_PORT_RST                            BIT(3)
16#define DEV_CLOCK_CFG_PHY_RST                             BIT(2)
17#define DEV_CLOCK_CFG_LINK_SPEED(x)                       ((x) & GENMASK(1, 0))
18#define DEV_CLOCK_CFG_LINK_SPEED_M                        GENMASK(1, 0)
19
20#define DEV_PORT_MISC_FWD_ERROR_ENA                       BIT(4)
21#define DEV_PORT_MISC_FWD_PAUSE_ENA                       BIT(3)
22#define DEV_PORT_MISC_FWD_CTRL_ENA                        BIT(2)
23#define DEV_PORT_MISC_DEV_LOOP_ENA                        BIT(1)
24#define DEV_PORT_MISC_HDX_FAST_DIS                        BIT(0)
25
26#define DEV_EEE_CFG_EEE_ENA                               BIT(22)
27#define DEV_EEE_CFG_EEE_TIMER_AGE(x)                      (((x) << 15) & GENMASK(21, 15))
28#define DEV_EEE_CFG_EEE_TIMER_AGE_M                       GENMASK(21, 15)
29#define DEV_EEE_CFG_EEE_TIMER_AGE_X(x)                    (((x) & GENMASK(21, 15)) >> 15)
30#define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x)                   (((x) << 8) & GENMASK(14, 8))
31#define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M                    GENMASK(14, 8)
32#define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x)                 (((x) & GENMASK(14, 8)) >> 8)
33#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x)                  (((x) << 1) & GENMASK(7, 1))
34#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M                   GENMASK(7, 1)
35#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_X(x)                (((x) & GENMASK(7, 1)) >> 1)
36#define DEV_EEE_CFG_PORT_LPI                              BIT(0)
37
38#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x)        (((x) << 4) & GENMASK(11, 4))
39#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M         GENMASK(11, 4)
40#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_X(x)      (((x) & GENMASK(11, 4)) >> 4)
41#define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG(x)      ((x) & GENMASK(3, 0))
42#define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG_M       GENMASK(3, 0)
43
44#define DEV_MAC_ENA_CFG_RX_ENA                            BIT(4)
45#define DEV_MAC_ENA_CFG_TX_ENA                            BIT(0)
46
47#define DEV_MAC_MODE_CFG_FC_WORD_SYNC_ENA                 BIT(8)
48#define DEV_MAC_MODE_CFG_GIGA_MODE_ENA                    BIT(4)
49#define DEV_MAC_MODE_CFG_FDX_ENA                          BIT(0)
50
51#define DEV_MAC_TAGS_CFG_TAG_ID(x)                        (((x) << 16) & GENMASK(31, 16))
52#define DEV_MAC_TAGS_CFG_TAG_ID_M                         GENMASK(31, 16)
53#define DEV_MAC_TAGS_CFG_TAG_ID_X(x)                      (((x) & GENMASK(31, 16)) >> 16)
54#define DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA                 BIT(2)
55#define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA                 BIT(1)
56#define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA                     BIT(0)
57
58#define DEV_MAC_ADV_CHK_CFG_LEN_DROP_ENA                  BIT(0)
59
60#define DEV_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK             BIT(17)
61#define DEV_MAC_IFG_CFG_REDUCED_TX_IFG                    BIT(16)
62#define DEV_MAC_IFG_CFG_TX_IFG(x)                         (((x) << 8) & GENMASK(12, 8))
63#define DEV_MAC_IFG_CFG_TX_IFG_M                          GENMASK(12, 8)
64#define DEV_MAC_IFG_CFG_TX_IFG_X(x)                       (((x) & GENMASK(12, 8)) >> 8)
65#define DEV_MAC_IFG_CFG_RX_IFG2(x)                        (((x) << 4) & GENMASK(7, 4))
66#define DEV_MAC_IFG_CFG_RX_IFG2_M                         GENMASK(7, 4)
67#define DEV_MAC_IFG_CFG_RX_IFG2_X(x)                      (((x) & GENMASK(7, 4)) >> 4)
68#define DEV_MAC_IFG_CFG_RX_IFG1(x)                        ((x) & GENMASK(3, 0))
69#define DEV_MAC_IFG_CFG_RX_IFG1_M                         GENMASK(3, 0)
70
71#define DEV_MAC_HDX_CFG_BYPASS_COL_SYNC                   BIT(26)
72#define DEV_MAC_HDX_CFG_OB_ENA                            BIT(25)
73#define DEV_MAC_HDX_CFG_WEXC_DIS                          BIT(24)
74#define DEV_MAC_HDX_CFG_SEED(x)                           (((x) << 16) & GENMASK(23, 16))
75#define DEV_MAC_HDX_CFG_SEED_M                            GENMASK(23, 16)
76#define DEV_MAC_HDX_CFG_SEED_X(x)                         (((x) & GENMASK(23, 16)) >> 16)
77#define DEV_MAC_HDX_CFG_SEED_LOAD                         BIT(12)
78#define DEV_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA           BIT(8)
79#define DEV_MAC_HDX_CFG_LATE_COL_POS(x)                   ((x) & GENMASK(6, 0))
80#define DEV_MAC_HDX_CFG_LATE_COL_POS_M                    GENMASK(6, 0)
81
82#define DEV_MAC_DBG_CFG_TBI_MODE                          BIT(4)
83#define DEV_MAC_DBG_CFG_IFG_CRS_EXT_CHK_ENA               BIT(0)
84
85#define DEV_MAC_STICKY_RX_IPG_SHRINK_STICKY               BIT(9)
86#define DEV_MAC_STICKY_RX_PREAM_SHRINK_STICKY             BIT(8)
87#define DEV_MAC_STICKY_RX_CARRIER_EXT_STICKY              BIT(7)
88#define DEV_MAC_STICKY_RX_CARRIER_EXT_ERR_STICKY          BIT(6)
89#define DEV_MAC_STICKY_RX_JUNK_STICKY                     BIT(5)
90#define DEV_MAC_STICKY_TX_RETRANSMIT_STICKY               BIT(4)
91#define DEV_MAC_STICKY_TX_JAM_STICKY                      BIT(3)
92#define DEV_MAC_STICKY_TX_FIFO_OFLW_STICKY                BIT(2)
93#define DEV_MAC_STICKY_TX_FRM_LEN_OVR_STICKY              BIT(1)
94#define DEV_MAC_STICKY_TX_ABORT_STICKY                    BIT(0)
95
96#define DEV_MM_CONFIG_ENABLE_CONFIG_MM_RX_ENA             BIT(0)
97#define DEV_MM_CONFIG_ENABLE_CONFIG_MM_TX_ENA             BIT(4)
98#define DEV_MM_CONFIG_ENABLE_CONFIG_KEEP_S_AFTER_D        BIT(8)
99
100#define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_DIS         BIT(0)
101#define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME(x)     (((x) << 4) & GENMASK(11, 4))
102#define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME_M      GENMASK(11, 4)
103#define DEV_MM_CONFIG_VERIF_CONFIG_PRM_VERIFY_TIME_X(x)   (((x) & GENMASK(11, 4)) >> 4)
104#define DEV_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS(x)   (((x) << 12) & GENMASK(13, 12))
105#define DEV_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS_M    GENMASK(13, 12)
106#define DEV_MM_CONFIG_VERIF_CONFIG_VERIF_TIMER_UNITS_X(x) (((x) & GENMASK(13, 12)) >> 12)
107
108#define DEV_MM_STAT_MM_STATUS_PRMPT_ACTIVE_STATUS         BIT(0)
109#define DEV_MM_STAT_MM_STATUS_PRMPT_ACTIVE_STICKY         BIT(4)
110#define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE(x)       (((x) << 8) & GENMASK(10, 8))
111#define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE_M        GENMASK(10, 8)
112#define DEV_MM_STAT_MM_STATUS_PRMPT_VERIFY_STATE_X(x)     (((x) & GENMASK(10, 8)) >> 8)
113#define DEV_MM_STAT_MM_STATUS_UNEXP_RX_PFRM_STICKY        BIT(12)
114#define DEV_MM_STAT_MM_STATUS_UNEXP_TX_PFRM_STICKY        BIT(16)
115#define DEV_MM_STAT_MM_STATUS_MM_RX_FRAME_STATUS          BIT(20)
116#define DEV_MM_STAT_MM_STATUS_MM_TX_FRAME_STATUS          BIT(24)
117#define DEV_MM_STAT_MM_STATUS_MM_TX_PRMPT_STATUS          BIT(28)
118
119#define PCS1G_CFG_LINK_STATUS_TYPE                        BIT(4)
120#define PCS1G_CFG_AN_LINK_CTRL_ENA                        BIT(1)
121#define PCS1G_CFG_PCS_ENA                                 BIT(0)
122
123#define PCS1G_MODE_CFG_UNIDIR_MODE_ENA                    BIT(4)
124#define PCS1G_MODE_CFG_SGMII_MODE_ENA                     BIT(0)
125
126#define PCS1G_SD_CFG_SD_SEL                               BIT(8)
127#define PCS1G_SD_CFG_SD_POL                               BIT(4)
128#define PCS1G_SD_CFG_SD_ENA                               BIT(0)
129
130#define PCS1G_ANEG_CFG_ADV_ABILITY(x)                     (((x) << 16) & GENMASK(31, 16))
131#define PCS1G_ANEG_CFG_ADV_ABILITY_M                      GENMASK(31, 16)
132#define PCS1G_ANEG_CFG_ADV_ABILITY_X(x)                   (((x) & GENMASK(31, 16)) >> 16)
133#define PCS1G_ANEG_CFG_SW_RESOLVE_ENA                     BIT(8)
134#define PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT              BIT(1)
135#define PCS1G_ANEG_CFG_ANEG_ENA                           BIT(0)
136
137#define PCS1G_ANEG_NP_CFG_NP_TX(x)                        (((x) << 16) & GENMASK(31, 16))
138#define PCS1G_ANEG_NP_CFG_NP_TX_M                         GENMASK(31, 16)
139#define PCS1G_ANEG_NP_CFG_NP_TX_X(x)                      (((x) & GENMASK(31, 16)) >> 16)
140#define PCS1G_ANEG_NP_CFG_NP_LOADED_ONE_SHOT              BIT(0)
141
142#define PCS1G_LB_CFG_RA_ENA                               BIT(4)
143#define PCS1G_LB_CFG_GMII_PHY_LB_ENA                      BIT(1)
144#define PCS1G_LB_CFG_TBI_HOST_LB_ENA                      BIT(0)
145
146#define PCS1G_DBG_CFG_UDLT                                BIT(0)
147
148#define PCS1G_CDET_CFG_CDET_ENA                           BIT(0)
149
150#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY(x)               (((x) << 16) & GENMASK(31, 16))
151#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_M                GENMASK(31, 16)
152#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_X(x)             (((x) & GENMASK(31, 16)) >> 16)
153#define PCS1G_ANEG_STATUS_PR                              BIT(4)
154#define PCS1G_ANEG_STATUS_PAGE_RX_STICKY                  BIT(3)
155#define PCS1G_ANEG_STATUS_ANEG_COMPLETE                   BIT(0)
156
157#define PCS1G_LINK_STATUS_DELAY_VAR(x)                    (((x) << 12) & GENMASK(15, 12))
158#define PCS1G_LINK_STATUS_DELAY_VAR_M                     GENMASK(15, 12)
159#define PCS1G_LINK_STATUS_DELAY_VAR_X(x)                  (((x) & GENMASK(15, 12)) >> 12)
160#define PCS1G_LINK_STATUS_SIGNAL_DETECT                   BIT(8)
161#define PCS1G_LINK_STATUS_LINK_STATUS                     BIT(4)
162#define PCS1G_LINK_STATUS_SYNC_STATUS                     BIT(0)
163
164#define PCS1G_STICKY_LINK_DOWN_STICKY                     BIT(4)
165#define PCS1G_STICKY_OUT_OF_SYNC_STICKY                   BIT(0)
166
167#define PCS1G_LPI_CFG_QSGMII_MS_SEL                       BIT(20)
168#define PCS1G_LPI_CFG_RX_LPI_OUT_DIS                      BIT(17)
169#define PCS1G_LPI_CFG_LPI_TESTMODE                        BIT(16)
170#define PCS1G_LPI_CFG_LPI_RX_WTIM(x)                      (((x) << 4) & GENMASK(5, 4))
171#define PCS1G_LPI_CFG_LPI_RX_WTIM_M                       GENMASK(5, 4)
172#define PCS1G_LPI_CFG_LPI_RX_WTIM_X(x)                    (((x) & GENMASK(5, 4)) >> 4)
173#define PCS1G_LPI_CFG_TX_ASSERT_LPIDLE                    BIT(0)
174
175#define PCS1G_LPI_STATUS_RX_LPI_FAIL                      BIT(16)
176#define PCS1G_LPI_STATUS_RX_LPI_EVENT_STICKY              BIT(12)
177#define PCS1G_LPI_STATUS_RX_QUIET                         BIT(9)
178#define PCS1G_LPI_STATUS_RX_LPI_MODE                      BIT(8)
179#define PCS1G_LPI_STATUS_TX_LPI_EVENT_STICKY              BIT(4)
180#define PCS1G_LPI_STATUS_TX_QUIET                         BIT(1)
181#define PCS1G_LPI_STATUS_TX_LPI_MODE                      BIT(0)
182
183#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT(x)                (((x) << 8) & GENMASK(15, 8))
184#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_M                 GENMASK(15, 8)
185#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_X(x)              (((x) & GENMASK(15, 8)) >> 8)
186#define PCS1G_TSTPAT_STATUS_JTP_ERR                       BIT(4)
187#define PCS1G_TSTPAT_STATUS_JTP_LOCK                      BIT(0)
188
189#define DEV_PCS_FX100_CFG_SD_SEL                          BIT(26)
190#define DEV_PCS_FX100_CFG_SD_POL                          BIT(25)
191#define DEV_PCS_FX100_CFG_SD_ENA                          BIT(24)
192#define DEV_PCS_FX100_CFG_LOOPBACK_ENA                    BIT(20)
193#define DEV_PCS_FX100_CFG_SWAP_MII_ENA                    BIT(16)
194#define DEV_PCS_FX100_CFG_RXBITSEL(x)                     (((x) << 12) & GENMASK(15, 12))
195#define DEV_PCS_FX100_CFG_RXBITSEL_M                      GENMASK(15, 12)
196#define DEV_PCS_FX100_CFG_RXBITSEL_X(x)                   (((x) & GENMASK(15, 12)) >> 12)
197#define DEV_PCS_FX100_CFG_SIGDET_CFG(x)                   (((x) << 9) & GENMASK(10, 9))
198#define DEV_PCS_FX100_CFG_SIGDET_CFG_M                    GENMASK(10, 9)
199#define DEV_PCS_FX100_CFG_SIGDET_CFG_X(x)                 (((x) & GENMASK(10, 9)) >> 9)
200#define DEV_PCS_FX100_CFG_LINKHYST_TM_ENA                 BIT(8)
201#define DEV_PCS_FX100_CFG_LINKHYSTTIMER(x)                (((x) << 4) & GENMASK(7, 4))
202#define DEV_PCS_FX100_CFG_LINKHYSTTIMER_M                 GENMASK(7, 4)
203#define DEV_PCS_FX100_CFG_LINKHYSTTIMER_X(x)              (((x) & GENMASK(7, 4)) >> 4)
204#define DEV_PCS_FX100_CFG_UNIDIR_MODE_ENA                 BIT(3)
205#define DEV_PCS_FX100_CFG_FEFCHK_ENA                      BIT(2)
206#define DEV_PCS_FX100_CFG_FEFGEN_ENA                      BIT(1)
207#define DEV_PCS_FX100_CFG_PCS_ENA                         BIT(0)
208
209#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP(x)              (((x) << 8) & GENMASK(11, 8))
210#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_M               GENMASK(11, 8)
211#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_X(x)            (((x) & GENMASK(11, 8)) >> 8)
212#define DEV_PCS_FX100_STATUS_PCS_ERROR_STICKY             BIT(7)
213#define DEV_PCS_FX100_STATUS_FEF_FOUND_STICKY             BIT(6)
214#define DEV_PCS_FX100_STATUS_SSD_ERROR_STICKY             BIT(5)
215#define DEV_PCS_FX100_STATUS_SYNC_LOST_STICKY             BIT(4)
216#define DEV_PCS_FX100_STATUS_FEF_STATUS                   BIT(2)
217#define DEV_PCS_FX100_STATUS_SIGNAL_DETECT                BIT(1)
218#define DEV_PCS_FX100_STATUS_SYNC_STATUS                  BIT(0)
219
220#endif
221