162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Microchip SAMA7 SFRBU registers offsets and bit definitions. 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries 662306a36Sopenharmony_ci * 762306a36Sopenharmony_ci * Author: Claudu Beznea <claudiu.beznea@microchip.com> 862306a36Sopenharmony_ci */ 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci#ifndef __SAMA7_SFRBU_H__ 1162306a36Sopenharmony_ci#define __SAMA7_SFRBU_H__ 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ci#ifdef CONFIG_SOC_SAMA7 1462306a36Sopenharmony_ci 1562306a36Sopenharmony_ci#define AT91_SFRBU_PSWBU (0x00) /* SFRBU Power Switch BU Control Register */ 1662306a36Sopenharmony_ci#define AT91_SFRBU_PSWBU_PSWKEY (0x4BD20C << 8) /* Specific value mandatory to allow writing of other register bits */ 1762306a36Sopenharmony_ci#define AT91_SFRBU_PSWBU_STATE (1 << 2) /* Power switch BU state */ 1862306a36Sopenharmony_ci#define AT91_SFRBU_PSWBU_SOFTSWITCH (1 << 1) /* Power switch BU source selection */ 1962306a36Sopenharmony_ci#define AT91_SFRBU_PSWBU_CTRL (1 << 0) /* Power switch BU control */ 2062306a36Sopenharmony_ci 2162306a36Sopenharmony_ci#define AT91_SFRBU_25LDOCR (0x0C) /* SFRBU 2.5V LDO Control Register */ 2262306a36Sopenharmony_ci#define AT91_SFRBU_25LDOCR_LDOANAKEY (0x3B6E18 << 8) /* Specific value mandatory to allow writing of other register bits. */ 2362306a36Sopenharmony_ci#define AT91_SFRBU_25LDOCR_STATE (1 << 3) /* LDOANA Switch On/Off Control */ 2462306a36Sopenharmony_ci#define AT91_SFRBU_25LDOCR_LP (1 << 2) /* LDOANA Low-Power Mode Control */ 2562306a36Sopenharmony_ci#define AT91_SFRBU_PD_VALUE_MSK (0x3) 2662306a36Sopenharmony_ci#define AT91_SFRBU_25LDOCR_PD_VALUE(v) ((v) & AT91_SFRBU_PD_VALUE_MSK) /* LDOANA Pull-down value */ 2762306a36Sopenharmony_ci 2862306a36Sopenharmony_ci#define AT91_FRBU_DDRPWR (0x10) /* SFRBU DDR Power Control Register */ 2962306a36Sopenharmony_ci#define AT91_FRBU_DDRPWR_STATE (1 << 0) /* DDR Power Mode State */ 3062306a36Sopenharmony_ci 3162306a36Sopenharmony_ci#endif /* CONFIG_SOC_SAMA7 */ 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_ci#endif /* __SAMA7_SFRBU_H__ */ 3462306a36Sopenharmony_ci 35