162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com) 462306a36Sopenharmony_ci */ 562306a36Sopenharmony_ci 662306a36Sopenharmony_ci#ifndef __SOC_ARC_TIMERS_H 762306a36Sopenharmony_ci#define __SOC_ARC_TIMERS_H 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci#include <soc/arc/aux.h> 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci/* Timer related Aux registers */ 1262306a36Sopenharmony_ci#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */ 1362306a36Sopenharmony_ci#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */ 1462306a36Sopenharmony_ci#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */ 1562306a36Sopenharmony_ci#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */ 1662306a36Sopenharmony_ci#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */ 1762306a36Sopenharmony_ci#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */ 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ci/* CTRL reg bits */ 2062306a36Sopenharmony_ci#define ARC_TIMER_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */ 2162306a36Sopenharmony_ci#define ARC_TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ 2262306a36Sopenharmony_ci 2362306a36Sopenharmony_ci#define ARC_TIMERN_MAX 0xFFFFFFFF 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ci#define ARC_REG_TIMERS_BCR 0x75 2662306a36Sopenharmony_ci 2762306a36Sopenharmony_cistruct bcr_timer { 2862306a36Sopenharmony_ci#ifdef CONFIG_CPU_BIG_ENDIAN 2962306a36Sopenharmony_ci unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8; 3062306a36Sopenharmony_ci#else 3162306a36Sopenharmony_ci unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15; 3262306a36Sopenharmony_ci#endif 3362306a36Sopenharmony_ci}; 3462306a36Sopenharmony_ci 3562306a36Sopenharmony_ci#endif 36