162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Information for the Marvell Armada MMP camera 462306a36Sopenharmony_ci */ 562306a36Sopenharmony_ci 662306a36Sopenharmony_ci#include <media/v4l2-mediabus.h> 762306a36Sopenharmony_ci 862306a36Sopenharmony_cienum dphy3_algo { 962306a36Sopenharmony_ci DPHY3_ALGO_DEFAULT = 0, 1062306a36Sopenharmony_ci DPHY3_ALGO_PXA910, 1162306a36Sopenharmony_ci DPHY3_ALGO_PXA2128 1262306a36Sopenharmony_ci}; 1362306a36Sopenharmony_ci 1462306a36Sopenharmony_cistruct mmp_camera_platform_data { 1562306a36Sopenharmony_ci enum v4l2_mbus_type bus_type; 1662306a36Sopenharmony_ci int mclk_src; /* which clock source the MCLK derives from */ 1762306a36Sopenharmony_ci int mclk_div; /* Clock Divider Value for MCLK */ 1862306a36Sopenharmony_ci /* 1962306a36Sopenharmony_ci * MIPI support 2062306a36Sopenharmony_ci */ 2162306a36Sopenharmony_ci int dphy[3]; /* DPHY: CSI2_DPHY3, CSI2_DPHY5, CSI2_DPHY6 */ 2262306a36Sopenharmony_ci enum dphy3_algo dphy3_algo; /* algos for calculate CSI2_DPHY3 */ 2362306a36Sopenharmony_ci int lane; /* ccic used lane number; 0 means DVP mode */ 2462306a36Sopenharmony_ci int lane_clk; 2562306a36Sopenharmony_ci}; 26