162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Copyright 2020,2022 NXP
462306a36Sopenharmony_ci */
562306a36Sopenharmony_ci
662306a36Sopenharmony_ci#ifndef __PHY_LVDS_H_
762306a36Sopenharmony_ci#define __PHY_LVDS_H_
862306a36Sopenharmony_ci
962306a36Sopenharmony_ci/**
1062306a36Sopenharmony_ci * struct phy_configure_opts_lvds - LVDS configuration set
1162306a36Sopenharmony_ci * @bits_per_lane_and_dclk_cycle:	Number of bits per lane per differential
1262306a36Sopenharmony_ci *					clock cycle.
1362306a36Sopenharmony_ci * @differential_clk_rate:		Clock rate, in Hertz, of the LVDS
1462306a36Sopenharmony_ci *					differential clock.
1562306a36Sopenharmony_ci * @lanes:				Number of active, consecutive,
1662306a36Sopenharmony_ci *					data lanes, starting from lane 0,
1762306a36Sopenharmony_ci *					used for the transmissions.
1862306a36Sopenharmony_ci * @is_slave:				Boolean, true if the phy is a slave
1962306a36Sopenharmony_ci *					which works together with a master
2062306a36Sopenharmony_ci *					phy to support dual link transmission,
2162306a36Sopenharmony_ci *					otherwise a regular phy or a master phy.
2262306a36Sopenharmony_ci *
2362306a36Sopenharmony_ci * This structure is used to represent the configuration state of a LVDS phy.
2462306a36Sopenharmony_ci */
2562306a36Sopenharmony_cistruct phy_configure_opts_lvds {
2662306a36Sopenharmony_ci	unsigned int	bits_per_lane_and_dclk_cycle;
2762306a36Sopenharmony_ci	unsigned long	differential_clk_rate;
2862306a36Sopenharmony_ci	unsigned int	lanes;
2962306a36Sopenharmony_ci	bool		is_slave;
3062306a36Sopenharmony_ci};
3162306a36Sopenharmony_ci
3262306a36Sopenharmony_ci#endif /* __PHY_LVDS_H_ */
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