162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright (C) 2018 Zodiac Inflight Innovations 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Author: Andrey Smirnov <andrew.smirnov@gmail.com> 662306a36Sopenharmony_ci */ 762306a36Sopenharmony_ci 862306a36Sopenharmony_ci#ifndef DT_BINDING_RESET_IMX8MQ_H 962306a36Sopenharmony_ci#define DT_BINDING_RESET_IMX8MQ_H 1062306a36Sopenharmony_ci 1162306a36Sopenharmony_ci#define IMX8MQ_RESET_A53_CORE_POR_RESET0 0 1262306a36Sopenharmony_ci#define IMX8MQ_RESET_A53_CORE_POR_RESET1 1 1362306a36Sopenharmony_ci#define IMX8MQ_RESET_A53_CORE_POR_RESET2 2 1462306a36Sopenharmony_ci#define IMX8MQ_RESET_A53_CORE_POR_RESET3 3 1562306a36Sopenharmony_ci#define IMX8MQ_RESET_A53_CORE_RESET0 4 1662306a36Sopenharmony_ci#define IMX8MQ_RESET_A53_CORE_RESET1 5 1762306a36Sopenharmony_ci#define IMX8MQ_RESET_A53_CORE_RESET2 6 1862306a36Sopenharmony_ci#define IMX8MQ_RESET_A53_CORE_RESET3 7 1962306a36Sopenharmony_ci#define IMX8MQ_RESET_A53_DBG_RESET0 8 2062306a36Sopenharmony_ci#define IMX8MQ_RESET_A53_DBG_RESET1 9 2162306a36Sopenharmony_ci#define IMX8MQ_RESET_A53_DBG_RESET2 10 2262306a36Sopenharmony_ci#define IMX8MQ_RESET_A53_DBG_RESET3 11 2362306a36Sopenharmony_ci#define IMX8MQ_RESET_A53_ETM_RESET0 12 2462306a36Sopenharmony_ci#define IMX8MQ_RESET_A53_ETM_RESET1 13 2562306a36Sopenharmony_ci#define IMX8MQ_RESET_A53_ETM_RESET2 14 2662306a36Sopenharmony_ci#define IMX8MQ_RESET_A53_ETM_RESET3 15 2762306a36Sopenharmony_ci#define IMX8MQ_RESET_A53_SOC_DBG_RESET 16 2862306a36Sopenharmony_ci#define IMX8MQ_RESET_A53_L2RESET 17 2962306a36Sopenharmony_ci#define IMX8MQ_RESET_SW_NON_SCLR_M4C_RST 18 3062306a36Sopenharmony_ci#define IMX8MQ_RESET_OTG1_PHY_RESET 19 3162306a36Sopenharmony_ci#define IMX8MQ_RESET_OTG2_PHY_RESET 20 /* i.MX8MN does NOT support */ 3262306a36Sopenharmony_ci#define IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N 21 /* i.MX8MN does NOT support */ 3362306a36Sopenharmony_ci#define IMX8MQ_RESET_MIPI_DSI_RESET_N 22 /* i.MX8MN does NOT support */ 3462306a36Sopenharmony_ci#define IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N 23 /* i.MX8MN does NOT support */ 3562306a36Sopenharmony_ci#define IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N 24 /* i.MX8MN does NOT support */ 3662306a36Sopenharmony_ci#define IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N 25 /* i.MX8MN does NOT support */ 3762306a36Sopenharmony_ci#define IMX8MQ_RESET_PCIEPHY 26 /* i.MX8MN does NOT support */ 3862306a36Sopenharmony_ci#define IMX8MQ_RESET_PCIEPHY_PERST 27 /* i.MX8MN does NOT support */ 3962306a36Sopenharmony_ci#define IMX8MQ_RESET_PCIE_CTRL_APPS_EN 28 /* i.MX8MN does NOT support */ 4062306a36Sopenharmony_ci#define IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF 29 /* i.MX8MN does NOT support */ 4162306a36Sopenharmony_ci#define IMX8MQ_RESET_HDMI_PHY_APB_RESET 30 /* i.MX8MM/i.MX8MN does NOT support */ 4262306a36Sopenharmony_ci#define IMX8MQ_RESET_DISP_RESET 31 4362306a36Sopenharmony_ci#define IMX8MQ_RESET_GPU_RESET 32 4462306a36Sopenharmony_ci#define IMX8MQ_RESET_VPU_RESET 33 /* i.MX8MN does NOT support */ 4562306a36Sopenharmony_ci#define IMX8MQ_RESET_PCIEPHY2 34 /* i.MX8MM/i.MX8MN does NOT support */ 4662306a36Sopenharmony_ci#define IMX8MQ_RESET_PCIEPHY2_PERST 35 /* i.MX8MM/i.MX8MN does NOT support */ 4762306a36Sopenharmony_ci#define IMX8MQ_RESET_PCIE2_CTRL_APPS_EN 36 /* i.MX8MM/i.MX8MN does NOT support */ 4862306a36Sopenharmony_ci#define IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF 37 /* i.MX8MM/i.MX8MN does NOT support */ 4962306a36Sopenharmony_ci#define IMX8MQ_RESET_MIPI_CSI1_CORE_RESET 38 /* i.MX8MM/i.MX8MN does NOT support */ 5062306a36Sopenharmony_ci#define IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET 39 /* i.MX8MM/i.MX8MN does NOT support */ 5162306a36Sopenharmony_ci#define IMX8MQ_RESET_MIPI_CSI1_ESC_RESET 40 /* i.MX8MM/i.MX8MN does NOT support */ 5262306a36Sopenharmony_ci#define IMX8MQ_RESET_MIPI_CSI2_CORE_RESET 41 /* i.MX8MM/i.MX8MN does NOT support */ 5362306a36Sopenharmony_ci#define IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET 42 /* i.MX8MM/i.MX8MN does NOT support */ 5462306a36Sopenharmony_ci#define IMX8MQ_RESET_MIPI_CSI2_ESC_RESET 43 /* i.MX8MM/i.MX8MN does NOT support */ 5562306a36Sopenharmony_ci#define IMX8MQ_RESET_DDRC1_PRST 44 /* i.MX8MN does NOT support */ 5662306a36Sopenharmony_ci#define IMX8MQ_RESET_DDRC1_CORE_RESET 45 /* i.MX8MN does NOT support */ 5762306a36Sopenharmony_ci#define IMX8MQ_RESET_DDRC1_PHY_RESET 46 /* i.MX8MN does NOT support */ 5862306a36Sopenharmony_ci#define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM/i.MX8MN does NOT support */ 5962306a36Sopenharmony_ci#define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM/i.MX8MN does NOT support */ 6062306a36Sopenharmony_ci#define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM/i.MX8MN does NOT support */ 6162306a36Sopenharmony_ci#define IMX8MQ_RESET_SW_M4C_RST 50 6262306a36Sopenharmony_ci#define IMX8MQ_RESET_SW_M4P_RST 51 6362306a36Sopenharmony_ci#define IMX8MQ_RESET_M4_ENABLE 52 6462306a36Sopenharmony_ci 6562306a36Sopenharmony_ci#define IMX8MQ_RESET_NUM 53 6662306a36Sopenharmony_ci 6762306a36Sopenharmony_ci#endif 68