162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Copyright (C) 2017 Impinj, Inc.
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
662306a36Sopenharmony_ci */
762306a36Sopenharmony_ci
862306a36Sopenharmony_ci#ifndef DT_BINDING_RESET_IMX7_H
962306a36Sopenharmony_ci#define DT_BINDING_RESET_IMX7_H
1062306a36Sopenharmony_ci
1162306a36Sopenharmony_ci#define IMX7_RESET_A7_CORE_POR_RESET0	0
1262306a36Sopenharmony_ci#define IMX7_RESET_A7_CORE_POR_RESET1	1
1362306a36Sopenharmony_ci#define IMX7_RESET_A7_CORE_RESET0	2
1462306a36Sopenharmony_ci#define IMX7_RESET_A7_CORE_RESET1	3
1562306a36Sopenharmony_ci#define IMX7_RESET_A7_DBG_RESET0	4
1662306a36Sopenharmony_ci#define IMX7_RESET_A7_DBG_RESET1	5
1762306a36Sopenharmony_ci#define IMX7_RESET_A7_ETM_RESET0	6
1862306a36Sopenharmony_ci#define IMX7_RESET_A7_ETM_RESET1	7
1962306a36Sopenharmony_ci#define IMX7_RESET_A7_SOC_DBG_RESET	8
2062306a36Sopenharmony_ci#define IMX7_RESET_A7_L2RESET		9
2162306a36Sopenharmony_ci#define IMX7_RESET_SW_M4C_RST		10
2262306a36Sopenharmony_ci#define IMX7_RESET_SW_M4P_RST		11
2362306a36Sopenharmony_ci#define IMX7_RESET_EIM_RST		12
2462306a36Sopenharmony_ci#define IMX7_RESET_HSICPHY_PORT_RST	13
2562306a36Sopenharmony_ci#define IMX7_RESET_USBPHY1_POR		14
2662306a36Sopenharmony_ci#define IMX7_RESET_USBPHY1_PORT_RST	15
2762306a36Sopenharmony_ci#define IMX7_RESET_USBPHY2_POR		16
2862306a36Sopenharmony_ci#define IMX7_RESET_USBPHY2_PORT_RST	17
2962306a36Sopenharmony_ci#define IMX7_RESET_MIPI_PHY_MRST	18
3062306a36Sopenharmony_ci#define IMX7_RESET_MIPI_PHY_SRST	19
3162306a36Sopenharmony_ci
3262306a36Sopenharmony_ci/*
3362306a36Sopenharmony_ci * IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN
3462306a36Sopenharmony_ci * and PCIEPHY_G_RST
3562306a36Sopenharmony_ci */
3662306a36Sopenharmony_ci#define IMX7_RESET_PCIEPHY		20
3762306a36Sopenharmony_ci#define IMX7_RESET_PCIEPHY_PERST	21
3862306a36Sopenharmony_ci
3962306a36Sopenharmony_ci/*
4062306a36Sopenharmony_ci * IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it
4162306a36Sopenharmony_ci * can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht
4262306a36Sopenharmony_ci * of as one
4362306a36Sopenharmony_ci */
4462306a36Sopenharmony_ci#define IMX7_RESET_PCIE_CTRL_APPS_EN	22
4562306a36Sopenharmony_ci#define IMX7_RESET_DDRC_PRST		23
4662306a36Sopenharmony_ci#define IMX7_RESET_DDRC_CORE_RST	24
4762306a36Sopenharmony_ci
4862306a36Sopenharmony_ci#define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25
4962306a36Sopenharmony_ci
5062306a36Sopenharmony_ci#define IMX7_RESET_NUM			26
5162306a36Sopenharmony_ci
5262306a36Sopenharmony_ci#endif
5362306a36Sopenharmony_ci
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