162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de> 462306a36Sopenharmony_ci */ 562306a36Sopenharmony_ci 662306a36Sopenharmony_ci#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H 762306a36Sopenharmony_ci#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H 862306a36Sopenharmony_ci 962306a36Sopenharmony_ci/* MPUMODRST */ 1062306a36Sopenharmony_ci#define CPU0_RESET 0 1162306a36Sopenharmony_ci#define CPU1_RESET 1 1262306a36Sopenharmony_ci#define WDS_RESET 2 1362306a36Sopenharmony_ci#define SCUPER_RESET 3 1462306a36Sopenharmony_ci#define L2_RESET 4 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci/* PERMODRST */ 1762306a36Sopenharmony_ci#define EMAC0_RESET 32 1862306a36Sopenharmony_ci#define EMAC1_RESET 33 1962306a36Sopenharmony_ci#define USB0_RESET 34 2062306a36Sopenharmony_ci#define USB1_RESET 35 2162306a36Sopenharmony_ci#define NAND_RESET 36 2262306a36Sopenharmony_ci#define QSPI_RESET 37 2362306a36Sopenharmony_ci#define L4WD0_RESET 38 2462306a36Sopenharmony_ci#define L4WD1_RESET 39 2562306a36Sopenharmony_ci#define OSC1TIMER0_RESET 40 2662306a36Sopenharmony_ci#define OSC1TIMER1_RESET 41 2762306a36Sopenharmony_ci#define SPTIMER0_RESET 42 2862306a36Sopenharmony_ci#define SPTIMER1_RESET 43 2962306a36Sopenharmony_ci#define I2C0_RESET 44 3062306a36Sopenharmony_ci#define I2C1_RESET 45 3162306a36Sopenharmony_ci#define I2C2_RESET 46 3262306a36Sopenharmony_ci#define I2C3_RESET 47 3362306a36Sopenharmony_ci#define UART0_RESET 48 3462306a36Sopenharmony_ci#define UART1_RESET 49 3562306a36Sopenharmony_ci#define SPIM0_RESET 50 3662306a36Sopenharmony_ci#define SPIM1_RESET 51 3762306a36Sopenharmony_ci#define SPIS0_RESET 52 3862306a36Sopenharmony_ci#define SPIS1_RESET 53 3962306a36Sopenharmony_ci#define SDMMC_RESET 54 4062306a36Sopenharmony_ci#define CAN0_RESET 55 4162306a36Sopenharmony_ci#define CAN1_RESET 56 4262306a36Sopenharmony_ci#define GPIO0_RESET 57 4362306a36Sopenharmony_ci#define GPIO1_RESET 58 4462306a36Sopenharmony_ci#define GPIO2_RESET 59 4562306a36Sopenharmony_ci#define DMA_RESET 60 4662306a36Sopenharmony_ci#define SDR_RESET 61 4762306a36Sopenharmony_ci 4862306a36Sopenharmony_ci/* PER2MODRST */ 4962306a36Sopenharmony_ci#define DMAIF0_RESET 64 5062306a36Sopenharmony_ci#define DMAIF1_RESET 65 5162306a36Sopenharmony_ci#define DMAIF2_RESET 66 5262306a36Sopenharmony_ci#define DMAIF3_RESET 67 5362306a36Sopenharmony_ci#define DMAIF4_RESET 68 5462306a36Sopenharmony_ci#define DMAIF5_RESET 69 5562306a36Sopenharmony_ci#define DMAIF6_RESET 70 5662306a36Sopenharmony_ci#define DMAIF7_RESET 71 5762306a36Sopenharmony_ci 5862306a36Sopenharmony_ci/* BRGMODRST */ 5962306a36Sopenharmony_ci#define HPS2FPGA_RESET 96 6062306a36Sopenharmony_ci#define LWHPS2FPGA_RESET 97 6162306a36Sopenharmony_ci#define FPGA2HPS_RESET 98 6262306a36Sopenharmony_ci 6362306a36Sopenharmony_ci/* MISCMODRST*/ 6462306a36Sopenharmony_ci#define ROM_RESET 128 6562306a36Sopenharmony_ci#define OCRAM_RESET 129 6662306a36Sopenharmony_ci#define SYSMGR_RESET 130 6762306a36Sopenharmony_ci#define SYSMGRCOLD_RESET 131 6862306a36Sopenharmony_ci#define FPGAMGR_RESET 132 6962306a36Sopenharmony_ci#define ACPIDMAP_RESET 133 7062306a36Sopenharmony_ci#define S2F_RESET 134 7162306a36Sopenharmony_ci#define S2FCOLD_RESET 135 7262306a36Sopenharmony_ci#define NRSTPIN_RESET 136 7362306a36Sopenharmony_ci#define TIMESTAMPCOLD_RESET 137 7462306a36Sopenharmony_ci#define CLKMGRCOLD_RESET 138 7562306a36Sopenharmony_ci#define SCANMGR_RESET 139 7662306a36Sopenharmony_ci#define FRZCTRLCOLD_RESET 140 7762306a36Sopenharmony_ci#define SYSDBG_RESET 141 7862306a36Sopenharmony_ci#define DBG_RESET 142 7962306a36Sopenharmony_ci#define TAPCOLD_RESET 143 8062306a36Sopenharmony_ci#define SDRCOLD_RESET 144 8162306a36Sopenharmony_ci 8262306a36Sopenharmony_ci#endif 83