162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0+ */
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Device Tree binding constants for Actions Semi S500 Reset Management Unit
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Copyright (c) 2014 Actions Semi Inc.
662306a36Sopenharmony_ci * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
762306a36Sopenharmony_ci */
862306a36Sopenharmony_ci
962306a36Sopenharmony_ci#ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H
1062306a36Sopenharmony_ci#define __DT_BINDINGS_ACTIONS_S500_RESET_H
1162306a36Sopenharmony_ci
1262306a36Sopenharmony_ci#define RESET_DMAC				0
1362306a36Sopenharmony_ci#define RESET_NORIF				1
1462306a36Sopenharmony_ci#define RESET_DDR				2
1562306a36Sopenharmony_ci#define RESET_NANDC				3
1662306a36Sopenharmony_ci#define RESET_SD0				4
1762306a36Sopenharmony_ci#define RESET_SD1				5
1862306a36Sopenharmony_ci#define RESET_PCM1				6
1962306a36Sopenharmony_ci#define RESET_DE				7
2062306a36Sopenharmony_ci#define RESET_LCD				8
2162306a36Sopenharmony_ci#define RESET_SD2				9
2262306a36Sopenharmony_ci#define RESET_DSI				10
2362306a36Sopenharmony_ci#define RESET_CSI				11
2462306a36Sopenharmony_ci#define RESET_BISP				12
2562306a36Sopenharmony_ci#define RESET_KEY				13
2662306a36Sopenharmony_ci#define RESET_GPIO				14
2762306a36Sopenharmony_ci#define RESET_AUDIO				15
2862306a36Sopenharmony_ci#define RESET_PCM0				16
2962306a36Sopenharmony_ci#define RESET_VDE				17
3062306a36Sopenharmony_ci#define RESET_VCE				18
3162306a36Sopenharmony_ci#define RESET_GPU3D				19
3262306a36Sopenharmony_ci#define RESET_NIC301				20
3362306a36Sopenharmony_ci#define RESET_LENS				21
3462306a36Sopenharmony_ci#define RESET_PERIPHRESET			22
3562306a36Sopenharmony_ci#define RESET_USB2_0				23
3662306a36Sopenharmony_ci#define RESET_TVOUT				24
3762306a36Sopenharmony_ci#define RESET_HDMI				25
3862306a36Sopenharmony_ci#define RESET_HDCP2TX				26
3962306a36Sopenharmony_ci#define RESET_UART6				27
4062306a36Sopenharmony_ci#define RESET_UART0				28
4162306a36Sopenharmony_ci#define RESET_UART1				29
4262306a36Sopenharmony_ci#define RESET_UART2				30
4362306a36Sopenharmony_ci#define RESET_SPI0				31
4462306a36Sopenharmony_ci#define RESET_SPI1				32
4562306a36Sopenharmony_ci#define RESET_SPI2				33
4662306a36Sopenharmony_ci#define RESET_SPI3				34
4762306a36Sopenharmony_ci#define RESET_I2C0				35
4862306a36Sopenharmony_ci#define RESET_I2C1				36
4962306a36Sopenharmony_ci#define RESET_USB3				37
5062306a36Sopenharmony_ci#define RESET_UART3				38
5162306a36Sopenharmony_ci#define RESET_UART4				39
5262306a36Sopenharmony_ci#define RESET_UART5				40
5362306a36Sopenharmony_ci#define RESET_I2C2				41
5462306a36Sopenharmony_ci#define RESET_I2C3				42
5562306a36Sopenharmony_ci#define RESET_ETHERNET				43
5662306a36Sopenharmony_ci#define RESET_CHIPID				44
5762306a36Sopenharmony_ci#define RESET_USB2_1				45
5862306a36Sopenharmony_ci#define RESET_WD0RESET				46
5962306a36Sopenharmony_ci#define RESET_WD1RESET				47
6062306a36Sopenharmony_ci#define RESET_WD2RESET				48
6162306a36Sopenharmony_ci#define RESET_WD3RESET				49
6262306a36Sopenharmony_ci#define RESET_DBG0RESET				50
6362306a36Sopenharmony_ci#define RESET_DBG1RESET				51
6462306a36Sopenharmony_ci#define RESET_DBG2RESET				52
6562306a36Sopenharmony_ci#define RESET_DBG3RESET				53
6662306a36Sopenharmony_ci
6762306a36Sopenharmony_ci#endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */
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