162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * Device Tree constants for the Texas Instruments DP83867 PHY 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Author: Dan Murphy <dmurphy@ti.com> 662306a36Sopenharmony_ci * 762306a36Sopenharmony_ci * Copyright: (C) 2015 Texas Instruments, Inc. 862306a36Sopenharmony_ci */ 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci#ifndef _DT_BINDINGS_TI_DP83867_H 1162306a36Sopenharmony_ci#define _DT_BINDINGS_TI_DP83867_H 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ci/* PHY CTRL bits */ 1462306a36Sopenharmony_ci#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 1562306a36Sopenharmony_ci#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 1662306a36Sopenharmony_ci#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 1762306a36Sopenharmony_ci#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 1862306a36Sopenharmony_ci 1962306a36Sopenharmony_ci/* RGMIIDCTL internal delay for rx and tx */ 2062306a36Sopenharmony_ci#define DP83867_RGMIIDCTL_250_PS 0x0 2162306a36Sopenharmony_ci#define DP83867_RGMIIDCTL_500_PS 0x1 2262306a36Sopenharmony_ci#define DP83867_RGMIIDCTL_750_PS 0x2 2362306a36Sopenharmony_ci#define DP83867_RGMIIDCTL_1_NS 0x3 2462306a36Sopenharmony_ci#define DP83867_RGMIIDCTL_1_25_NS 0x4 2562306a36Sopenharmony_ci#define DP83867_RGMIIDCTL_1_50_NS 0x5 2662306a36Sopenharmony_ci#define DP83867_RGMIIDCTL_1_75_NS 0x6 2762306a36Sopenharmony_ci#define DP83867_RGMIIDCTL_2_00_NS 0x7 2862306a36Sopenharmony_ci#define DP83867_RGMIIDCTL_2_25_NS 0x8 2962306a36Sopenharmony_ci#define DP83867_RGMIIDCTL_2_50_NS 0x9 3062306a36Sopenharmony_ci#define DP83867_RGMIIDCTL_2_75_NS 0xa 3162306a36Sopenharmony_ci#define DP83867_RGMIIDCTL_3_00_NS 0xb 3262306a36Sopenharmony_ci#define DP83867_RGMIIDCTL_3_25_NS 0xc 3362306a36Sopenharmony_ci#define DP83867_RGMIIDCTL_3_50_NS 0xd 3462306a36Sopenharmony_ci#define DP83867_RGMIIDCTL_3_75_NS 0xe 3562306a36Sopenharmony_ci#define DP83867_RGMIIDCTL_4_00_NS 0xf 3662306a36Sopenharmony_ci 3762306a36Sopenharmony_ci/* IO_MUX_CFG - Clock output selection */ 3862306a36Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 3962306a36Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 4062306a36Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 4162306a36Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 4262306a36Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 4362306a36Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 4462306a36Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 4562306a36Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 4662306a36Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 4762306a36Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 4862306a36Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA 4962306a36Sopenharmony_ci#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB 5062306a36Sopenharmony_ci#define DP83867_CLK_O_SEL_REF_CLK 0xC 5162306a36Sopenharmony_ci/* Special flag to indicate clock should be off */ 5262306a36Sopenharmony_ci#define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF 5362306a36Sopenharmony_ci#endif 54