162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 262306a36Sopenharmony_ci/* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved. */ 362306a36Sopenharmony_ci 462306a36Sopenharmony_ci/* 562306a36Sopenharmony_ci * This header provides constants for binding nvidia,tegra234-gpio*. 662306a36Sopenharmony_ci * 762306a36Sopenharmony_ci * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below 862306a36Sopenharmony_ci * provide names for this. 962306a36Sopenharmony_ci * 1062306a36Sopenharmony_ci * The second cell contains standard flag values specified in gpio.h. 1162306a36Sopenharmony_ci */ 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ci#ifndef _DT_BINDINGS_GPIO_TEGRA234_GPIO_H 1462306a36Sopenharmony_ci#define _DT_BINDINGS_GPIO_TEGRA234_GPIO_H 1562306a36Sopenharmony_ci 1662306a36Sopenharmony_ci#include <dt-bindings/gpio/gpio.h> 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ci/* GPIOs implemented by main GPIO controller */ 1962306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_A 0 2062306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_B 1 2162306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_C 2 2262306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_D 3 2362306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_E 4 2462306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_F 5 2562306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_G 6 2662306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_H 7 2762306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_I 8 2862306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_J 9 2962306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_K 10 3062306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_L 11 3162306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_M 12 3262306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_N 13 3362306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_P 14 3462306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_Q 15 3562306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_R 16 3662306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_X 17 3762306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_Y 18 3862306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_Z 19 3962306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_AC 20 4062306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_AD 21 4162306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_AE 22 4262306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_AF 23 4362306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO_PORT_AG 24 4462306a36Sopenharmony_ci 4562306a36Sopenharmony_ci#define TEGRA234_MAIN_GPIO(port, offset) \ 4662306a36Sopenharmony_ci ((TEGRA234_MAIN_GPIO_PORT_##port * 8) + offset) 4762306a36Sopenharmony_ci 4862306a36Sopenharmony_ci/* GPIOs implemented by AON GPIO controller */ 4962306a36Sopenharmony_ci#define TEGRA234_AON_GPIO_PORT_AA 0 5062306a36Sopenharmony_ci#define TEGRA234_AON_GPIO_PORT_BB 1 5162306a36Sopenharmony_ci#define TEGRA234_AON_GPIO_PORT_CC 2 5262306a36Sopenharmony_ci#define TEGRA234_AON_GPIO_PORT_DD 3 5362306a36Sopenharmony_ci#define TEGRA234_AON_GPIO_PORT_EE 4 5462306a36Sopenharmony_ci#define TEGRA234_AON_GPIO_PORT_GG 5 5562306a36Sopenharmony_ci 5662306a36Sopenharmony_ci#define TEGRA234_AON_GPIO(port, offset) \ 5762306a36Sopenharmony_ci ((TEGRA234_AON_GPIO_PORT_##port * 8) + offset) 5862306a36Sopenharmony_ci 5962306a36Sopenharmony_ci#endif 60