162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * stm32fx-clock.h
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Copyright (C) 2016 STMicroelectronics
662306a36Sopenharmony_ci * Author: Gabriel Fernandez for STMicroelectronics.
762306a36Sopenharmony_ci */
862306a36Sopenharmony_ci
962306a36Sopenharmony_ci/*
1062306a36Sopenharmony_ci * List of clocks which are not derived from system clock (SYSCLOCK)
1162306a36Sopenharmony_ci *
1262306a36Sopenharmony_ci * The index of these clocks is the secondary index of DT bindings
1362306a36Sopenharmony_ci * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt)
1462306a36Sopenharmony_ci *
1562306a36Sopenharmony_ci * e.g:
1662306a36Sopenharmony_ci	<assigned-clocks = <&rcc 1 CLK_LSE>;
1762306a36Sopenharmony_ci*/
1862306a36Sopenharmony_ci
1962306a36Sopenharmony_ci#ifndef _DT_BINDINGS_CLK_STMFX_H
2062306a36Sopenharmony_ci#define _DT_BINDINGS_CLK_STMFX_H
2162306a36Sopenharmony_ci
2262306a36Sopenharmony_ci#define SYSTICK			0
2362306a36Sopenharmony_ci#define FCLK			1
2462306a36Sopenharmony_ci#define CLK_LSI			2
2562306a36Sopenharmony_ci#define CLK_LSE			3
2662306a36Sopenharmony_ci#define CLK_HSE_RTC		4
2762306a36Sopenharmony_ci#define CLK_RTC			5
2862306a36Sopenharmony_ci#define PLL_VCO_I2S		6
2962306a36Sopenharmony_ci#define PLL_VCO_SAI		7
3062306a36Sopenharmony_ci#define CLK_LCD			8
3162306a36Sopenharmony_ci#define CLK_I2S			9
3262306a36Sopenharmony_ci#define CLK_SAI1		10
3362306a36Sopenharmony_ci#define CLK_SAI2		11
3462306a36Sopenharmony_ci#define CLK_I2SQ_PDIV		12
3562306a36Sopenharmony_ci#define CLK_SAIQ_PDIV		13
3662306a36Sopenharmony_ci#define CLK_HSI			14
3762306a36Sopenharmony_ci#define CLK_SYSCLK		15
3862306a36Sopenharmony_ci#define CLK_F469_DSI		16
3962306a36Sopenharmony_ci
4062306a36Sopenharmony_ci#define END_PRIMARY_CLK		17
4162306a36Sopenharmony_ci
4262306a36Sopenharmony_ci#define CLK_HDMI_CEC		16
4362306a36Sopenharmony_ci#define CLK_SPDIF		17
4462306a36Sopenharmony_ci#define CLK_USART1		18
4562306a36Sopenharmony_ci#define CLK_USART2		19
4662306a36Sopenharmony_ci#define CLK_USART3		20
4762306a36Sopenharmony_ci#define CLK_UART4		21
4862306a36Sopenharmony_ci#define CLK_UART5		22
4962306a36Sopenharmony_ci#define CLK_USART6		23
5062306a36Sopenharmony_ci#define CLK_UART7		24
5162306a36Sopenharmony_ci#define CLK_UART8		25
5262306a36Sopenharmony_ci#define CLK_I2C1		26
5362306a36Sopenharmony_ci#define CLK_I2C2		27
5462306a36Sopenharmony_ci#define CLK_I2C3		28
5562306a36Sopenharmony_ci#define CLK_I2C4		29
5662306a36Sopenharmony_ci#define CLK_LPTIMER		30
5762306a36Sopenharmony_ci#define CLK_PLL_SRC		31
5862306a36Sopenharmony_ci#define CLK_DFSDM1		32
5962306a36Sopenharmony_ci#define CLK_ADFSDM1		33
6062306a36Sopenharmony_ci#define CLK_F769_DSI		34
6162306a36Sopenharmony_ci#define END_PRIMARY_CLK_F7	35
6262306a36Sopenharmony_ci
6362306a36Sopenharmony_ci#endif
64