1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 4 * Author: Jeffy Chen <jeffy.chen@rock-chips.com> 5 */ 6 7#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H 8#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H 9 10/* core clocks */ 11#define PLL_APLL 1 12#define PLL_DPLL 2 13#define PLL_CPLL 3 14#define PLL_GPLL 4 15#define ARMCLK 5 16 17/* sclk gates (special clocks) */ 18#define SCLK_SPI0 65 19#define SCLK_NANDC 67 20#define SCLK_SDMMC 68 21#define SCLK_SDIO 69 22#define SCLK_EMMC 71 23#define SCLK_TSADC 72 24#define SCLK_UART0 77 25#define SCLK_UART1 78 26#define SCLK_UART2 79 27#define SCLK_I2S0 80 28#define SCLK_I2S1 81 29#define SCLK_I2S2 82 30#define SCLK_SPDIF 83 31#define SCLK_TIMER0 85 32#define SCLK_TIMER1 86 33#define SCLK_TIMER2 87 34#define SCLK_TIMER3 88 35#define SCLK_TIMER4 89 36#define SCLK_TIMER5 90 37#define SCLK_I2S_OUT 113 38#define SCLK_SDMMC_DRV 114 39#define SCLK_SDIO_DRV 115 40#define SCLK_EMMC_DRV 117 41#define SCLK_SDMMC_SAMPLE 118 42#define SCLK_SDIO_SAMPLE 119 43#define SCLK_SDIO_SRC 120 44#define SCLK_EMMC_SAMPLE 121 45#define SCLK_VOP 122 46#define SCLK_HDMI_HDCP 123 47#define SCLK_MAC_SRC 124 48#define SCLK_MAC_EXTCLK 125 49#define SCLK_MAC 126 50#define SCLK_MAC_REFOUT 127 51#define SCLK_MAC_REF 128 52#define SCLK_MAC_RX 129 53#define SCLK_MAC_TX 130 54#define SCLK_MAC_PHY 131 55#define SCLK_MAC_OUT 132 56#define SCLK_VDEC_CABAC 133 57#define SCLK_VDEC_CORE 134 58#define SCLK_RGA 135 59#define SCLK_HDCP 136 60#define SCLK_HDMI_CEC 137 61#define SCLK_CRYPTO 138 62#define SCLK_TSP 139 63#define SCLK_HSADC 140 64#define SCLK_WIFI 141 65#define SCLK_OTGPHY0 142 66#define SCLK_OTGPHY1 143 67#define SCLK_HDMI_PHY 144 68 69/* dclk gates */ 70#define DCLK_VOP 190 71#define DCLK_HDMI_PHY 191 72 73/* aclk gates */ 74#define ACLK_DMAC 194 75#define ACLK_CPU 195 76#define ACLK_VPU_PRE 196 77#define ACLK_RKVDEC_PRE 197 78#define ACLK_RGA_PRE 198 79#define ACLK_IEP_PRE 199 80#define ACLK_HDCP_PRE 200 81#define ACLK_VOP_PRE 201 82#define ACLK_VPU 202 83#define ACLK_RKVDEC 203 84#define ACLK_IEP 204 85#define ACLK_RGA 205 86#define ACLK_HDCP 206 87#define ACLK_PERI 210 88#define ACLK_VOP 211 89#define ACLK_GMAC 212 90#define ACLK_GPU 213 91 92/* pclk gates */ 93#define PCLK_GPIO0 320 94#define PCLK_GPIO1 321 95#define PCLK_GPIO2 322 96#define PCLK_GPIO3 323 97#define PCLK_VIO_H2P 324 98#define PCLK_HDCP 325 99#define PCLK_EFUSE_1024 326 100#define PCLK_EFUSE_256 327 101#define PCLK_GRF 329 102#define PCLK_I2C0 332 103#define PCLK_I2C1 333 104#define PCLK_I2C2 334 105#define PCLK_I2C3 335 106#define PCLK_SPI0 338 107#define PCLK_UART0 341 108#define PCLK_UART1 342 109#define PCLK_UART2 343 110#define PCLK_TSADC 344 111#define PCLK_PWM 350 112#define PCLK_TIMER 353 113#define PCLK_CPU 354 114#define PCLK_PERI 363 115#define PCLK_HDMI_CTRL 364 116#define PCLK_HDMI_PHY 365 117#define PCLK_GMAC 367 118 119/* hclk gates */ 120#define HCLK_I2S0_8CH 442 121#define HCLK_I2S1_8CH 443 122#define HCLK_I2S2_2CH 444 123#define HCLK_SPDIF_8CH 445 124#define HCLK_VOP 452 125#define HCLK_NANDC 453 126#define HCLK_SDMMC 456 127#define HCLK_SDIO 457 128#define HCLK_EMMC 459 129#define HCLK_CPU 460 130#define HCLK_VPU_PRE 461 131#define HCLK_RKVDEC_PRE 462 132#define HCLK_VIO_PRE 463 133#define HCLK_VPU 464 134#define HCLK_RKVDEC 465 135#define HCLK_VIO 466 136#define HCLK_RGA 467 137#define HCLK_IEP 468 138#define HCLK_VIO_H2P 469 139#define HCLK_HDCP_MMU 470 140#define HCLK_HOST0 471 141#define HCLK_HOST1 472 142#define HCLK_HOST2 473 143#define HCLK_OTG 474 144#define HCLK_TSP 475 145#define HCLK_M_CRYPTO 476 146#define HCLK_S_CRYPTO 477 147#define HCLK_PERI 478 148 149#define CLK_NR_CLKS (HCLK_PERI + 1) 150 151/* soft-reset indices */ 152#define SRST_CORE0_PO 0 153#define SRST_CORE1_PO 1 154#define SRST_CORE2_PO 2 155#define SRST_CORE3_PO 3 156#define SRST_CORE0 4 157#define SRST_CORE1 5 158#define SRST_CORE2 6 159#define SRST_CORE3 7 160#define SRST_CORE0_DBG 8 161#define SRST_CORE1_DBG 9 162#define SRST_CORE2_DBG 10 163#define SRST_CORE3_DBG 11 164#define SRST_TOPDBG 12 165#define SRST_ACLK_CORE 13 166#define SRST_NOC 14 167#define SRST_L2C 15 168 169#define SRST_CPUSYS_H 18 170#define SRST_BUSSYS_H 19 171#define SRST_SPDIF 20 172#define SRST_INTMEM 21 173#define SRST_ROM 22 174#define SRST_OTG_ADP 23 175#define SRST_I2S0 24 176#define SRST_I2S1 25 177#define SRST_I2S2 26 178#define SRST_ACODEC_P 27 179#define SRST_DFIMON 28 180#define SRST_MSCH 29 181#define SRST_EFUSE1024 30 182#define SRST_EFUSE256 31 183 184#define SRST_GPIO0 32 185#define SRST_GPIO1 33 186#define SRST_GPIO2 34 187#define SRST_GPIO3 35 188#define SRST_PERIPH_NOC_A 36 189#define SRST_PERIPH_NOC_BUS_H 37 190#define SRST_PERIPH_NOC_P 38 191#define SRST_UART0 39 192#define SRST_UART1 40 193#define SRST_UART2 41 194#define SRST_PHYNOC 42 195#define SRST_I2C0 43 196#define SRST_I2C1 44 197#define SRST_I2C2 45 198#define SRST_I2C3 46 199 200#define SRST_PWM 48 201#define SRST_A53_GIC 49 202#define SRST_DAP 51 203#define SRST_DAP_NOC 52 204#define SRST_CRYPTO 53 205#define SRST_SGRF 54 206#define SRST_GRF 55 207#define SRST_GMAC 56 208#define SRST_PERIPH_NOC_H 58 209#define SRST_MACPHY 63 210 211#define SRST_DMA 64 212#define SRST_NANDC 68 213#define SRST_USBOTG 69 214#define SRST_OTGC 70 215#define SRST_USBHOST0 71 216#define SRST_HOST_CTRL0 72 217#define SRST_USBHOST1 73 218#define SRST_HOST_CTRL1 74 219#define SRST_USBHOST2 75 220#define SRST_HOST_CTRL2 76 221#define SRST_USBPOR0 77 222#define SRST_USBPOR1 78 223#define SRST_DDRMSCH 79 224 225#define SRST_SMART_CARD 80 226#define SRST_SDMMC 81 227#define SRST_SDIO 82 228#define SRST_EMMC 83 229#define SRST_SPI 84 230#define SRST_TSP_H 85 231#define SRST_TSP 86 232#define SRST_TSADC 87 233#define SRST_DDRPHY 88 234#define SRST_DDRPHY_P 89 235#define SRST_DDRCTRL 90 236#define SRST_DDRCTRL_P 91 237#define SRST_HOST0_ECHI 92 238#define SRST_HOST1_ECHI 93 239#define SRST_HOST2_ECHI 94 240#define SRST_VOP_NOC_A 95 241 242#define SRST_HDMI_P 96 243#define SRST_VIO_ARBI_H 97 244#define SRST_IEP_NOC_A 98 245#define SRST_VIO_NOC_H 99 246#define SRST_VOP_A 100 247#define SRST_VOP_H 101 248#define SRST_VOP_D 102 249#define SRST_UTMI0 103 250#define SRST_UTMI1 104 251#define SRST_UTMI2 105 252#define SRST_UTMI3 106 253#define SRST_RGA 107 254#define SRST_RGA_NOC_A 108 255#define SRST_RGA_A 109 256#define SRST_RGA_H 110 257#define SRST_HDCP_A 111 258 259#define SRST_VPU_A 112 260#define SRST_VPU_H 113 261#define SRST_VPU_NOC_A 116 262#define SRST_VPU_NOC_H 117 263#define SRST_RKVDEC_A 118 264#define SRST_RKVDEC_NOC_A 119 265#define SRST_RKVDEC_H 120 266#define SRST_RKVDEC_NOC_H 121 267#define SRST_RKVDEC_CORE 122 268#define SRST_RKVDEC_CABAC 123 269#define SRST_IEP_A 124 270#define SRST_IEP_H 125 271#define SRST_GPU_A 126 272#define SRST_GPU_NOC_A 127 273 274#define SRST_CORE_DBG 128 275#define SRST_DBG_P 129 276#define SRST_TIMER0 130 277#define SRST_TIMER1 131 278#define SRST_TIMER2 132 279#define SRST_TIMER3 133 280#define SRST_TIMER4 134 281#define SRST_TIMER5 135 282#define SRST_VIO_H2P 136 283#define SRST_HDMIPHY 139 284#define SRST_VDAC 140 285#define SRST_TIMER_6CH_P 141 286 287#endif 288