162306a36Sopenharmony_ci/* 262306a36Sopenharmony_ci * Copyright (c) 2015 Joachim Eastwood <manabian@gmail.com> 362306a36Sopenharmony_ci * 462306a36Sopenharmony_ci * This code is released using a dual license strategy: BSD/GPL 562306a36Sopenharmony_ci * You can choose the licence that better fits your requirements. 662306a36Sopenharmony_ci * 762306a36Sopenharmony_ci * Released under the terms of 3-clause BSD License 862306a36Sopenharmony_ci * Released under the terms of GNU General Public License Version 2.0 962306a36Sopenharmony_ci * 1062306a36Sopenharmony_ci */ 1162306a36Sopenharmony_ci 1262306a36Sopenharmony_ci/* Clock Control Unit 1 (CCU1) clock offsets */ 1362306a36Sopenharmony_ci#define CLK_APB3_BUS 0x100 1462306a36Sopenharmony_ci#define CLK_APB3_I2C1 0x108 1562306a36Sopenharmony_ci#define CLK_APB3_DAC 0x110 1662306a36Sopenharmony_ci#define CLK_APB3_ADC0 0x118 1762306a36Sopenharmony_ci#define CLK_APB3_ADC1 0x120 1862306a36Sopenharmony_ci#define CLK_APB3_CAN0 0x128 1962306a36Sopenharmony_ci#define CLK_APB1_BUS 0x200 2062306a36Sopenharmony_ci#define CLK_APB1_MOTOCON_PWM 0x208 2162306a36Sopenharmony_ci#define CLK_APB1_I2C0 0x210 2262306a36Sopenharmony_ci#define CLK_APB1_I2S 0x218 2362306a36Sopenharmony_ci#define CLK_APB1_CAN1 0x220 2462306a36Sopenharmony_ci#define CLK_SPIFI 0x300 2562306a36Sopenharmony_ci#define CLK_CPU_BUS 0x400 2662306a36Sopenharmony_ci#define CLK_CPU_SPIFI 0x408 2762306a36Sopenharmony_ci#define CLK_CPU_GPIO 0x410 2862306a36Sopenharmony_ci#define CLK_CPU_LCD 0x418 2962306a36Sopenharmony_ci#define CLK_CPU_ETHERNET 0x420 3062306a36Sopenharmony_ci#define CLK_CPU_USB0 0x428 3162306a36Sopenharmony_ci#define CLK_CPU_EMC 0x430 3262306a36Sopenharmony_ci#define CLK_CPU_SDIO 0x438 3362306a36Sopenharmony_ci#define CLK_CPU_DMA 0x440 3462306a36Sopenharmony_ci#define CLK_CPU_CORE 0x448 3562306a36Sopenharmony_ci#define CLK_CPU_SCT 0x468 3662306a36Sopenharmony_ci#define CLK_CPU_USB1 0x470 3762306a36Sopenharmony_ci#define CLK_CPU_EMCDIV 0x478 3862306a36Sopenharmony_ci#define CLK_CPU_FLASHA 0x480 3962306a36Sopenharmony_ci#define CLK_CPU_FLASHB 0x488 4062306a36Sopenharmony_ci#define CLK_CPU_M0APP 0x490 4162306a36Sopenharmony_ci#define CLK_CPU_ADCHS 0x498 4262306a36Sopenharmony_ci#define CLK_CPU_EEPROM 0x4a0 4362306a36Sopenharmony_ci#define CLK_CPU_WWDT 0x500 4462306a36Sopenharmony_ci#define CLK_CPU_UART0 0x508 4562306a36Sopenharmony_ci#define CLK_CPU_UART1 0x510 4662306a36Sopenharmony_ci#define CLK_CPU_SSP0 0x518 4762306a36Sopenharmony_ci#define CLK_CPU_TIMER0 0x520 4862306a36Sopenharmony_ci#define CLK_CPU_TIMER1 0x528 4962306a36Sopenharmony_ci#define CLK_CPU_SCU 0x530 5062306a36Sopenharmony_ci#define CLK_CPU_CREG 0x538 5162306a36Sopenharmony_ci#define CLK_CPU_RITIMER 0x600 5262306a36Sopenharmony_ci#define CLK_CPU_UART2 0x608 5362306a36Sopenharmony_ci#define CLK_CPU_UART3 0x610 5462306a36Sopenharmony_ci#define CLK_CPU_TIMER2 0x618 5562306a36Sopenharmony_ci#define CLK_CPU_TIMER3 0x620 5662306a36Sopenharmony_ci#define CLK_CPU_SSP1 0x628 5762306a36Sopenharmony_ci#define CLK_CPU_QEI 0x630 5862306a36Sopenharmony_ci#define CLK_PERIPH_BUS 0x700 5962306a36Sopenharmony_ci#define CLK_PERIPH_CORE 0x710 6062306a36Sopenharmony_ci#define CLK_PERIPH_SGPIO 0x718 6162306a36Sopenharmony_ci#define CLK_USB0 0x800 6262306a36Sopenharmony_ci#define CLK_USB1 0x900 6362306a36Sopenharmony_ci#define CLK_SPI 0xA00 6462306a36Sopenharmony_ci#define CLK_ADCHS 0xB00 6562306a36Sopenharmony_ci 6662306a36Sopenharmony_ci/* Clock Control Unit 2 (CCU2) clock offsets */ 6762306a36Sopenharmony_ci#define CLK_AUDIO 0x100 6862306a36Sopenharmony_ci#define CLK_APB2_UART3 0x200 6962306a36Sopenharmony_ci#define CLK_APB2_UART2 0x300 7062306a36Sopenharmony_ci#define CLK_APB0_UART1 0x400 7162306a36Sopenharmony_ci#define CLK_APB0_UART0 0x500 7262306a36Sopenharmony_ci#define CLK_APB2_SSP1 0x600 7362306a36Sopenharmony_ci#define CLK_APB0_SSP0 0x700 7462306a36Sopenharmony_ci#define CLK_SDIO 0x800 75