162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0+ */
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Device Tree binding constants for Actions Semi S500 Clock Management Unit
462306a36Sopenharmony_ci *
562306a36Sopenharmony_ci * Copyright (c) 2014 Actions Semi Inc.
662306a36Sopenharmony_ci * Copyright (c) 2018 LSI-TEC - Caninos Loucos
762306a36Sopenharmony_ci */
862306a36Sopenharmony_ci
962306a36Sopenharmony_ci#ifndef __DT_BINDINGS_CLOCK_S500_CMU_H
1062306a36Sopenharmony_ci#define __DT_BINDINGS_CLOCK_S500_CMU_H
1162306a36Sopenharmony_ci
1262306a36Sopenharmony_ci#define CLK_NONE		0
1362306a36Sopenharmony_ci
1462306a36Sopenharmony_ci/* fixed rate clocks */
1562306a36Sopenharmony_ci#define CLK_LOSC		1
1662306a36Sopenharmony_ci#define CLK_HOSC		2
1762306a36Sopenharmony_ci
1862306a36Sopenharmony_ci/* pll clocks */
1962306a36Sopenharmony_ci#define CLK_CORE_PLL		3
2062306a36Sopenharmony_ci#define CLK_DEV_PLL		4
2162306a36Sopenharmony_ci#define CLK_DDR_PLL		5
2262306a36Sopenharmony_ci#define CLK_NAND_PLL		6
2362306a36Sopenharmony_ci#define CLK_DISPLAY_PLL		7
2462306a36Sopenharmony_ci#define CLK_ETHERNET_PLL	8
2562306a36Sopenharmony_ci#define CLK_AUDIO_PLL		9
2662306a36Sopenharmony_ci
2762306a36Sopenharmony_ci/* system clock */
2862306a36Sopenharmony_ci#define CLK_DEV			10
2962306a36Sopenharmony_ci#define CLK_H			11
3062306a36Sopenharmony_ci#define CLK_AHBPREDIV		12
3162306a36Sopenharmony_ci#define CLK_AHB			13
3262306a36Sopenharmony_ci#define CLK_DE			14
3362306a36Sopenharmony_ci#define CLK_BISP		15
3462306a36Sopenharmony_ci#define CLK_VCE			16
3562306a36Sopenharmony_ci#define CLK_VDE			17
3662306a36Sopenharmony_ci
3762306a36Sopenharmony_ci/* peripheral device clock */
3862306a36Sopenharmony_ci#define CLK_TIMER		18
3962306a36Sopenharmony_ci#define CLK_I2C0		19
4062306a36Sopenharmony_ci#define CLK_I2C1		20
4162306a36Sopenharmony_ci#define CLK_I2C2		21
4262306a36Sopenharmony_ci#define CLK_I2C3		22
4362306a36Sopenharmony_ci#define CLK_PWM0		23
4462306a36Sopenharmony_ci#define CLK_PWM1		24
4562306a36Sopenharmony_ci#define CLK_PWM2		25
4662306a36Sopenharmony_ci#define CLK_PWM3		26
4762306a36Sopenharmony_ci#define CLK_PWM4		27
4862306a36Sopenharmony_ci#define CLK_PWM5		28
4962306a36Sopenharmony_ci#define CLK_SD0			29
5062306a36Sopenharmony_ci#define CLK_SD1			30
5162306a36Sopenharmony_ci#define CLK_SD2			31
5262306a36Sopenharmony_ci#define CLK_SENSOR0		32
5362306a36Sopenharmony_ci#define CLK_SENSOR1		33
5462306a36Sopenharmony_ci#define CLK_SPI0		34
5562306a36Sopenharmony_ci#define CLK_SPI1		35
5662306a36Sopenharmony_ci#define CLK_SPI2		36
5762306a36Sopenharmony_ci#define CLK_SPI3		37
5862306a36Sopenharmony_ci#define CLK_UART0		38
5962306a36Sopenharmony_ci#define CLK_UART1		39
6062306a36Sopenharmony_ci#define CLK_UART2		40
6162306a36Sopenharmony_ci#define CLK_UART3		41
6262306a36Sopenharmony_ci#define CLK_UART4		42
6362306a36Sopenharmony_ci#define CLK_UART5		43
6462306a36Sopenharmony_ci#define CLK_UART6		44
6562306a36Sopenharmony_ci#define CLK_DE1			45
6662306a36Sopenharmony_ci#define CLK_DE2			46
6762306a36Sopenharmony_ci#define CLK_I2SRX		47
6862306a36Sopenharmony_ci#define CLK_I2STX		48
6962306a36Sopenharmony_ci#define CLK_HDMI_AUDIO		49
7062306a36Sopenharmony_ci#define CLK_HDMI		50
7162306a36Sopenharmony_ci#define CLK_SPDIF		51
7262306a36Sopenharmony_ci#define CLK_NAND		52
7362306a36Sopenharmony_ci#define CLK_ECC			53
7462306a36Sopenharmony_ci#define CLK_RMII_REF		54
7562306a36Sopenharmony_ci#define CLK_GPIO		55
7662306a36Sopenharmony_ci
7762306a36Sopenharmony_ci/* additional clocks */
7862306a36Sopenharmony_ci#define CLK_APB			56
7962306a36Sopenharmony_ci#define CLK_DMAC		57
8062306a36Sopenharmony_ci#define CLK_NIC			58
8162306a36Sopenharmony_ci#define CLK_ETHERNET		59
8262306a36Sopenharmony_ci
8362306a36Sopenharmony_ci#define CLK_NR_CLKS		(CLK_ETHERNET + 1)
8462306a36Sopenharmony_ci
8562306a36Sopenharmony_ci#endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */
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