162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-or-later
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Copyright 2005-2008 Freescale Semiconductor, Inc. All Rights Reserved.
462306a36Sopenharmony_ci * Copyright 2008 Luotao Fu, kernel@pengutronix.de
562306a36Sopenharmony_ci */
662306a36Sopenharmony_ci
762306a36Sopenharmony_ci#include <linux/clk.h>
862306a36Sopenharmony_ci#include <linux/delay.h>
962306a36Sopenharmony_ci#include <linux/io.h>
1062306a36Sopenharmony_ci#include <linux/ktime.h>
1162306a36Sopenharmony_ci#include <linux/module.h>
1262306a36Sopenharmony_ci#include <linux/mod_devicetable.h>
1362306a36Sopenharmony_ci#include <linux/platform_device.h>
1462306a36Sopenharmony_ci
1562306a36Sopenharmony_ci#include <linux/w1.h>
1662306a36Sopenharmony_ci
1762306a36Sopenharmony_ci/*
1862306a36Sopenharmony_ci * MXC W1 Register offsets
1962306a36Sopenharmony_ci */
2062306a36Sopenharmony_ci#define MXC_W1_CONTROL		0x00
2162306a36Sopenharmony_ci# define MXC_W1_CONTROL_RDST	BIT(3)
2262306a36Sopenharmony_ci# define MXC_W1_CONTROL_WR(x)	BIT(5 - (x))
2362306a36Sopenharmony_ci# define MXC_W1_CONTROL_PST	BIT(6)
2462306a36Sopenharmony_ci# define MXC_W1_CONTROL_RPP	BIT(7)
2562306a36Sopenharmony_ci#define MXC_W1_TIME_DIVIDER	0x02
2662306a36Sopenharmony_ci#define MXC_W1_RESET		0x04
2762306a36Sopenharmony_ci# define MXC_W1_RESET_RST	BIT(0)
2862306a36Sopenharmony_ci
2962306a36Sopenharmony_cistruct mxc_w1_device {
3062306a36Sopenharmony_ci	void __iomem *regs;
3162306a36Sopenharmony_ci	struct clk *clk;
3262306a36Sopenharmony_ci	struct w1_bus_master bus_master;
3362306a36Sopenharmony_ci};
3462306a36Sopenharmony_ci
3562306a36Sopenharmony_ci/*
3662306a36Sopenharmony_ci * this is the low level routine to
3762306a36Sopenharmony_ci * reset the device on the One Wire interface
3862306a36Sopenharmony_ci * on the hardware
3962306a36Sopenharmony_ci */
4062306a36Sopenharmony_cistatic u8 mxc_w1_ds2_reset_bus(void *data)
4162306a36Sopenharmony_ci{
4262306a36Sopenharmony_ci	struct mxc_w1_device *dev = data;
4362306a36Sopenharmony_ci	ktime_t timeout;
4462306a36Sopenharmony_ci
4562306a36Sopenharmony_ci	writeb(MXC_W1_CONTROL_RPP, dev->regs + MXC_W1_CONTROL);
4662306a36Sopenharmony_ci
4762306a36Sopenharmony_ci	/* Wait for reset sequence 511+512us, use 1500us for sure */
4862306a36Sopenharmony_ci	timeout = ktime_add_us(ktime_get(), 1500);
4962306a36Sopenharmony_ci
5062306a36Sopenharmony_ci	udelay(511 + 512);
5162306a36Sopenharmony_ci
5262306a36Sopenharmony_ci	do {
5362306a36Sopenharmony_ci		u8 ctrl = readb(dev->regs + MXC_W1_CONTROL);
5462306a36Sopenharmony_ci
5562306a36Sopenharmony_ci		/* PST bit is valid after the RPP bit is self-cleared */
5662306a36Sopenharmony_ci		if (!(ctrl & MXC_W1_CONTROL_RPP))
5762306a36Sopenharmony_ci			return !(ctrl & MXC_W1_CONTROL_PST);
5862306a36Sopenharmony_ci	} while (ktime_before(ktime_get(), timeout));
5962306a36Sopenharmony_ci
6062306a36Sopenharmony_ci	return 1;
6162306a36Sopenharmony_ci}
6262306a36Sopenharmony_ci
6362306a36Sopenharmony_ci/*
6462306a36Sopenharmony_ci * this is the low level routine to read/write a bit on the One Wire
6562306a36Sopenharmony_ci * interface on the hardware. It does write 0 if parameter bit is set
6662306a36Sopenharmony_ci * to 0, otherwise a write 1/read.
6762306a36Sopenharmony_ci */
6862306a36Sopenharmony_cistatic u8 mxc_w1_ds2_touch_bit(void *data, u8 bit)
6962306a36Sopenharmony_ci{
7062306a36Sopenharmony_ci	struct mxc_w1_device *dev = data;
7162306a36Sopenharmony_ci	ktime_t timeout;
7262306a36Sopenharmony_ci
7362306a36Sopenharmony_ci	writeb(MXC_W1_CONTROL_WR(bit), dev->regs + MXC_W1_CONTROL);
7462306a36Sopenharmony_ci
7562306a36Sopenharmony_ci	/* Wait for read/write bit (60us, Max 120us), use 200us for sure */
7662306a36Sopenharmony_ci	timeout = ktime_add_us(ktime_get(), 200);
7762306a36Sopenharmony_ci
7862306a36Sopenharmony_ci	udelay(60);
7962306a36Sopenharmony_ci
8062306a36Sopenharmony_ci	do {
8162306a36Sopenharmony_ci		u8 ctrl = readb(dev->regs + MXC_W1_CONTROL);
8262306a36Sopenharmony_ci
8362306a36Sopenharmony_ci		/* RDST bit is valid after the WR1/RD bit is self-cleared */
8462306a36Sopenharmony_ci		if (!(ctrl & MXC_W1_CONTROL_WR(bit)))
8562306a36Sopenharmony_ci			return !!(ctrl & MXC_W1_CONTROL_RDST);
8662306a36Sopenharmony_ci	} while (ktime_before(ktime_get(), timeout));
8762306a36Sopenharmony_ci
8862306a36Sopenharmony_ci	return 0;
8962306a36Sopenharmony_ci}
9062306a36Sopenharmony_ci
9162306a36Sopenharmony_cistatic int mxc_w1_probe(struct platform_device *pdev)
9262306a36Sopenharmony_ci{
9362306a36Sopenharmony_ci	struct mxc_w1_device *mdev;
9462306a36Sopenharmony_ci	unsigned long clkrate;
9562306a36Sopenharmony_ci	unsigned int clkdiv;
9662306a36Sopenharmony_ci	int err;
9762306a36Sopenharmony_ci
9862306a36Sopenharmony_ci	mdev = devm_kzalloc(&pdev->dev, sizeof(struct mxc_w1_device),
9962306a36Sopenharmony_ci			    GFP_KERNEL);
10062306a36Sopenharmony_ci	if (!mdev)
10162306a36Sopenharmony_ci		return -ENOMEM;
10262306a36Sopenharmony_ci
10362306a36Sopenharmony_ci	mdev->clk = devm_clk_get(&pdev->dev, NULL);
10462306a36Sopenharmony_ci	if (IS_ERR(mdev->clk))
10562306a36Sopenharmony_ci		return PTR_ERR(mdev->clk);
10662306a36Sopenharmony_ci
10762306a36Sopenharmony_ci	err = clk_prepare_enable(mdev->clk);
10862306a36Sopenharmony_ci	if (err)
10962306a36Sopenharmony_ci		return err;
11062306a36Sopenharmony_ci
11162306a36Sopenharmony_ci	clkrate = clk_get_rate(mdev->clk);
11262306a36Sopenharmony_ci	if (clkrate < 10000000)
11362306a36Sopenharmony_ci		dev_warn(&pdev->dev,
11462306a36Sopenharmony_ci			 "Low clock frequency causes improper function\n");
11562306a36Sopenharmony_ci
11662306a36Sopenharmony_ci	clkdiv = DIV_ROUND_CLOSEST(clkrate, 1000000);
11762306a36Sopenharmony_ci	clkrate /= clkdiv;
11862306a36Sopenharmony_ci	if ((clkrate < 980000) || (clkrate > 1020000))
11962306a36Sopenharmony_ci		dev_warn(&pdev->dev,
12062306a36Sopenharmony_ci			 "Incorrect time base frequency %lu Hz\n", clkrate);
12162306a36Sopenharmony_ci
12262306a36Sopenharmony_ci	mdev->regs = devm_platform_ioremap_resource(pdev, 0);
12362306a36Sopenharmony_ci	if (IS_ERR(mdev->regs)) {
12462306a36Sopenharmony_ci		err = PTR_ERR(mdev->regs);
12562306a36Sopenharmony_ci		goto out_disable_clk;
12662306a36Sopenharmony_ci	}
12762306a36Sopenharmony_ci
12862306a36Sopenharmony_ci	/* Software reset 1-Wire module */
12962306a36Sopenharmony_ci	writeb(MXC_W1_RESET_RST, mdev->regs + MXC_W1_RESET);
13062306a36Sopenharmony_ci	writeb(0, mdev->regs + MXC_W1_RESET);
13162306a36Sopenharmony_ci
13262306a36Sopenharmony_ci	writeb(clkdiv - 1, mdev->regs + MXC_W1_TIME_DIVIDER);
13362306a36Sopenharmony_ci
13462306a36Sopenharmony_ci	mdev->bus_master.data = mdev;
13562306a36Sopenharmony_ci	mdev->bus_master.reset_bus = mxc_w1_ds2_reset_bus;
13662306a36Sopenharmony_ci	mdev->bus_master.touch_bit = mxc_w1_ds2_touch_bit;
13762306a36Sopenharmony_ci
13862306a36Sopenharmony_ci	platform_set_drvdata(pdev, mdev);
13962306a36Sopenharmony_ci
14062306a36Sopenharmony_ci	err = w1_add_master_device(&mdev->bus_master);
14162306a36Sopenharmony_ci	if (err)
14262306a36Sopenharmony_ci		goto out_disable_clk;
14362306a36Sopenharmony_ci
14462306a36Sopenharmony_ci	return 0;
14562306a36Sopenharmony_ci
14662306a36Sopenharmony_ciout_disable_clk:
14762306a36Sopenharmony_ci	clk_disable_unprepare(mdev->clk);
14862306a36Sopenharmony_ci	return err;
14962306a36Sopenharmony_ci}
15062306a36Sopenharmony_ci
15162306a36Sopenharmony_ci/*
15262306a36Sopenharmony_ci * disassociate the w1 device from the driver
15362306a36Sopenharmony_ci */
15462306a36Sopenharmony_cistatic int mxc_w1_remove(struct platform_device *pdev)
15562306a36Sopenharmony_ci{
15662306a36Sopenharmony_ci	struct mxc_w1_device *mdev = platform_get_drvdata(pdev);
15762306a36Sopenharmony_ci
15862306a36Sopenharmony_ci	w1_remove_master_device(&mdev->bus_master);
15962306a36Sopenharmony_ci
16062306a36Sopenharmony_ci	clk_disable_unprepare(mdev->clk);
16162306a36Sopenharmony_ci
16262306a36Sopenharmony_ci	return 0;
16362306a36Sopenharmony_ci}
16462306a36Sopenharmony_ci
16562306a36Sopenharmony_cistatic const struct of_device_id mxc_w1_dt_ids[] = {
16662306a36Sopenharmony_ci	{ .compatible = "fsl,imx21-owire" },
16762306a36Sopenharmony_ci	{ /* sentinel */ }
16862306a36Sopenharmony_ci};
16962306a36Sopenharmony_ciMODULE_DEVICE_TABLE(of, mxc_w1_dt_ids);
17062306a36Sopenharmony_ci
17162306a36Sopenharmony_cistatic struct platform_driver mxc_w1_driver = {
17262306a36Sopenharmony_ci	.driver = {
17362306a36Sopenharmony_ci		.name = "mxc_w1",
17462306a36Sopenharmony_ci		.of_match_table = mxc_w1_dt_ids,
17562306a36Sopenharmony_ci	},
17662306a36Sopenharmony_ci	.probe = mxc_w1_probe,
17762306a36Sopenharmony_ci	.remove = mxc_w1_remove,
17862306a36Sopenharmony_ci};
17962306a36Sopenharmony_cimodule_platform_driver(mxc_w1_driver);
18062306a36Sopenharmony_ci
18162306a36Sopenharmony_ciMODULE_LICENSE("GPL");
18262306a36Sopenharmony_ciMODULE_AUTHOR("Freescale Semiconductors Inc");
18362306a36Sopenharmony_ciMODULE_DESCRIPTION("Driver for One-Wire on MXC");
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