1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * linux/drivers/video/omap2/dss/venc.c 4 * 5 * Copyright (C) 2009 Nokia Corporation 6 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 7 * 8 * VENC settings from TI's DSS driver 9 */ 10 11#define DSS_SUBSYS_NAME "VENC" 12 13#include <linux/kernel.h> 14#include <linux/module.h> 15#include <linux/clk.h> 16#include <linux/err.h> 17#include <linux/io.h> 18#include <linux/mutex.h> 19#include <linux/completion.h> 20#include <linux/delay.h> 21#include <linux/string.h> 22#include <linux/seq_file.h> 23#include <linux/platform_device.h> 24#include <linux/regulator/consumer.h> 25#include <linux/pm_runtime.h> 26#include <linux/of.h> 27#include <linux/component.h> 28 29#include <video/omapfb_dss.h> 30 31#include "dss.h" 32#include "dss_features.h" 33 34/* Venc registers */ 35#define VENC_REV_ID 0x00 36#define VENC_STATUS 0x04 37#define VENC_F_CONTROL 0x08 38#define VENC_VIDOUT_CTRL 0x10 39#define VENC_SYNC_CTRL 0x14 40#define VENC_LLEN 0x1C 41#define VENC_FLENS 0x20 42#define VENC_HFLTR_CTRL 0x24 43#define VENC_CC_CARR_WSS_CARR 0x28 44#define VENC_C_PHASE 0x2C 45#define VENC_GAIN_U 0x30 46#define VENC_GAIN_V 0x34 47#define VENC_GAIN_Y 0x38 48#define VENC_BLACK_LEVEL 0x3C 49#define VENC_BLANK_LEVEL 0x40 50#define VENC_X_COLOR 0x44 51#define VENC_M_CONTROL 0x48 52#define VENC_BSTAMP_WSS_DATA 0x4C 53#define VENC_S_CARR 0x50 54#define VENC_LINE21 0x54 55#define VENC_LN_SEL 0x58 56#define VENC_L21__WC_CTL 0x5C 57#define VENC_HTRIGGER_VTRIGGER 0x60 58#define VENC_SAVID__EAVID 0x64 59#define VENC_FLEN__FAL 0x68 60#define VENC_LAL__PHASE_RESET 0x6C 61#define VENC_HS_INT_START_STOP_X 0x70 62#define VENC_HS_EXT_START_STOP_X 0x74 63#define VENC_VS_INT_START_X 0x78 64#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C 65#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80 66#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84 67#define VENC_VS_EXT_STOP_Y 0x88 68#define VENC_AVID_START_STOP_X 0x90 69#define VENC_AVID_START_STOP_Y 0x94 70#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0 71#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4 72#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8 73#define VENC_TVDETGP_INT_START_STOP_X 0xB0 74#define VENC_TVDETGP_INT_START_STOP_Y 0xB4 75#define VENC_GEN_CTRL 0xB8 76#define VENC_OUTPUT_CONTROL 0xC4 77#define VENC_OUTPUT_TEST 0xC8 78#define VENC_DAC_B__DAC_C 0xC8 79 80struct venc_config { 81 u32 f_control; 82 u32 vidout_ctrl; 83 u32 sync_ctrl; 84 u32 llen; 85 u32 flens; 86 u32 hfltr_ctrl; 87 u32 cc_carr_wss_carr; 88 u32 c_phase; 89 u32 gain_u; 90 u32 gain_v; 91 u32 gain_y; 92 u32 black_level; 93 u32 blank_level; 94 u32 x_color; 95 u32 m_control; 96 u32 bstamp_wss_data; 97 u32 s_carr; 98 u32 line21; 99 u32 ln_sel; 100 u32 l21__wc_ctl; 101 u32 htrigger_vtrigger; 102 u32 savid__eavid; 103 u32 flen__fal; 104 u32 lal__phase_reset; 105 u32 hs_int_start_stop_x; 106 u32 hs_ext_start_stop_x; 107 u32 vs_int_start_x; 108 u32 vs_int_stop_x__vs_int_start_y; 109 u32 vs_int_stop_y__vs_ext_start_x; 110 u32 vs_ext_stop_x__vs_ext_start_y; 111 u32 vs_ext_stop_y; 112 u32 avid_start_stop_x; 113 u32 avid_start_stop_y; 114 u32 fid_int_start_x__fid_int_start_y; 115 u32 fid_int_offset_y__fid_ext_start_x; 116 u32 fid_ext_start_y__fid_ext_offset_y; 117 u32 tvdetgp_int_start_stop_x; 118 u32 tvdetgp_int_start_stop_y; 119 u32 gen_ctrl; 120}; 121 122/* from TRM */ 123static const struct venc_config venc_config_pal_trm = { 124 .f_control = 0, 125 .vidout_ctrl = 1, 126 .sync_ctrl = 0x40, 127 .llen = 0x35F, /* 863 */ 128 .flens = 0x270, /* 624 */ 129 .hfltr_ctrl = 0, 130 .cc_carr_wss_carr = 0x2F7225ED, 131 .c_phase = 0, 132 .gain_u = 0x111, 133 .gain_v = 0x181, 134 .gain_y = 0x140, 135 .black_level = 0x3B, 136 .blank_level = 0x3B, 137 .x_color = 0x7, 138 .m_control = 0x2, 139 .bstamp_wss_data = 0x3F, 140 .s_carr = 0x2A098ACB, 141 .line21 = 0, 142 .ln_sel = 0x01290015, 143 .l21__wc_ctl = 0x0000F603, 144 .htrigger_vtrigger = 0, 145 146 .savid__eavid = 0x06A70108, 147 .flen__fal = 0x00180270, 148 .lal__phase_reset = 0x00040135, 149 .hs_int_start_stop_x = 0x00880358, 150 .hs_ext_start_stop_x = 0x000F035F, 151 .vs_int_start_x = 0x01A70000, 152 .vs_int_stop_x__vs_int_start_y = 0x000001A7, 153 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000, 154 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF, 155 .vs_ext_stop_y = 0x00000025, 156 .avid_start_stop_x = 0x03530083, 157 .avid_start_stop_y = 0x026C002E, 158 .fid_int_start_x__fid_int_start_y = 0x0001008A, 159 .fid_int_offset_y__fid_ext_start_x = 0x002E0138, 160 .fid_ext_start_y__fid_ext_offset_y = 0x01380001, 161 162 .tvdetgp_int_start_stop_x = 0x00140001, 163 .tvdetgp_int_start_stop_y = 0x00010001, 164 .gen_ctrl = 0x00FF0000, 165}; 166 167/* from TRM */ 168static const struct venc_config venc_config_ntsc_trm = { 169 .f_control = 0, 170 .vidout_ctrl = 1, 171 .sync_ctrl = 0x8040, 172 .llen = 0x359, 173 .flens = 0x20C, 174 .hfltr_ctrl = 0, 175 .cc_carr_wss_carr = 0x043F2631, 176 .c_phase = 0, 177 .gain_u = 0x102, 178 .gain_v = 0x16C, 179 .gain_y = 0x12F, 180 .black_level = 0x43, 181 .blank_level = 0x38, 182 .x_color = 0x7, 183 .m_control = 0x1, 184 .bstamp_wss_data = 0x38, 185 .s_carr = 0x21F07C1F, 186 .line21 = 0, 187 .ln_sel = 0x01310011, 188 .l21__wc_ctl = 0x0000F003, 189 .htrigger_vtrigger = 0, 190 191 .savid__eavid = 0x069300F4, 192 .flen__fal = 0x0016020C, 193 .lal__phase_reset = 0x00060107, 194 .hs_int_start_stop_x = 0x008E0350, 195 .hs_ext_start_stop_x = 0x000F0359, 196 .vs_int_start_x = 0x01A00000, 197 .vs_int_stop_x__vs_int_start_y = 0x020701A0, 198 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024, 199 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC, 200 .vs_ext_stop_y = 0x00000006, 201 .avid_start_stop_x = 0x03480078, 202 .avid_start_stop_y = 0x02060024, 203 .fid_int_start_x__fid_int_start_y = 0x0001008A, 204 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106, 205 .fid_ext_start_y__fid_ext_offset_y = 0x01060006, 206 207 .tvdetgp_int_start_stop_x = 0x00140001, 208 .tvdetgp_int_start_stop_y = 0x00010001, 209 .gen_ctrl = 0x00F90000, 210}; 211 212const struct omap_video_timings omap_dss_pal_timings = { 213 .x_res = 720, 214 .y_res = 574, 215 .pixelclock = 13500000, 216 .hsw = 64, 217 .hfp = 12, 218 .hbp = 68, 219 .vsw = 5, 220 .vfp = 5, 221 .vbp = 41, 222 223 .interlace = true, 224}; 225EXPORT_SYMBOL(omap_dss_pal_timings); 226 227const struct omap_video_timings omap_dss_ntsc_timings = { 228 .x_res = 720, 229 .y_res = 482, 230 .pixelclock = 13500000, 231 .hsw = 64, 232 .hfp = 16, 233 .hbp = 58, 234 .vsw = 6, 235 .vfp = 6, 236 .vbp = 31, 237 238 .interlace = true, 239}; 240EXPORT_SYMBOL(omap_dss_ntsc_timings); 241 242static struct { 243 struct platform_device *pdev; 244 void __iomem *base; 245 struct mutex venc_lock; 246 u32 wss_data; 247 struct regulator *vdda_dac_reg; 248 249 struct clk *tv_dac_clk; 250 251 struct omap_video_timings timings; 252 enum omap_dss_venc_type type; 253 bool invert_polarity; 254 255 struct omap_dss_device output; 256} venc; 257 258static inline void venc_write_reg(int idx, u32 val) 259{ 260 __raw_writel(val, venc.base + idx); 261} 262 263static inline u32 venc_read_reg(int idx) 264{ 265 u32 l = __raw_readl(venc.base + idx); 266 return l; 267} 268 269static void venc_write_config(const struct venc_config *config) 270{ 271 DSSDBG("write venc conf\n"); 272 273 venc_write_reg(VENC_LLEN, config->llen); 274 venc_write_reg(VENC_FLENS, config->flens); 275 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr); 276 venc_write_reg(VENC_C_PHASE, config->c_phase); 277 venc_write_reg(VENC_GAIN_U, config->gain_u); 278 venc_write_reg(VENC_GAIN_V, config->gain_v); 279 venc_write_reg(VENC_GAIN_Y, config->gain_y); 280 venc_write_reg(VENC_BLACK_LEVEL, config->black_level); 281 venc_write_reg(VENC_BLANK_LEVEL, config->blank_level); 282 venc_write_reg(VENC_M_CONTROL, config->m_control); 283 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | 284 venc.wss_data); 285 venc_write_reg(VENC_S_CARR, config->s_carr); 286 venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl); 287 venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid); 288 venc_write_reg(VENC_FLEN__FAL, config->flen__fal); 289 venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset); 290 venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x); 291 venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x); 292 venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x); 293 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y, 294 config->vs_int_stop_x__vs_int_start_y); 295 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X, 296 config->vs_int_stop_y__vs_ext_start_x); 297 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y, 298 config->vs_ext_stop_x__vs_ext_start_y); 299 venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y); 300 venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x); 301 venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y); 302 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y, 303 config->fid_int_start_x__fid_int_start_y); 304 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X, 305 config->fid_int_offset_y__fid_ext_start_x); 306 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y, 307 config->fid_ext_start_y__fid_ext_offset_y); 308 309 venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C)); 310 venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl); 311 venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl); 312 venc_write_reg(VENC_X_COLOR, config->x_color); 313 venc_write_reg(VENC_LINE21, config->line21); 314 venc_write_reg(VENC_LN_SEL, config->ln_sel); 315 venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger); 316 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X, 317 config->tvdetgp_int_start_stop_x); 318 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y, 319 config->tvdetgp_int_start_stop_y); 320 venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl); 321 venc_write_reg(VENC_F_CONTROL, config->f_control); 322 venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl); 323} 324 325static void venc_reset(void) 326{ 327 int t = 1000; 328 329 venc_write_reg(VENC_F_CONTROL, 1<<8); 330 while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) { 331 if (--t == 0) { 332 DSSERR("Failed to reset venc\n"); 333 return; 334 } 335 } 336 337#ifdef CONFIG_FB_OMAP2_DSS_SLEEP_AFTER_VENC_RESET 338 /* the magical sleep that makes things work */ 339 /* XXX more info? What bug this circumvents? */ 340 msleep(20); 341#endif 342} 343 344static int venc_runtime_get(void) 345{ 346 int r; 347 348 DSSDBG("venc_runtime_get\n"); 349 350 r = pm_runtime_resume_and_get(&venc.pdev->dev); 351 if (WARN_ON(r < 0)) 352 return r; 353 return 0; 354} 355 356static void venc_runtime_put(void) 357{ 358 int r; 359 360 DSSDBG("venc_runtime_put\n"); 361 362 r = pm_runtime_put_sync(&venc.pdev->dev); 363 WARN_ON(r < 0 && r != -ENOSYS); 364} 365 366static const struct venc_config *venc_timings_to_config( 367 struct omap_video_timings *timings) 368{ 369 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0) 370 return &venc_config_pal_trm; 371 372 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0) 373 return &venc_config_ntsc_trm; 374 375 BUG(); 376 return NULL; 377} 378 379static int venc_power_on(struct omap_dss_device *dssdev) 380{ 381 struct omap_overlay_manager *mgr = venc.output.manager; 382 u32 l; 383 int r; 384 385 r = venc_runtime_get(); 386 if (r) 387 goto err0; 388 389 venc_reset(); 390 venc_write_config(venc_timings_to_config(&venc.timings)); 391 392 dss_set_venc_output(venc.type); 393 dss_set_dac_pwrdn_bgz(1); 394 395 l = 0; 396 397 if (venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE) 398 l |= 1 << 1; 399 else /* S-Video */ 400 l |= (1 << 0) | (1 << 2); 401 402 if (venc.invert_polarity == false) 403 l |= 1 << 3; 404 405 venc_write_reg(VENC_OUTPUT_CONTROL, l); 406 407 dss_mgr_set_timings(mgr, &venc.timings); 408 409 r = regulator_enable(venc.vdda_dac_reg); 410 if (r) 411 goto err1; 412 413 r = dss_mgr_enable(mgr); 414 if (r) 415 goto err2; 416 417 return 0; 418 419err2: 420 regulator_disable(venc.vdda_dac_reg); 421err1: 422 venc_write_reg(VENC_OUTPUT_CONTROL, 0); 423 dss_set_dac_pwrdn_bgz(0); 424 425 venc_runtime_put(); 426err0: 427 return r; 428} 429 430static void venc_power_off(struct omap_dss_device *dssdev) 431{ 432 struct omap_overlay_manager *mgr = venc.output.manager; 433 434 venc_write_reg(VENC_OUTPUT_CONTROL, 0); 435 dss_set_dac_pwrdn_bgz(0); 436 437 dss_mgr_disable(mgr); 438 439 regulator_disable(venc.vdda_dac_reg); 440 441 venc_runtime_put(); 442} 443 444static int venc_display_enable(struct omap_dss_device *dssdev) 445{ 446 struct omap_dss_device *out = &venc.output; 447 int r; 448 449 DSSDBG("venc_display_enable\n"); 450 451 mutex_lock(&venc.venc_lock); 452 453 if (out->manager == NULL) { 454 DSSERR("Failed to enable display: no output/manager\n"); 455 r = -ENODEV; 456 goto err0; 457 } 458 459 r = venc_power_on(dssdev); 460 if (r) 461 goto err0; 462 463 venc.wss_data = 0; 464 465 mutex_unlock(&venc.venc_lock); 466 467 return 0; 468err0: 469 mutex_unlock(&venc.venc_lock); 470 return r; 471} 472 473static void venc_display_disable(struct omap_dss_device *dssdev) 474{ 475 DSSDBG("venc_display_disable\n"); 476 477 mutex_lock(&venc.venc_lock); 478 479 venc_power_off(dssdev); 480 481 mutex_unlock(&venc.venc_lock); 482} 483 484static void venc_set_timings(struct omap_dss_device *dssdev, 485 struct omap_video_timings *timings) 486{ 487 DSSDBG("venc_set_timings\n"); 488 489 mutex_lock(&venc.venc_lock); 490 491 /* Reset WSS data when the TV standard changes. */ 492 if (memcmp(&venc.timings, timings, sizeof(*timings))) 493 venc.wss_data = 0; 494 495 venc.timings = *timings; 496 497 dispc_set_tv_pclk(13500000); 498 499 mutex_unlock(&venc.venc_lock); 500} 501 502static int venc_check_timings(struct omap_dss_device *dssdev, 503 struct omap_video_timings *timings) 504{ 505 DSSDBG("venc_check_timings\n"); 506 507 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0) 508 return 0; 509 510 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0) 511 return 0; 512 513 return -EINVAL; 514} 515 516static void venc_get_timings(struct omap_dss_device *dssdev, 517 struct omap_video_timings *timings) 518{ 519 mutex_lock(&venc.venc_lock); 520 521 *timings = venc.timings; 522 523 mutex_unlock(&venc.venc_lock); 524} 525 526static u32 venc_get_wss(struct omap_dss_device *dssdev) 527{ 528 /* Invert due to VENC_L21_WC_CTL:INV=1 */ 529 return (venc.wss_data >> 8) ^ 0xfffff; 530} 531 532static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss) 533{ 534 const struct venc_config *config; 535 int r; 536 537 DSSDBG("venc_set_wss\n"); 538 539 mutex_lock(&venc.venc_lock); 540 541 config = venc_timings_to_config(&venc.timings); 542 543 /* Invert due to VENC_L21_WC_CTL:INV=1 */ 544 venc.wss_data = (wss ^ 0xfffff) << 8; 545 546 r = venc_runtime_get(); 547 if (r) 548 goto err; 549 550 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | 551 venc.wss_data); 552 553 venc_runtime_put(); 554 555err: 556 mutex_unlock(&venc.venc_lock); 557 558 return r; 559} 560 561static void venc_set_type(struct omap_dss_device *dssdev, 562 enum omap_dss_venc_type type) 563{ 564 mutex_lock(&venc.venc_lock); 565 566 venc.type = type; 567 568 mutex_unlock(&venc.venc_lock); 569} 570 571static void venc_invert_vid_out_polarity(struct omap_dss_device *dssdev, 572 bool invert_polarity) 573{ 574 mutex_lock(&venc.venc_lock); 575 576 venc.invert_polarity = invert_polarity; 577 578 mutex_unlock(&venc.venc_lock); 579} 580 581static int venc_init_regulator(void) 582{ 583 struct regulator *vdda_dac; 584 585 if (venc.vdda_dac_reg != NULL) 586 return 0; 587 588 if (venc.pdev->dev.of_node) 589 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda"); 590 else 591 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda_dac"); 592 593 if (IS_ERR(vdda_dac)) { 594 if (PTR_ERR(vdda_dac) != -EPROBE_DEFER) 595 DSSERR("can't get VDDA_DAC regulator\n"); 596 return PTR_ERR(vdda_dac); 597 } 598 599 venc.vdda_dac_reg = vdda_dac; 600 601 return 0; 602} 603 604static void venc_dump_regs(struct seq_file *s) 605{ 606#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r)) 607 608 if (venc_runtime_get()) 609 return; 610 611 DUMPREG(VENC_F_CONTROL); 612 DUMPREG(VENC_VIDOUT_CTRL); 613 DUMPREG(VENC_SYNC_CTRL); 614 DUMPREG(VENC_LLEN); 615 DUMPREG(VENC_FLENS); 616 DUMPREG(VENC_HFLTR_CTRL); 617 DUMPREG(VENC_CC_CARR_WSS_CARR); 618 DUMPREG(VENC_C_PHASE); 619 DUMPREG(VENC_GAIN_U); 620 DUMPREG(VENC_GAIN_V); 621 DUMPREG(VENC_GAIN_Y); 622 DUMPREG(VENC_BLACK_LEVEL); 623 DUMPREG(VENC_BLANK_LEVEL); 624 DUMPREG(VENC_X_COLOR); 625 DUMPREG(VENC_M_CONTROL); 626 DUMPREG(VENC_BSTAMP_WSS_DATA); 627 DUMPREG(VENC_S_CARR); 628 DUMPREG(VENC_LINE21); 629 DUMPREG(VENC_LN_SEL); 630 DUMPREG(VENC_L21__WC_CTL); 631 DUMPREG(VENC_HTRIGGER_VTRIGGER); 632 DUMPREG(VENC_SAVID__EAVID); 633 DUMPREG(VENC_FLEN__FAL); 634 DUMPREG(VENC_LAL__PHASE_RESET); 635 DUMPREG(VENC_HS_INT_START_STOP_X); 636 DUMPREG(VENC_HS_EXT_START_STOP_X); 637 DUMPREG(VENC_VS_INT_START_X); 638 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y); 639 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X); 640 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y); 641 DUMPREG(VENC_VS_EXT_STOP_Y); 642 DUMPREG(VENC_AVID_START_STOP_X); 643 DUMPREG(VENC_AVID_START_STOP_Y); 644 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y); 645 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X); 646 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y); 647 DUMPREG(VENC_TVDETGP_INT_START_STOP_X); 648 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y); 649 DUMPREG(VENC_GEN_CTRL); 650 DUMPREG(VENC_OUTPUT_CONTROL); 651 DUMPREG(VENC_OUTPUT_TEST); 652 653 venc_runtime_put(); 654 655#undef DUMPREG 656} 657 658static int venc_get_clocks(struct platform_device *pdev) 659{ 660 struct clk *clk; 661 662 if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) { 663 clk = devm_clk_get(&pdev->dev, "tv_dac_clk"); 664 if (IS_ERR(clk)) { 665 DSSERR("can't get tv_dac_clk\n"); 666 return PTR_ERR(clk); 667 } 668 } else { 669 clk = NULL; 670 } 671 672 venc.tv_dac_clk = clk; 673 674 return 0; 675} 676 677static int venc_connect(struct omap_dss_device *dssdev, 678 struct omap_dss_device *dst) 679{ 680 struct omap_overlay_manager *mgr; 681 int r; 682 683 r = venc_init_regulator(); 684 if (r) 685 return r; 686 687 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel); 688 if (!mgr) 689 return -ENODEV; 690 691 r = dss_mgr_connect(mgr, dssdev); 692 if (r) 693 return r; 694 695 r = omapdss_output_set_device(dssdev, dst); 696 if (r) { 697 DSSERR("failed to connect output to new device: %s\n", 698 dst->name); 699 dss_mgr_disconnect(mgr, dssdev); 700 return r; 701 } 702 703 return 0; 704} 705 706static void venc_disconnect(struct omap_dss_device *dssdev, 707 struct omap_dss_device *dst) 708{ 709 WARN_ON(dst != dssdev->dst); 710 711 if (dst != dssdev->dst) 712 return; 713 714 omapdss_output_unset_device(dssdev); 715 716 if (dssdev->manager) 717 dss_mgr_disconnect(dssdev->manager, dssdev); 718} 719 720static const struct omapdss_atv_ops venc_ops = { 721 .connect = venc_connect, 722 .disconnect = venc_disconnect, 723 724 .enable = venc_display_enable, 725 .disable = venc_display_disable, 726 727 .check_timings = venc_check_timings, 728 .set_timings = venc_set_timings, 729 .get_timings = venc_get_timings, 730 731 .set_type = venc_set_type, 732 .invert_vid_out_polarity = venc_invert_vid_out_polarity, 733 734 .set_wss = venc_set_wss, 735 .get_wss = venc_get_wss, 736}; 737 738static void venc_init_output(struct platform_device *pdev) 739{ 740 struct omap_dss_device *out = &venc.output; 741 742 out->dev = &pdev->dev; 743 out->id = OMAP_DSS_OUTPUT_VENC; 744 out->output_type = OMAP_DISPLAY_TYPE_VENC; 745 out->name = "venc.0"; 746 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT; 747 out->ops.atv = &venc_ops; 748 out->owner = THIS_MODULE; 749 750 omapdss_register_output(out); 751} 752 753static void venc_uninit_output(struct platform_device *pdev) 754{ 755 struct omap_dss_device *out = &venc.output; 756 757 omapdss_unregister_output(out); 758} 759 760static int venc_probe_of(struct platform_device *pdev) 761{ 762 struct device_node *node = pdev->dev.of_node; 763 struct device_node *ep; 764 u32 channels; 765 int r; 766 767 ep = omapdss_of_get_first_endpoint(node); 768 if (!ep) 769 return 0; 770 771 venc.invert_polarity = of_property_read_bool(ep, "ti,invert-polarity"); 772 773 r = of_property_read_u32(ep, "ti,channels", &channels); 774 if (r) { 775 dev_err(&pdev->dev, 776 "failed to read property 'ti,channels': %d\n", r); 777 goto err; 778 } 779 780 switch (channels) { 781 case 1: 782 venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE; 783 break; 784 case 2: 785 venc.type = OMAP_DSS_VENC_TYPE_SVIDEO; 786 break; 787 default: 788 dev_err(&pdev->dev, "bad channel property '%d'\n", channels); 789 r = -EINVAL; 790 goto err; 791 } 792 793 of_node_put(ep); 794 795 return 0; 796err: 797 of_node_put(ep); 798 799 return 0; 800} 801 802/* VENC HW IP initialisation */ 803static int venc_bind(struct device *dev, struct device *master, void *data) 804{ 805 struct platform_device *pdev = to_platform_device(dev); 806 u8 rev_id; 807 struct resource *venc_mem; 808 int r; 809 810 venc.pdev = pdev; 811 812 mutex_init(&venc.venc_lock); 813 814 venc.wss_data = 0; 815 816 venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0); 817 if (!venc_mem) { 818 DSSERR("can't get IORESOURCE_MEM VENC\n"); 819 return -EINVAL; 820 } 821 822 venc.base = devm_ioremap(&pdev->dev, venc_mem->start, 823 resource_size(venc_mem)); 824 if (!venc.base) { 825 DSSERR("can't ioremap VENC\n"); 826 return -ENOMEM; 827 } 828 829 r = venc_get_clocks(pdev); 830 if (r) 831 return r; 832 833 pm_runtime_enable(&pdev->dev); 834 835 r = venc_runtime_get(); 836 if (r) 837 goto err_runtime_get; 838 839 rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff); 840 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id); 841 842 venc_runtime_put(); 843 844 if (pdev->dev.of_node) { 845 r = venc_probe_of(pdev); 846 if (r) { 847 DSSERR("Invalid DT data\n"); 848 goto err_probe_of; 849 } 850 } 851 852 dss_debugfs_create_file("venc", venc_dump_regs); 853 854 venc_init_output(pdev); 855 856 return 0; 857 858err_probe_of: 859err_runtime_get: 860 pm_runtime_disable(&pdev->dev); 861 return r; 862} 863 864static void venc_unbind(struct device *dev, struct device *master, void *data) 865{ 866 struct platform_device *pdev = to_platform_device(dev); 867 868 venc_uninit_output(pdev); 869 870 pm_runtime_disable(&pdev->dev); 871} 872 873static const struct component_ops venc_component_ops = { 874 .bind = venc_bind, 875 .unbind = venc_unbind, 876}; 877 878static int venc_probe(struct platform_device *pdev) 879{ 880 return component_add(&pdev->dev, &venc_component_ops); 881} 882 883static void venc_remove(struct platform_device *pdev) 884{ 885 component_del(&pdev->dev, &venc_component_ops); 886} 887 888static int venc_runtime_suspend(struct device *dev) 889{ 890 clk_disable_unprepare(venc.tv_dac_clk); 891 892 dispc_runtime_put(); 893 894 return 0; 895} 896 897static int venc_runtime_resume(struct device *dev) 898{ 899 int r; 900 901 r = dispc_runtime_get(); 902 if (r < 0) 903 return r; 904 905 clk_prepare_enable(venc.tv_dac_clk); 906 907 return 0; 908} 909 910static const struct dev_pm_ops venc_pm_ops = { 911 .runtime_suspend = venc_runtime_suspend, 912 .runtime_resume = venc_runtime_resume, 913}; 914 915static const struct of_device_id venc_of_match[] = { 916 { .compatible = "ti,omap2-venc", }, 917 { .compatible = "ti,omap3-venc", }, 918 { .compatible = "ti,omap4-venc", }, 919 {}, 920}; 921 922static struct platform_driver omap_venchw_driver = { 923 .probe = venc_probe, 924 .remove_new = venc_remove, 925 .driver = { 926 .name = "omapdss_venc", 927 .pm = &venc_pm_ops, 928 .of_match_table = venc_of_match, 929 .suppress_bind_attrs = true, 930 }, 931}; 932 933int __init venc_init_platform_driver(void) 934{ 935 return platform_driver_register(&omap_venchw_driver); 936} 937 938void venc_uninit_platform_driver(void) 939{ 940 platform_driver_unregister(&omap_venchw_driver); 941} 942