1/* 2 * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver 3 * 4 * Copyright 2004 Antonino Daplas <adaplas@pol.net> 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file COPYING in the main directory of this archive 8 * for more details. 9 * 10 */ 11 12#include <linux/aperture.h> 13#include <linux/module.h> 14#include <linux/kernel.h> 15#include <linux/errno.h> 16#include <linux/string.h> 17#include <linux/mm.h> 18#include <linux/slab.h> 19#include <linux/delay.h> 20#include <linux/fb.h> 21#include <linux/init.h> 22#include <linux/pci.h> 23#include <linux/console.h> 24#include <linux/backlight.h> 25#ifdef CONFIG_BOOTX_TEXT 26#include <asm/btext.h> 27#endif 28 29#include "nv_local.h" 30#include "nv_type.h" 31#include "nv_proto.h" 32#include "nv_dma.h" 33 34#ifdef CONFIG_FB_NVIDIA_DEBUG 35#define NVTRACE printk 36#else 37#define NVTRACE if (0) printk 38#endif 39 40#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __func__) 41#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __func__) 42 43#ifdef CONFIG_FB_NVIDIA_DEBUG 44#define assert(expr) \ 45 if (!(expr)) { \ 46 printk( "Assertion failed! %s,%s,%s,line=%d\n",\ 47 #expr,__FILE__,__func__,__LINE__); \ 48 BUG(); \ 49 } 50#else 51#define assert(expr) 52#endif 53 54#define PFX "nvidiafb: " 55 56/* HW cursor parameters */ 57#define MAX_CURS 32 58 59static const struct pci_device_id nvidiafb_pci_tbl[] = { 60 {PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 61 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0}, 62 { 0, } 63}; 64MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl); 65 66/* command line data, set in nvidiafb_setup() */ 67static int flatpanel = -1; /* Autodetect later */ 68static int fpdither = -1; 69static int forceCRTC = -1; 70static int hwcur = 0; 71static int noaccel = 0; 72static int noscale = 0; 73static int paneltweak = 0; 74static int vram = 0; 75static int bpp = 8; 76static int reverse_i2c; 77static bool nomtrr = false; 78static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT); 79 80static char *mode_option = NULL; 81 82static struct fb_fix_screeninfo nvidiafb_fix = { 83 .type = FB_TYPE_PACKED_PIXELS, 84 .xpanstep = 8, 85 .ypanstep = 1, 86}; 87 88static struct fb_var_screeninfo nvidiafb_default_var = { 89 .xres = 640, 90 .yres = 480, 91 .xres_virtual = 640, 92 .yres_virtual = 480, 93 .bits_per_pixel = 8, 94 .red = {0, 8, 0}, 95 .green = {0, 8, 0}, 96 .blue = {0, 8, 0}, 97 .transp = {0, 0, 0}, 98 .activate = FB_ACTIVATE_NOW, 99 .height = -1, 100 .width = -1, 101 .pixclock = 39721, 102 .left_margin = 40, 103 .right_margin = 24, 104 .upper_margin = 32, 105 .lower_margin = 11, 106 .hsync_len = 96, 107 .vsync_len = 2, 108 .vmode = FB_VMODE_NONINTERLACED 109}; 110 111static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8, 112 u16 bg, u16 fg, u32 w, u32 h) 113{ 114 u32 *data = (u32 *) data8; 115 int i, j, k = 0; 116 u32 b, tmp; 117 118 w = (w + 1) & ~1; 119 120 for (i = 0; i < h; i++) { 121 b = *data++; 122 reverse_order(&b); 123 124 for (j = 0; j < w / 2; j++) { 125 tmp = 0; 126#if defined (__BIG_ENDIAN) 127 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16; 128 b <<= 1; 129 tmp |= (b & (1 << 31)) ? fg : bg; 130 b <<= 1; 131#else 132 tmp = (b & 1) ? fg : bg; 133 b >>= 1; 134 tmp |= (b & 1) ? fg << 16 : bg << 16; 135 b >>= 1; 136#endif 137 NV_WR32(&par->CURSOR[k++], 0, tmp); 138 } 139 k += (MAX_CURS - w) / 2; 140 } 141} 142 143static void nvidia_write_clut(struct nvidia_par *par, 144 u8 regnum, u8 red, u8 green, u8 blue) 145{ 146 NVWriteDacMask(par, 0xff); 147 NVWriteDacWriteAddr(par, regnum); 148 NVWriteDacData(par, red); 149 NVWriteDacData(par, green); 150 NVWriteDacData(par, blue); 151} 152 153static void nvidia_read_clut(struct nvidia_par *par, 154 u8 regnum, u8 * red, u8 * green, u8 * blue) 155{ 156 NVWriteDacMask(par, 0xff); 157 NVWriteDacReadAddr(par, regnum); 158 *red = NVReadDacData(par); 159 *green = NVReadDacData(par); 160 *blue = NVReadDacData(par); 161} 162 163static int nvidia_panel_tweak(struct nvidia_par *par, 164 struct _riva_hw_state *state) 165{ 166 int tweak = 0; 167 168 if (par->paneltweak) { 169 tweak = par->paneltweak; 170 } else { 171 /* Begin flat panel hacks. 172 * This is unfortunate, but some chips need this register 173 * tweaked or else you get artifacts where adjacent pixels are 174 * swapped. There are no hard rules for what to set here so all 175 * we can do is experiment and apply hacks. 176 */ 177 if (((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) { 178 /* At least one NV34 laptop needs this workaround. */ 179 tweak = -1; 180 } 181 182 if ((par->Chipset & 0xfff0) == 0x0310) 183 tweak = 1; 184 /* end flat panel hacks */ 185 } 186 187 return tweak; 188} 189 190static void nvidia_screen_off(struct nvidia_par *par, int on) 191{ 192 unsigned char tmp; 193 194 if (on) { 195 /* 196 * Turn off screen and disable sequencer. 197 */ 198 tmp = NVReadSeq(par, 0x01); 199 200 NVWriteSeq(par, 0x00, 0x01); /* Synchronous Reset */ 201 NVWriteSeq(par, 0x01, tmp | 0x20); /* disable the display */ 202 } else { 203 /* 204 * Reenable sequencer, then turn on screen. 205 */ 206 207 tmp = NVReadSeq(par, 0x01); 208 209 NVWriteSeq(par, 0x01, tmp & ~0x20); /* reenable display */ 210 NVWriteSeq(par, 0x00, 0x03); /* End Reset */ 211 } 212} 213 214static void nvidia_save_vga(struct nvidia_par *par, 215 struct _riva_hw_state *state) 216{ 217 int i; 218 219 NVTRACE_ENTER(); 220 NVLockUnlock(par, 0); 221 222 NVUnloadStateExt(par, state); 223 224 state->misc_output = NVReadMiscOut(par); 225 226 for (i = 0; i < NUM_CRT_REGS; i++) 227 state->crtc[i] = NVReadCrtc(par, i); 228 229 for (i = 0; i < NUM_ATC_REGS; i++) 230 state->attr[i] = NVReadAttr(par, i); 231 232 for (i = 0; i < NUM_GRC_REGS; i++) 233 state->gra[i] = NVReadGr(par, i); 234 235 for (i = 0; i < NUM_SEQ_REGS; i++) 236 state->seq[i] = NVReadSeq(par, i); 237 NVTRACE_LEAVE(); 238} 239 240#undef DUMP_REG 241 242static void nvidia_write_regs(struct nvidia_par *par, 243 struct _riva_hw_state *state) 244{ 245 int i; 246 247 NVTRACE_ENTER(); 248 249 NVLoadStateExt(par, state); 250 251 NVWriteMiscOut(par, state->misc_output); 252 253 for (i = 1; i < NUM_SEQ_REGS; i++) { 254#ifdef DUMP_REG 255 printk(" SEQ[%02x] = %08x\n", i, state->seq[i]); 256#endif 257 NVWriteSeq(par, i, state->seq[i]); 258 } 259 260 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 of CRTC[17] */ 261 NVWriteCrtc(par, 0x11, state->crtc[0x11] & ~0x80); 262 263 for (i = 0; i < NUM_CRT_REGS; i++) { 264 switch (i) { 265 case 0x19: 266 case 0x20 ... 0x40: 267 break; 268 default: 269#ifdef DUMP_REG 270 printk("CRTC[%02x] = %08x\n", i, state->crtc[i]); 271#endif 272 NVWriteCrtc(par, i, state->crtc[i]); 273 } 274 } 275 276 for (i = 0; i < NUM_GRC_REGS; i++) { 277#ifdef DUMP_REG 278 printk(" GRA[%02x] = %08x\n", i, state->gra[i]); 279#endif 280 NVWriteGr(par, i, state->gra[i]); 281 } 282 283 for (i = 0; i < NUM_ATC_REGS; i++) { 284#ifdef DUMP_REG 285 printk("ATTR[%02x] = %08x\n", i, state->attr[i]); 286#endif 287 NVWriteAttr(par, i, state->attr[i]); 288 } 289 290 NVTRACE_LEAVE(); 291} 292 293static int nvidia_calc_regs(struct fb_info *info) 294{ 295 struct nvidia_par *par = info->par; 296 struct _riva_hw_state *state = &par->ModeReg; 297 int i, depth = fb_get_color_depth(&info->var, &info->fix); 298 int h_display = info->var.xres / 8 - 1; 299 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1; 300 int h_end = (info->var.xres + info->var.right_margin + 301 info->var.hsync_len) / 8 - 1; 302 int h_total = (info->var.xres + info->var.right_margin + 303 info->var.hsync_len + info->var.left_margin) / 8 - 5; 304 int h_blank_s = h_display; 305 int h_blank_e = h_total + 4; 306 int v_display = info->var.yres - 1; 307 int v_start = info->var.yres + info->var.lower_margin - 1; 308 int v_end = (info->var.yres + info->var.lower_margin + 309 info->var.vsync_len) - 1; 310 int v_total = (info->var.yres + info->var.lower_margin + 311 info->var.vsync_len + info->var.upper_margin) - 2; 312 int v_blank_s = v_display; 313 int v_blank_e = v_total + 1; 314 315 /* 316 * Set all CRTC values. 317 */ 318 319 if (info->var.vmode & FB_VMODE_INTERLACED) 320 v_total |= 1; 321 322 if (par->FlatPanel == 1) { 323 v_start = v_total - 3; 324 v_end = v_total - 2; 325 v_blank_s = v_start; 326 h_start = h_total - 5; 327 h_end = h_total - 2; 328 h_blank_e = h_total + 4; 329 } 330 331 state->crtc[0x0] = Set8Bits(h_total); 332 state->crtc[0x1] = Set8Bits(h_display); 333 state->crtc[0x2] = Set8Bits(h_blank_s); 334 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0) 335 | SetBit(7); 336 state->crtc[0x4] = Set8Bits(h_start); 337 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7) 338 | SetBitField(h_end, 4: 0, 4:0); 339 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0); 340 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0) 341 | SetBitField(v_display, 8: 8, 1:1) 342 | SetBitField(v_start, 8: 8, 2:2) 343 | SetBitField(v_blank_s, 8: 8, 3:3) 344 | SetBit(4) 345 | SetBitField(v_total, 9: 9, 5:5) 346 | SetBitField(v_display, 9: 9, 6:6) 347 | SetBitField(v_start, 9: 9, 7:7); 348 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5) 349 | SetBit(6) 350 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00); 351 state->crtc[0x10] = Set8Bits(v_start); 352 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5); 353 state->crtc[0x12] = Set8Bits(v_display); 354 state->crtc[0x13] = ((info->var.xres_virtual / 8) * 355 (info->var.bits_per_pixel / 8)); 356 state->crtc[0x15] = Set8Bits(v_blank_s); 357 state->crtc[0x16] = Set8Bits(v_blank_e); 358 359 state->attr[0x10] = 0x01; 360 361 if (par->Television) 362 state->attr[0x11] = 0x00; 363 364 state->screen = SetBitField(h_blank_e, 6: 6, 4:4) 365 | SetBitField(v_blank_s, 10: 10, 3:3) 366 | SetBitField(v_start, 10: 10, 2:2) 367 | SetBitField(v_display, 10: 10, 1:1) 368 | SetBitField(v_total, 10: 10, 0:0); 369 370 state->horiz = SetBitField(h_total, 8: 8, 0:0) 371 | SetBitField(h_display, 8: 8, 1:1) 372 | SetBitField(h_blank_s, 8: 8, 2:2) 373 | SetBitField(h_start, 8: 8, 3:3); 374 375 state->extra = SetBitField(v_total, 11: 11, 0:0) 376 | SetBitField(v_display, 11: 11, 2:2) 377 | SetBitField(v_start, 11: 11, 4:4) 378 | SetBitField(v_blank_s, 11: 11, 6:6); 379 380 if (info->var.vmode & FB_VMODE_INTERLACED) { 381 h_total = (h_total >> 1) & ~1; 382 state->interlace = Set8Bits(h_total); 383 state->horiz |= SetBitField(h_total, 8: 8, 4:4); 384 } else { 385 state->interlace = 0xff; /* interlace off */ 386 } 387 388 /* 389 * Calculate the extended registers. 390 */ 391 392 if (depth < 24) 393 i = depth; 394 else 395 i = 32; 396 397 if (par->Architecture >= NV_ARCH_10) 398 par->CURSOR = (volatile u32 __iomem *)(info->screen_base + 399 par->CursorStart); 400 401 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) 402 state->misc_output &= ~0x40; 403 else 404 state->misc_output |= 0x40; 405 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) 406 state->misc_output &= ~0x80; 407 else 408 state->misc_output |= 0x80; 409 410 NVCalcStateExt(par, state, i, info->var.xres_virtual, 411 info->var.xres, info->var.yres_virtual, 412 1000000000 / info->var.pixclock, info->var.vmode); 413 414 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff; 415 if (par->FlatPanel == 1) { 416 state->pixel |= (1 << 7); 417 418 if (!par->fpScaler || (par->fpWidth <= info->var.xres) 419 || (par->fpHeight <= info->var.yres)) { 420 state->scale |= (1 << 8); 421 } 422 423 if (!par->crtcSync_read) { 424 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828); 425 par->crtcSync_read = 1; 426 } 427 428 par->PanelTweak = nvidia_panel_tweak(par, state); 429 } 430 431 state->vpll = state->pll; 432 state->vpll2 = state->pll; 433 state->vpllB = state->pllB; 434 state->vpll2B = state->pllB; 435 436 VGA_WR08(par->PCIO, 0x03D4, 0x1C); 437 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5); 438 439 if (par->CRTCnumber) { 440 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000; 441 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000; 442 state->crtcOwner = 3; 443 state->pllsel |= 0x20000800; 444 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508); 445 if (par->twoStagePLL) 446 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578); 447 } else if (par->twoHeads) { 448 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000; 449 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000; 450 state->crtcOwner = 0; 451 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520); 452 if (par->twoStagePLL) 453 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C); 454 } 455 456 state->cursorConfig = 0x00000100; 457 458 if (info->var.vmode & FB_VMODE_DOUBLE) 459 state->cursorConfig |= (1 << 4); 460 461 if (par->alphaCursor) { 462 if ((par->Chipset & 0x0ff0) != 0x0110) 463 state->cursorConfig |= 0x04011000; 464 else 465 state->cursorConfig |= 0x14011000; 466 state->general |= (1 << 29); 467 } else 468 state->cursorConfig |= 0x02000000; 469 470 if (par->twoHeads) { 471 if ((par->Chipset & 0x0ff0) == 0x0110) { 472 state->dither = NV_RD32(par->PRAMDAC, 0x0528) & 473 ~0x00010000; 474 if (par->FPDither) 475 state->dither |= 0x00010000; 476 } else { 477 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1; 478 if (par->FPDither) 479 state->dither |= 1; 480 } 481 } 482 483 state->timingH = 0; 484 state->timingV = 0; 485 state->displayV = info->var.xres; 486 487 return 0; 488} 489 490static void nvidia_init_vga(struct fb_info *info) 491{ 492 struct nvidia_par *par = info->par; 493 struct _riva_hw_state *state = &par->ModeReg; 494 int i; 495 496 for (i = 0; i < 0x10; i++) 497 state->attr[i] = i; 498 state->attr[0x10] = 0x41; 499 state->attr[0x11] = 0xff; 500 state->attr[0x12] = 0x0f; 501 state->attr[0x13] = 0x00; 502 state->attr[0x14] = 0x00; 503 504 memset(state->crtc, 0x00, NUM_CRT_REGS); 505 state->crtc[0x0a] = 0x20; 506 state->crtc[0x17] = 0xe3; 507 state->crtc[0x18] = 0xff; 508 state->crtc[0x28] = 0x40; 509 510 memset(state->gra, 0x00, NUM_GRC_REGS); 511 state->gra[0x05] = 0x40; 512 state->gra[0x06] = 0x05; 513 state->gra[0x07] = 0x0f; 514 state->gra[0x08] = 0xff; 515 516 state->seq[0x00] = 0x03; 517 state->seq[0x01] = 0x01; 518 state->seq[0x02] = 0x0f; 519 state->seq[0x03] = 0x00; 520 state->seq[0x04] = 0x0e; 521 522 state->misc_output = 0xeb; 523} 524 525static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor) 526{ 527 struct nvidia_par *par = info->par; 528 u8 data[MAX_CURS * MAX_CURS / 8]; 529 int i, set = cursor->set; 530 u16 fg, bg; 531 532 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS) 533 return -ENXIO; 534 535 NVShowHideCursor(par, 0); 536 537 if (par->cursor_reset) { 538 set = FB_CUR_SETALL; 539 par->cursor_reset = 0; 540 } 541 542 if (set & FB_CUR_SETSIZE) 543 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2); 544 545 if (set & FB_CUR_SETPOS) { 546 u32 xx, yy, temp; 547 548 yy = cursor->image.dy - info->var.yoffset; 549 xx = cursor->image.dx - info->var.xoffset; 550 temp = xx & 0xFFFF; 551 temp |= yy << 16; 552 553 NV_WR32(par->PRAMDAC, 0x0000300, temp); 554 } 555 556 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) { 557 u32 bg_idx = cursor->image.bg_color; 558 u32 fg_idx = cursor->image.fg_color; 559 u32 s_pitch = (cursor->image.width + 7) >> 3; 560 u32 d_pitch = MAX_CURS / 8; 561 u8 *dat = (u8 *) cursor->image.data; 562 u8 *msk = (u8 *) cursor->mask; 563 u8 *src; 564 565 src = kmalloc_array(s_pitch, cursor->image.height, GFP_ATOMIC); 566 567 if (src) { 568 switch (cursor->rop) { 569 case ROP_XOR: 570 for (i = 0; i < s_pitch * cursor->image.height; i++) 571 src[i] = dat[i] ^ msk[i]; 572 break; 573 case ROP_COPY: 574 default: 575 for (i = 0; i < s_pitch * cursor->image.height; i++) 576 src[i] = dat[i] & msk[i]; 577 break; 578 } 579 580 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch, 581 cursor->image.height); 582 583 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) | 584 ((info->cmap.green[bg_idx] & 0xf8) << 2) | 585 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15; 586 587 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) | 588 ((info->cmap.green[fg_idx] & 0xf8) << 2) | 589 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15; 590 591 NVLockUnlock(par, 0); 592 593 nvidiafb_load_cursor_image(par, data, bg, fg, 594 cursor->image.width, 595 cursor->image.height); 596 kfree(src); 597 } 598 } 599 600 if (cursor->enable) 601 NVShowHideCursor(par, 1); 602 603 return 0; 604} 605 606static struct fb_ops nvidia_fb_ops; 607 608static int nvidiafb_set_par(struct fb_info *info) 609{ 610 struct nvidia_par *par = info->par; 611 612 NVTRACE_ENTER(); 613 614 NVLockUnlock(par, 1); 615 if (!par->FlatPanel || !par->twoHeads) 616 par->FPDither = 0; 617 618 if (par->FPDither < 0) { 619 if ((par->Chipset & 0x0ff0) == 0x0110) 620 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x0528) 621 & 0x00010000); 622 else 623 par->FPDither = !!(NV_RD32(par->PRAMDAC, 0x083C) & 1); 624 printk(KERN_INFO PFX "Flat panel dithering %s\n", 625 par->FPDither ? "enabled" : "disabled"); 626 } 627 628 info->fix.visual = (info->var.bits_per_pixel == 8) ? 629 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 630 631 nvidia_init_vga(info); 632 nvidia_calc_regs(info); 633 634 NVLockUnlock(par, 0); 635 if (par->twoHeads) { 636 VGA_WR08(par->PCIO, 0x03D4, 0x44); 637 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner); 638 NVLockUnlock(par, 0); 639 } 640 641 nvidia_screen_off(par, 1); 642 643 nvidia_write_regs(par, &par->ModeReg); 644 NVSetStartAddress(par, 0); 645 646#if defined (__BIG_ENDIAN) 647 /* turn on LFB swapping */ 648 { 649 unsigned char tmp; 650 651 VGA_WR08(par->PCIO, 0x3d4, 0x46); 652 tmp = VGA_RD08(par->PCIO, 0x3d5); 653 tmp |= (1 << 7); 654 VGA_WR08(par->PCIO, 0x3d5, tmp); 655 } 656#endif 657 658 info->fix.line_length = (info->var.xres_virtual * 659 info->var.bits_per_pixel) >> 3; 660 if (info->var.accel_flags) { 661 nvidia_fb_ops.fb_imageblit = nvidiafb_imageblit; 662 nvidia_fb_ops.fb_fillrect = nvidiafb_fillrect; 663 nvidia_fb_ops.fb_copyarea = nvidiafb_copyarea; 664 nvidia_fb_ops.fb_sync = nvidiafb_sync; 665 info->pixmap.scan_align = 4; 666 info->flags &= ~FBINFO_HWACCEL_DISABLED; 667 info->flags |= FBINFO_READS_FAST; 668 NVResetGraphics(info); 669 } else { 670 nvidia_fb_ops.fb_imageblit = cfb_imageblit; 671 nvidia_fb_ops.fb_fillrect = cfb_fillrect; 672 nvidia_fb_ops.fb_copyarea = cfb_copyarea; 673 nvidia_fb_ops.fb_sync = NULL; 674 info->pixmap.scan_align = 1; 675 info->flags |= FBINFO_HWACCEL_DISABLED; 676 info->flags &= ~FBINFO_READS_FAST; 677 } 678 679 par->cursor_reset = 1; 680 681 nvidia_screen_off(par, 0); 682 683#ifdef CONFIG_BOOTX_TEXT 684 /* Update debug text engine */ 685 btext_update_display(info->fix.smem_start, 686 info->var.xres, info->var.yres, 687 info->var.bits_per_pixel, info->fix.line_length); 688#endif 689 690 NVLockUnlock(par, 0); 691 NVTRACE_LEAVE(); 692 return 0; 693} 694 695static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green, 696 unsigned blue, unsigned transp, 697 struct fb_info *info) 698{ 699 struct nvidia_par *par = info->par; 700 int i; 701 702 NVTRACE_ENTER(); 703 if (regno >= (1 << info->var.green.length)) 704 return -EINVAL; 705 706 if (info->var.grayscale) { 707 /* gray = 0.30*R + 0.59*G + 0.11*B */ 708 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8; 709 } 710 711 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) { 712 ((u32 *) info->pseudo_palette)[regno] = 713 (regno << info->var.red.offset) | 714 (regno << info->var.green.offset) | 715 (regno << info->var.blue.offset); 716 } 717 718 switch (info->var.bits_per_pixel) { 719 case 8: 720 /* "transparent" stuff is completely ignored. */ 721 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8); 722 break; 723 case 16: 724 if (info->var.green.length == 5) { 725 for (i = 0; i < 8; i++) { 726 nvidia_write_clut(par, regno * 8 + i, red >> 8, 727 green >> 8, blue >> 8); 728 } 729 } else { 730 u8 r, g, b; 731 732 if (regno < 32) { 733 for (i = 0; i < 8; i++) { 734 nvidia_write_clut(par, regno * 8 + i, 735 red >> 8, green >> 8, 736 blue >> 8); 737 } 738 } 739 740 nvidia_read_clut(par, regno * 4, &r, &g, &b); 741 742 for (i = 0; i < 4; i++) 743 nvidia_write_clut(par, regno * 4 + i, r, 744 green >> 8, b); 745 } 746 break; 747 case 32: 748 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8); 749 break; 750 default: 751 /* do nothing */ 752 break; 753 } 754 755 NVTRACE_LEAVE(); 756 return 0; 757} 758 759static int nvidiafb_check_var(struct fb_var_screeninfo *var, 760 struct fb_info *info) 761{ 762 struct nvidia_par *par = info->par; 763 int memlen, vramlen, mode_valid = 0; 764 int pitch, err = 0; 765 766 NVTRACE_ENTER(); 767 if (!var->pixclock) 768 return -EINVAL; 769 770 var->transp.offset = 0; 771 var->transp.length = 0; 772 773 var->xres &= ~7; 774 775 if (var->bits_per_pixel <= 8) 776 var->bits_per_pixel = 8; 777 else if (var->bits_per_pixel <= 16) 778 var->bits_per_pixel = 16; 779 else 780 var->bits_per_pixel = 32; 781 782 switch (var->bits_per_pixel) { 783 case 8: 784 var->red.offset = 0; 785 var->red.length = 8; 786 var->green.offset = 0; 787 var->green.length = 8; 788 var->blue.offset = 0; 789 var->blue.length = 8; 790 var->transp.offset = 0; 791 var->transp.length = 0; 792 break; 793 case 16: 794 var->green.length = (var->green.length < 6) ? 5 : 6; 795 var->red.length = 5; 796 var->blue.length = 5; 797 var->transp.length = 6 - var->green.length; 798 var->blue.offset = 0; 799 var->green.offset = 5; 800 var->red.offset = 5 + var->green.length; 801 var->transp.offset = (5 + var->red.offset) & 15; 802 break; 803 case 32: /* RGBA 8888 */ 804 var->red.offset = 16; 805 var->red.length = 8; 806 var->green.offset = 8; 807 var->green.length = 8; 808 var->blue.offset = 0; 809 var->blue.length = 8; 810 var->transp.length = 8; 811 var->transp.offset = 24; 812 break; 813 } 814 815 var->red.msb_right = 0; 816 var->green.msb_right = 0; 817 var->blue.msb_right = 0; 818 var->transp.msb_right = 0; 819 820 if (!info->monspecs.hfmax || !info->monspecs.vfmax || 821 !info->monspecs.dclkmax || !fb_validate_mode(var, info)) 822 mode_valid = 1; 823 824 /* calculate modeline if supported by monitor */ 825 if (!mode_valid && info->monspecs.gtf) { 826 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info)) 827 mode_valid = 1; 828 } 829 830 if (!mode_valid) { 831 const struct fb_videomode *mode; 832 833 mode = fb_find_best_mode(var, &info->modelist); 834 if (mode) { 835 fb_videomode_to_var(var, mode); 836 mode_valid = 1; 837 } 838 } 839 840 if (!mode_valid && info->monspecs.modedb_len) 841 return -EINVAL; 842 843 /* 844 * If we're on a flat panel, check if the mode is outside of the 845 * panel dimensions. If so, cap it and try for the next best mode 846 * before bailing out. 847 */ 848 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres || 849 par->fpHeight < var->yres)) { 850 const struct fb_videomode *mode; 851 852 var->xres = par->fpWidth; 853 var->yres = par->fpHeight; 854 855 mode = fb_find_best_mode(var, &info->modelist); 856 if (!mode) { 857 printk(KERN_ERR PFX "mode out of range of flat " 858 "panel dimensions\n"); 859 return -EINVAL; 860 } 861 862 fb_videomode_to_var(var, mode); 863 } 864 865 if (var->yres_virtual < var->yres) 866 var->yres_virtual = var->yres; 867 868 if (var->xres_virtual < var->xres) 869 var->xres_virtual = var->xres; 870 871 var->xres_virtual = (var->xres_virtual + 63) & ~63; 872 873 vramlen = info->screen_size; 874 pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8; 875 memlen = pitch * var->yres_virtual; 876 877 if (memlen > vramlen) { 878 var->yres_virtual = vramlen / pitch; 879 880 if (var->yres_virtual < var->yres) { 881 var->yres_virtual = var->yres; 882 var->xres_virtual = vramlen / var->yres_virtual; 883 var->xres_virtual /= var->bits_per_pixel / 8; 884 var->xres_virtual &= ~63; 885 pitch = (var->xres_virtual * 886 var->bits_per_pixel + 7) / 8; 887 memlen = pitch * var->yres; 888 889 if (var->xres_virtual < var->xres) { 890 printk("nvidiafb: required video memory, " 891 "%d bytes, for %dx%d-%d (virtual) " 892 "is out of range\n", 893 memlen, var->xres_virtual, 894 var->yres_virtual, var->bits_per_pixel); 895 err = -ENOMEM; 896 } 897 } 898 } 899 900 if (var->accel_flags) { 901 if (var->yres_virtual > 0x7fff) 902 var->yres_virtual = 0x7fff; 903 if (var->xres_virtual > 0x7fff) 904 var->xres_virtual = 0x7fff; 905 } 906 907 var->xres_virtual &= ~63; 908 909 NVTRACE_LEAVE(); 910 911 return err; 912} 913 914static int nvidiafb_pan_display(struct fb_var_screeninfo *var, 915 struct fb_info *info) 916{ 917 struct nvidia_par *par = info->par; 918 u32 total; 919 920 total = var->yoffset * info->fix.line_length + var->xoffset; 921 922 NVSetStartAddress(par, total); 923 924 return 0; 925} 926 927static int nvidiafb_blank(int blank, struct fb_info *info) 928{ 929 struct nvidia_par *par = info->par; 930 unsigned char tmp, vesa; 931 932 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */ 933 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */ 934 935 NVTRACE_ENTER(); 936 937 if (blank) 938 tmp |= 0x20; 939 940 switch (blank) { 941 case FB_BLANK_UNBLANK: 942 case FB_BLANK_NORMAL: 943 break; 944 case FB_BLANK_VSYNC_SUSPEND: 945 vesa |= 0x80; 946 break; 947 case FB_BLANK_HSYNC_SUSPEND: 948 vesa |= 0x40; 949 break; 950 case FB_BLANK_POWERDOWN: 951 vesa |= 0xc0; 952 break; 953 } 954 955 NVWriteSeq(par, 0x01, tmp); 956 NVWriteCrtc(par, 0x1a, vesa); 957 958 NVTRACE_LEAVE(); 959 960 return 0; 961} 962 963/* 964 * Because the VGA registers are not mapped linearly in its MMIO space, 965 * restrict VGA register saving and restore to x86 only, where legacy VGA IO 966 * access is legal. Consequently, we must also check if the device is the 967 * primary display. 968 */ 969#ifdef CONFIG_X86 970static void save_vga_x86(struct nvidia_par *par) 971{ 972 struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE]; 973 974 if (res && res->flags & IORESOURCE_ROM_SHADOW) { 975 memset(&par->vgastate, 0, sizeof(par->vgastate)); 976 par->vgastate.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | 977 VGA_SAVE_CMAP; 978 save_vga(&par->vgastate); 979 } 980} 981 982static void restore_vga_x86(struct nvidia_par *par) 983{ 984 struct resource *res= &par->pci_dev->resource[PCI_ROM_RESOURCE]; 985 986 if (res && res->flags & IORESOURCE_ROM_SHADOW) 987 restore_vga(&par->vgastate); 988} 989#else 990#define save_vga_x86(x) do {} while (0) 991#define restore_vga_x86(x) do {} while (0) 992#endif /* X86 */ 993 994static int nvidiafb_open(struct fb_info *info, int user) 995{ 996 struct nvidia_par *par = info->par; 997 998 if (!par->open_count) { 999 save_vga_x86(par); 1000 nvidia_save_vga(par, &par->initial_state); 1001 } 1002 1003 par->open_count++; 1004 return 0; 1005} 1006 1007static int nvidiafb_release(struct fb_info *info, int user) 1008{ 1009 struct nvidia_par *par = info->par; 1010 int err = 0; 1011 1012 if (!par->open_count) { 1013 err = -EINVAL; 1014 goto done; 1015 } 1016 1017 if (par->open_count == 1) { 1018 nvidia_write_regs(par, &par->initial_state); 1019 restore_vga_x86(par); 1020 } 1021 1022 par->open_count--; 1023done: 1024 return err; 1025} 1026 1027static struct fb_ops nvidia_fb_ops = { 1028 .owner = THIS_MODULE, 1029 .fb_open = nvidiafb_open, 1030 .fb_release = nvidiafb_release, 1031 .fb_check_var = nvidiafb_check_var, 1032 .fb_set_par = nvidiafb_set_par, 1033 .fb_setcolreg = nvidiafb_setcolreg, 1034 .fb_pan_display = nvidiafb_pan_display, 1035 .fb_blank = nvidiafb_blank, 1036 .fb_fillrect = nvidiafb_fillrect, 1037 .fb_copyarea = nvidiafb_copyarea, 1038 .fb_imageblit = nvidiafb_imageblit, 1039 .fb_cursor = nvidiafb_cursor, 1040 .fb_sync = nvidiafb_sync, 1041}; 1042 1043static int nvidiafb_suspend_late(struct device *dev, pm_message_t mesg) 1044{ 1045 struct fb_info *info = dev_get_drvdata(dev); 1046 struct nvidia_par *par = info->par; 1047 1048 if (mesg.event == PM_EVENT_PRETHAW) 1049 mesg.event = PM_EVENT_FREEZE; 1050 console_lock(); 1051 par->pm_state = mesg.event; 1052 1053 if (mesg.event & PM_EVENT_SLEEP) { 1054 fb_set_suspend(info, 1); 1055 nvidiafb_blank(FB_BLANK_POWERDOWN, info); 1056 nvidia_write_regs(par, &par->SavedReg); 1057 } 1058 dev->power.power_state = mesg; 1059 1060 console_unlock(); 1061 return 0; 1062} 1063 1064static int __maybe_unused nvidiafb_suspend(struct device *dev) 1065{ 1066 return nvidiafb_suspend_late(dev, PMSG_SUSPEND); 1067} 1068 1069static int __maybe_unused nvidiafb_hibernate(struct device *dev) 1070{ 1071 return nvidiafb_suspend_late(dev, PMSG_HIBERNATE); 1072} 1073 1074static int __maybe_unused nvidiafb_freeze(struct device *dev) 1075{ 1076 return nvidiafb_suspend_late(dev, PMSG_FREEZE); 1077} 1078 1079static int __maybe_unused nvidiafb_resume(struct device *dev) 1080{ 1081 struct fb_info *info = dev_get_drvdata(dev); 1082 struct nvidia_par *par = info->par; 1083 1084 console_lock(); 1085 1086 par->pm_state = PM_EVENT_ON; 1087 nvidiafb_set_par(info); 1088 fb_set_suspend (info, 0); 1089 nvidiafb_blank(FB_BLANK_UNBLANK, info); 1090 1091 console_unlock(); 1092 return 0; 1093} 1094 1095static const struct dev_pm_ops nvidiafb_pm_ops = { 1096#ifdef CONFIG_PM_SLEEP 1097 .suspend = nvidiafb_suspend, 1098 .resume = nvidiafb_resume, 1099 .freeze = nvidiafb_freeze, 1100 .thaw = nvidiafb_resume, 1101 .poweroff = nvidiafb_hibernate, 1102 .restore = nvidiafb_resume, 1103#endif /* CONFIG_PM_SLEEP */ 1104}; 1105 1106static int nvidia_set_fbinfo(struct fb_info *info) 1107{ 1108 struct fb_monspecs *specs = &info->monspecs; 1109 struct fb_videomode modedb; 1110 struct nvidia_par *par = info->par; 1111 int lpitch; 1112 1113 NVTRACE_ENTER(); 1114 info->flags = 1115 FBINFO_HWACCEL_IMAGEBLIT 1116 | FBINFO_HWACCEL_FILLRECT 1117 | FBINFO_HWACCEL_COPYAREA 1118 | FBINFO_HWACCEL_YPAN; 1119 1120 fb_videomode_to_modelist(info->monspecs.modedb, 1121 info->monspecs.modedb_len, &info->modelist); 1122 fb_var_to_videomode(&modedb, &nvidiafb_default_var); 1123 1124 switch (bpp) { 1125 case 0 ... 8: 1126 bpp = 8; 1127 break; 1128 case 9 ... 16: 1129 bpp = 16; 1130 break; 1131 default: 1132 bpp = 32; 1133 break; 1134 } 1135 1136 if (specs->modedb != NULL) { 1137 const struct fb_videomode *mode; 1138 1139 mode = fb_find_best_display(specs, &info->modelist); 1140 fb_videomode_to_var(&nvidiafb_default_var, mode); 1141 nvidiafb_default_var.bits_per_pixel = bpp; 1142 } else if (par->fpWidth && par->fpHeight) { 1143 char buf[16]; 1144 1145 memset(buf, 0, 16); 1146 snprintf(buf, 15, "%dx%dMR", par->fpWidth, par->fpHeight); 1147 fb_find_mode(&nvidiafb_default_var, info, buf, specs->modedb, 1148 specs->modedb_len, &modedb, bpp); 1149 } 1150 1151 if (mode_option) 1152 fb_find_mode(&nvidiafb_default_var, info, mode_option, 1153 specs->modedb, specs->modedb_len, &modedb, bpp); 1154 1155 info->var = nvidiafb_default_var; 1156 info->fix.visual = (info->var.bits_per_pixel == 8) ? 1157 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR; 1158 info->pseudo_palette = par->pseudo_palette; 1159 fb_alloc_cmap(&info->cmap, 256, 0); 1160 fb_destroy_modedb(info->monspecs.modedb); 1161 info->monspecs.modedb = NULL; 1162 1163 /* maximize virtual vertical length */ 1164 lpitch = info->var.xres_virtual * 1165 ((info->var.bits_per_pixel + 7) >> 3); 1166 info->var.yres_virtual = info->screen_size / lpitch; 1167 1168 info->pixmap.scan_align = 4; 1169 info->pixmap.buf_align = 4; 1170 info->pixmap.access_align = 32; 1171 info->pixmap.size = 8 * 1024; 1172 info->pixmap.flags = FB_PIXMAP_SYSTEM; 1173 1174 if (!hwcur) 1175 nvidia_fb_ops.fb_cursor = NULL; 1176 1177 info->var.accel_flags = (!noaccel); 1178 1179 switch (par->Architecture) { 1180 case NV_ARCH_04: 1181 info->fix.accel = FB_ACCEL_NV4; 1182 break; 1183 case NV_ARCH_10: 1184 info->fix.accel = FB_ACCEL_NV_10; 1185 break; 1186 case NV_ARCH_20: 1187 info->fix.accel = FB_ACCEL_NV_20; 1188 break; 1189 case NV_ARCH_30: 1190 info->fix.accel = FB_ACCEL_NV_30; 1191 break; 1192 case NV_ARCH_40: 1193 info->fix.accel = FB_ACCEL_NV_40; 1194 break; 1195 } 1196 1197 NVTRACE_LEAVE(); 1198 1199 return nvidiafb_check_var(&info->var, info); 1200} 1201 1202static u32 nvidia_get_chipset(struct pci_dev *pci_dev, 1203 volatile u32 __iomem *REGS) 1204{ 1205 u32 id = (pci_dev->vendor << 16) | pci_dev->device; 1206 1207 printk(KERN_INFO PFX "Device ID: %x \n", id); 1208 1209 if ((id & 0xfff0) == 0x00f0 || 1210 (id & 0xfff0) == 0x02e0) { 1211 /* pci-e */ 1212 id = NV_RD32(REGS, 0x1800); 1213 1214 if ((id & 0x0000ffff) == 0x000010DE) 1215 id = 0x10DE0000 | (id >> 16); 1216 else if ((id & 0xffff0000) == 0xDE100000) /* wrong endian */ 1217 id = 0x10DE0000 | ((id << 8) & 0x0000ff00) | 1218 ((id >> 8) & 0x000000ff); 1219 printk(KERN_INFO PFX "Subsystem ID: %x \n", id); 1220 } 1221 1222 return id; 1223} 1224 1225static u32 nvidia_get_arch(u32 Chipset) 1226{ 1227 u32 arch = 0; 1228 1229 switch (Chipset & 0x0ff0) { 1230 case 0x0100: /* GeForce 256 */ 1231 case 0x0110: /* GeForce2 MX */ 1232 case 0x0150: /* GeForce2 */ 1233 case 0x0170: /* GeForce4 MX */ 1234 case 0x0180: /* GeForce4 MX (8x AGP) */ 1235 case 0x01A0: /* nForce */ 1236 case 0x01F0: /* nForce2 */ 1237 arch = NV_ARCH_10; 1238 break; 1239 case 0x0200: /* GeForce3 */ 1240 case 0x0250: /* GeForce4 Ti */ 1241 case 0x0280: /* GeForce4 Ti (8x AGP) */ 1242 arch = NV_ARCH_20; 1243 break; 1244 case 0x0300: /* GeForceFX 5800 */ 1245 case 0x0310: /* GeForceFX 5600 */ 1246 case 0x0320: /* GeForceFX 5200 */ 1247 case 0x0330: /* GeForceFX 5900 */ 1248 case 0x0340: /* GeForceFX 5700 */ 1249 arch = NV_ARCH_30; 1250 break; 1251 case 0x0040: /* GeForce 6800 */ 1252 case 0x00C0: /* GeForce 6800 */ 1253 case 0x0120: /* GeForce 6800 */ 1254 case 0x0140: /* GeForce 6600 */ 1255 case 0x0160: /* GeForce 6200 */ 1256 case 0x01D0: /* GeForce 7200, 7300, 7400 */ 1257 case 0x0090: /* GeForce 7800 */ 1258 case 0x0210: /* GeForce 6800 */ 1259 case 0x0220: /* GeForce 6200 */ 1260 case 0x0240: /* GeForce 6100 */ 1261 case 0x0290: /* GeForce 7900 */ 1262 case 0x0390: /* GeForce 7600 */ 1263 case 0x03D0: 1264 arch = NV_ARCH_40; 1265 break; 1266 case 0x0020: /* TNT, TNT2 */ 1267 arch = NV_ARCH_04; 1268 break; 1269 default: /* unknown architecture */ 1270 break; 1271 } 1272 1273 return arch; 1274} 1275 1276static int nvidiafb_probe(struct pci_dev *pd, const struct pci_device_id *ent) 1277{ 1278 struct nvidia_par *par; 1279 struct fb_info *info; 1280 unsigned short cmd; 1281 int ret; 1282 volatile u32 __iomem *REGS; 1283 int Chipset; 1284 u32 Architecture; 1285 1286 NVTRACE_ENTER(); 1287 assert(pd != NULL); 1288 1289 if (pci_enable_device(pd)) { 1290 printk(KERN_ERR PFX "cannot enable PCI device\n"); 1291 return -ENODEV; 1292 } 1293 1294 /* enable IO and mem if not already done */ 1295 pci_read_config_word(pd, PCI_COMMAND, &cmd); 1296 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY); 1297 pci_write_config_word(pd, PCI_COMMAND, cmd); 1298 1299 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0); 1300 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0); 1301 1302 REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len); 1303 if (!REGS) { 1304 printk(KERN_ERR PFX "cannot ioremap MMIO base\n"); 1305 return -ENODEV; 1306 } 1307 1308 Chipset = nvidia_get_chipset(pd, REGS); 1309 Architecture = nvidia_get_arch(Chipset); 1310 if (Architecture == 0) { 1311 printk(KERN_ERR PFX "unknown NV_ARCH\n"); 1312 goto err_out; 1313 } 1314 1315 ret = aperture_remove_conflicting_pci_devices(pd, "nvidiafb"); 1316 if (ret) 1317 goto err_out; 1318 1319 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev); 1320 if (!info) 1321 goto err_out; 1322 1323 par = info->par; 1324 par->pci_dev = pd; 1325 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL); 1326 1327 if (info->pixmap.addr == NULL) 1328 goto err_out_kfree; 1329 1330 if (pci_request_regions(pd, "nvidiafb")) { 1331 printk(KERN_ERR PFX "cannot request PCI regions\n"); 1332 goto err_out_enable; 1333 } 1334 1335 par->FlatPanel = flatpanel; 1336 if (flatpanel == 1) 1337 printk(KERN_INFO PFX "flatpanel support enabled\n"); 1338 par->FPDither = fpdither; 1339 1340 par->CRTCnumber = forceCRTC; 1341 par->FpScale = (!noscale); 1342 par->paneltweak = paneltweak; 1343 par->reverse_i2c = reverse_i2c; 1344 1345 nvidiafb_fix.smem_start = pci_resource_start(pd, 1); 1346 1347 par->REGS = REGS; 1348 1349 par->Chipset = Chipset; 1350 par->Architecture = Architecture; 1351 1352 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4); 1353 1354 if (NVCommonSetup(info)) 1355 goto err_out_free_base0; 1356 1357 par->FbAddress = nvidiafb_fix.smem_start; 1358 par->FbMapSize = par->RamAmountKBytes * 1024; 1359 if (vram && vram * 1024 * 1024 < par->FbMapSize) 1360 par->FbMapSize = vram * 1024 * 1024; 1361 1362 /* Limit amount of vram to 64 MB */ 1363 if (par->FbMapSize > 64 * 1024 * 1024) 1364 par->FbMapSize = 64 * 1024 * 1024; 1365 1366 if(par->Architecture >= NV_ARCH_40) 1367 par->FbUsableSize = par->FbMapSize - (560 * 1024); 1368 else 1369 par->FbUsableSize = par->FbMapSize - (128 * 1024); 1370 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 : 1371 16 * 1024; 1372 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize; 1373 par->CursorStart = par->FbUsableSize + (32 * 1024); 1374 1375 info->screen_base = ioremap_wc(nvidiafb_fix.smem_start, 1376 par->FbMapSize); 1377 info->screen_size = par->FbUsableSize; 1378 nvidiafb_fix.smem_len = par->RamAmountKBytes * 1024; 1379 1380 if (!info->screen_base) { 1381 printk(KERN_ERR PFX "cannot ioremap FB base\n"); 1382 goto err_out_free_base1; 1383 } 1384 1385 par->FbStart = info->screen_base; 1386 1387 if (!nomtrr) 1388 par->wc_cookie = arch_phys_wc_add(nvidiafb_fix.smem_start, 1389 par->RamAmountKBytes * 1024); 1390 1391 info->fbops = &nvidia_fb_ops; 1392 info->fix = nvidiafb_fix; 1393 1394 if (nvidia_set_fbinfo(info) < 0) { 1395 printk(KERN_ERR PFX "error setting initial video mode\n"); 1396 goto err_out_iounmap_fb; 1397 } 1398 1399 nvidia_save_vga(par, &par->SavedReg); 1400 1401 pci_set_drvdata(pd, info); 1402 1403 if (register_framebuffer(info) < 0) { 1404 printk(KERN_ERR PFX "error registering nVidia framebuffer\n"); 1405 goto err_out_iounmap_fb; 1406 } 1407 1408 if (backlight) 1409 nvidia_bl_init(par); 1410 1411 printk(KERN_INFO PFX 1412 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n", 1413 info->fix.id, 1414 par->FbMapSize / (1024 * 1024), info->fix.smem_start); 1415 1416 NVTRACE_LEAVE(); 1417 return 0; 1418 1419err_out_iounmap_fb: 1420 iounmap(info->screen_base); 1421err_out_free_base1: 1422 fb_destroy_modedb(info->monspecs.modedb); 1423 nvidia_delete_i2c_busses(par); 1424err_out_free_base0: 1425 pci_release_regions(pd); 1426err_out_enable: 1427 kfree(info->pixmap.addr); 1428err_out_kfree: 1429 framebuffer_release(info); 1430err_out: 1431 iounmap(REGS); 1432 return -ENODEV; 1433} 1434 1435static void nvidiafb_remove(struct pci_dev *pd) 1436{ 1437 struct fb_info *info = pci_get_drvdata(pd); 1438 struct nvidia_par *par = info->par; 1439 1440 NVTRACE_ENTER(); 1441 1442 nvidia_bl_exit(par); 1443 unregister_framebuffer(info); 1444 1445 arch_phys_wc_del(par->wc_cookie); 1446 iounmap(info->screen_base); 1447 fb_destroy_modedb(info->monspecs.modedb); 1448 nvidia_delete_i2c_busses(par); 1449 iounmap(par->REGS); 1450 pci_release_regions(pd); 1451 kfree(info->pixmap.addr); 1452 framebuffer_release(info); 1453 NVTRACE_LEAVE(); 1454} 1455 1456/* ------------------------------------------------------------------------- * 1457 * 1458 * initialization 1459 * 1460 * ------------------------------------------------------------------------- */ 1461 1462#ifndef MODULE 1463static int nvidiafb_setup(char *options) 1464{ 1465 char *this_opt; 1466 1467 NVTRACE_ENTER(); 1468 if (!options || !*options) 1469 return 0; 1470 1471 while ((this_opt = strsep(&options, ",")) != NULL) { 1472 if (!strncmp(this_opt, "forceCRTC", 9)) { 1473 char *p; 1474 1475 p = this_opt + 9; 1476 if (!*p || !*(++p)) 1477 continue; 1478 forceCRTC = *p - '0'; 1479 if (forceCRTC < 0 || forceCRTC > 1) 1480 forceCRTC = -1; 1481 } else if (!strncmp(this_opt, "flatpanel", 9)) { 1482 flatpanel = 1; 1483 } else if (!strncmp(this_opt, "hwcur", 5)) { 1484 hwcur = 1; 1485 } else if (!strncmp(this_opt, "noaccel", 6)) { 1486 noaccel = 1; 1487 } else if (!strncmp(this_opt, "noscale", 7)) { 1488 noscale = 1; 1489 } else if (!strncmp(this_opt, "reverse_i2c", 11)) { 1490 reverse_i2c = 1; 1491 } else if (!strncmp(this_opt, "paneltweak:", 11)) { 1492 paneltweak = simple_strtoul(this_opt+11, NULL, 0); 1493 } else if (!strncmp(this_opt, "vram:", 5)) { 1494 vram = simple_strtoul(this_opt+5, NULL, 0); 1495 } else if (!strncmp(this_opt, "backlight:", 10)) { 1496 backlight = simple_strtoul(this_opt+10, NULL, 0); 1497 } else if (!strncmp(this_opt, "nomtrr", 6)) { 1498 nomtrr = true; 1499 } else if (!strncmp(this_opt, "fpdither:", 9)) { 1500 fpdither = simple_strtol(this_opt+9, NULL, 0); 1501 } else if (!strncmp(this_opt, "bpp:", 4)) { 1502 bpp = simple_strtoul(this_opt+4, NULL, 0); 1503 } else 1504 mode_option = this_opt; 1505 } 1506 NVTRACE_LEAVE(); 1507 return 0; 1508} 1509#endif /* !MODULE */ 1510 1511static struct pci_driver nvidiafb_driver = { 1512 .name = "nvidiafb", 1513 .id_table = nvidiafb_pci_tbl, 1514 .probe = nvidiafb_probe, 1515 .driver.pm = &nvidiafb_pm_ops, 1516 .remove = nvidiafb_remove, 1517}; 1518 1519/* ------------------------------------------------------------------------- * 1520 * 1521 * modularization 1522 * 1523 * ------------------------------------------------------------------------- */ 1524 1525static int nvidiafb_init(void) 1526{ 1527#ifndef MODULE 1528 char *option = NULL; 1529#endif 1530 1531 if (fb_modesetting_disabled("nvidiafb")) 1532 return -ENODEV; 1533 1534#ifndef MODULE 1535 if (fb_get_options("nvidiafb", &option)) 1536 return -ENODEV; 1537 nvidiafb_setup(option); 1538#endif 1539 return pci_register_driver(&nvidiafb_driver); 1540} 1541 1542module_init(nvidiafb_init); 1543 1544static void __exit nvidiafb_exit(void) 1545{ 1546 pci_unregister_driver(&nvidiafb_driver); 1547} 1548 1549module_exit(nvidiafb_exit); 1550 1551module_param(flatpanel, int, 0); 1552MODULE_PARM_DESC(flatpanel, 1553 "Enables experimental flat panel support for some chipsets. " 1554 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)"); 1555module_param(fpdither, int, 0); 1556MODULE_PARM_DESC(fpdither, 1557 "Enables dithering of flat panel for 6 bits panels. " 1558 "(0=disabled, 1=enabled, -1=autodetect) (default=-1)"); 1559module_param(hwcur, int, 0); 1560MODULE_PARM_DESC(hwcur, 1561 "Enables hardware cursor implementation. (0 or 1=enabled) " 1562 "(default=0)"); 1563module_param(noaccel, int, 0); 1564MODULE_PARM_DESC(noaccel, 1565 "Disables hardware acceleration. (0 or 1=disable) " 1566 "(default=0)"); 1567module_param(noscale, int, 0); 1568MODULE_PARM_DESC(noscale, 1569 "Disables screen scaling. (0 or 1=disable) " 1570 "(default=0, do scaling)"); 1571module_param(paneltweak, int, 0); 1572MODULE_PARM_DESC(paneltweak, 1573 "Tweak display settings for flatpanels. " 1574 "(default=0, no tweaks)"); 1575module_param(forceCRTC, int, 0); 1576MODULE_PARM_DESC(forceCRTC, 1577 "Forces usage of a particular CRTC in case autodetection " 1578 "fails. (0 or 1) (default=autodetect)"); 1579module_param(vram, int, 0); 1580MODULE_PARM_DESC(vram, 1581 "amount of framebuffer memory to remap in MiB" 1582 "(default=0 - remap entire memory)"); 1583module_param(mode_option, charp, 0); 1584MODULE_PARM_DESC(mode_option, "Specify initial video mode"); 1585module_param(bpp, int, 0); 1586MODULE_PARM_DESC(bpp, "pixel width in bits" 1587 "(default=8)"); 1588module_param(reverse_i2c, int, 0); 1589MODULE_PARM_DESC(reverse_i2c, "reverse port assignment of the i2c bus"); 1590module_param(nomtrr, bool, false); 1591MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) " 1592 "(default=0)"); 1593 1594MODULE_AUTHOR("Antonino Daplas"); 1595MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset"); 1596MODULE_LICENSE("GPL"); 1597