1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef __RADEONFB_H__ 3#define __RADEONFB_H__ 4 5#ifdef CONFIG_FB_RADEON_DEBUG 6#define DEBUG 1 7#endif 8 9#include <linux/module.h> 10#include <linux/kernel.h> 11#include <linux/sched.h> 12#include <linux/delay.h> 13#include <linux/pci.h> 14#include <linux/fb.h> 15 16 17#ifdef CONFIG_FB_RADEON_I2C 18#include <linux/i2c.h> 19#include <linux/i2c-algo-bit.h> 20#endif 21 22#include <asm/io.h> 23 24#ifdef CONFIG_SPARC 25#include <asm/prom.h> 26#endif 27 28#include <video/radeon.h> 29 30/*************************************************************** 31 * Most of the definitions here are adapted right from XFree86 * 32 ***************************************************************/ 33 34 35/* 36 * Chip families. Must fit in the low 16 bits of a long word 37 */ 38enum radeon_family { 39 CHIP_FAMILY_UNKNOW, 40 CHIP_FAMILY_LEGACY, 41 CHIP_FAMILY_RADEON, 42 CHIP_FAMILY_RV100, 43 CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ 44 CHIP_FAMILY_RV200, 45 CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), 46 RS250 (IGP 7000) */ 47 CHIP_FAMILY_R200, 48 CHIP_FAMILY_RV250, 49 CHIP_FAMILY_RS300, /* Radeon 9000 IGP */ 50 CHIP_FAMILY_RV280, 51 CHIP_FAMILY_R300, 52 CHIP_FAMILY_R350, 53 CHIP_FAMILY_RV350, 54 CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ 55 CHIP_FAMILY_R420, /* R420/R423/M18 */ 56 CHIP_FAMILY_RC410, 57 CHIP_FAMILY_RS400, 58 CHIP_FAMILY_RS480, 59 CHIP_FAMILY_LAST, 60}; 61 62#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \ 63 ((rinfo)->family == CHIP_FAMILY_RV200) || \ 64 ((rinfo)->family == CHIP_FAMILY_RS100) || \ 65 ((rinfo)->family == CHIP_FAMILY_RS200) || \ 66 ((rinfo)->family == CHIP_FAMILY_RV250) || \ 67 ((rinfo)->family == CHIP_FAMILY_RV280) || \ 68 ((rinfo)->family == CHIP_FAMILY_RS300)) 69 70 71#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \ 72 ((rinfo)->family == CHIP_FAMILY_RV350) || \ 73 ((rinfo)->family == CHIP_FAMILY_R350) || \ 74 ((rinfo)->family == CHIP_FAMILY_RV380) || \ 75 ((rinfo)->family == CHIP_FAMILY_R420) || \ 76 ((rinfo)->family == CHIP_FAMILY_RC410) || \ 77 ((rinfo)->family == CHIP_FAMILY_RS480)) 78 79/* 80 * Chip flags 81 */ 82enum radeon_chip_flags { 83 CHIP_FAMILY_MASK = 0x0000ffffUL, 84 CHIP_FLAGS_MASK = 0xffff0000UL, 85 CHIP_IS_MOBILITY = 0x00010000UL, 86 CHIP_IS_IGP = 0x00020000UL, 87 CHIP_HAS_CRTC2 = 0x00040000UL, 88}; 89 90/* 91 * Errata workarounds 92 */ 93enum radeon_errata { 94 CHIP_ERRATA_R300_CG = 0x00000001, 95 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, 96 CHIP_ERRATA_PLL_DELAY = 0x00000004, 97}; 98 99 100/* 101 * Monitor types 102 */ 103enum radeon_montype { 104 MT_NONE = 0, 105 MT_CRT, /* CRT */ 106 MT_LCD, /* LCD */ 107 MT_DFP, /* DVI */ 108 MT_CTV, /* composite TV */ 109 MT_STV /* S-Video out */ 110}; 111 112/* 113 * DDC i2c ports 114 */ 115enum ddc_type { 116 ddc_none, 117 ddc_monid, 118 ddc_dvi, 119 ddc_vga, 120 ddc_crt2, 121}; 122 123/* 124 * Connector types 125 */ 126enum conn_type { 127 conn_none, 128 conn_proprietary, 129 conn_crt, 130 conn_DVI_I, 131 conn_DVI_D, 132}; 133 134 135/* 136 * PLL infos 137 */ 138struct pll_info { 139 int ppll_max; 140 int ppll_min; 141 int sclk, mclk; 142 int ref_div; 143 int ref_clk; 144}; 145 146 147/* 148 * This structure contains the various registers manipulated by this 149 * driver for setting or restoring a mode. It's mostly copied from 150 * XFree's RADEONSaveRec structure. A few chip settings might still be 151 * tweaked without beeing reflected or saved in these registers though 152 */ 153struct radeon_regs { 154 /* Common registers */ 155 u32 ovr_clr; 156 u32 ovr_wid_left_right; 157 u32 ovr_wid_top_bottom; 158 u32 ov0_scale_cntl; 159 u32 mpp_tb_config; 160 u32 mpp_gp_config; 161 u32 subpic_cntl; 162 u32 viph_control; 163 u32 i2c_cntl_1; 164 u32 gen_int_cntl; 165 u32 cap0_trig_cntl; 166 u32 cap1_trig_cntl; 167 u32 bus_cntl; 168 u32 surface_cntl; 169 u32 bios_5_scratch; 170 171 /* Other registers to save for VT switches or driver load/unload */ 172 u32 dp_datatype; 173 u32 rbbm_soft_reset; 174 u32 clock_cntl_index; 175 u32 amcgpio_en_reg; 176 u32 amcgpio_mask; 177 178 /* Surface/tiling registers */ 179 u32 surf_lower_bound[8]; 180 u32 surf_upper_bound[8]; 181 u32 surf_info[8]; 182 183 /* CRTC registers */ 184 u32 crtc_gen_cntl; 185 u32 crtc_ext_cntl; 186 u32 dac_cntl; 187 u32 crtc_h_total_disp; 188 u32 crtc_h_sync_strt_wid; 189 u32 crtc_v_total_disp; 190 u32 crtc_v_sync_strt_wid; 191 u32 crtc_offset; 192 u32 crtc_offset_cntl; 193 u32 crtc_pitch; 194 u32 disp_merge_cntl; 195 u32 grph_buffer_cntl; 196 u32 crtc_more_cntl; 197 198 /* CRTC2 registers */ 199 u32 crtc2_gen_cntl; 200 u32 dac2_cntl; 201 u32 disp_output_cntl; 202 u32 disp_hw_debug; 203 u32 disp2_merge_cntl; 204 u32 grph2_buffer_cntl; 205 u32 crtc2_h_total_disp; 206 u32 crtc2_h_sync_strt_wid; 207 u32 crtc2_v_total_disp; 208 u32 crtc2_v_sync_strt_wid; 209 u32 crtc2_offset; 210 u32 crtc2_offset_cntl; 211 u32 crtc2_pitch; 212 213 /* Flat panel regs */ 214 u32 fp_crtc_h_total_disp; 215 u32 fp_crtc_v_total_disp; 216 u32 fp_gen_cntl; 217 u32 fp2_gen_cntl; 218 u32 fp_h_sync_strt_wid; 219 u32 fp2_h_sync_strt_wid; 220 u32 fp_horz_stretch; 221 u32 fp_panel_cntl; 222 u32 fp_v_sync_strt_wid; 223 u32 fp2_v_sync_strt_wid; 224 u32 fp_vert_stretch; 225 u32 lvds_gen_cntl; 226 u32 lvds_pll_cntl; 227 u32 tmds_crc; 228 u32 tmds_transmitter_cntl; 229 230 /* Computed values for PLL */ 231 u32 dot_clock_freq; 232 int feedback_div; 233 int post_div; 234 235 /* PLL registers */ 236 u32 ppll_div_3; 237 u32 ppll_ref_div; 238 u32 vclk_ecp_cntl; 239 u32 clk_cntl_index; 240 241 /* Computed values for PLL2 */ 242 u32 dot_clock_freq_2; 243 int feedback_div_2; 244 int post_div_2; 245 246 /* PLL2 registers */ 247 u32 p2pll_ref_div; 248 u32 p2pll_div_0; 249 u32 htotal_cntl2; 250 251 /* Palette */ 252 int palette_valid; 253}; 254 255struct panel_info { 256 int xres, yres; 257 int valid; 258 int clock; 259 int hOver_plus, hSync_width, hblank; 260 int vOver_plus, vSync_width, vblank; 261 int hAct_high, vAct_high, interlaced; 262 int pwr_delay; 263 int use_bios_dividers; 264 int ref_divider; 265 int post_divider; 266 int fbk_divider; 267}; 268 269struct radeonfb_info; 270 271#ifdef CONFIG_FB_RADEON_I2C 272struct radeon_i2c_chan { 273 struct radeonfb_info *rinfo; 274 u32 ddc_reg; 275 struct i2c_adapter adapter; 276 struct i2c_algo_bit_data algo; 277}; 278#endif 279 280enum radeon_pm_mode { 281 radeon_pm_none = 0, /* Nothing supported */ 282 radeon_pm_d2 = 0x00000001, /* Can do D2 state */ 283 radeon_pm_off = 0x00000002, /* Can resume from D3 cold */ 284}; 285 286typedef void (*reinit_function_ptr)(struct radeonfb_info *rinfo); 287 288struct radeonfb_info { 289 struct fb_info *info; 290 291 struct radeon_regs state; 292 struct radeon_regs init_state; 293 294 char name[50]; 295 296 unsigned long mmio_base_phys; 297 unsigned long fb_base_phys; 298 299 void __iomem *mmio_base; 300 void __iomem *fb_base; 301 302 unsigned long fb_local_base; 303 304 struct pci_dev *pdev; 305#if defined(CONFIG_PPC) || defined(CONFIG_SPARC) 306 struct device_node *of_node; 307#endif 308 309 void __iomem *bios_seg; 310 int fp_bios_start; 311 312 u32 pseudo_palette[16]; 313 struct { u8 red, green, blue, pad; } 314 palette[256]; 315 316 int chipset; 317 u8 family; 318 u8 rev; 319 unsigned int errata; 320 unsigned long video_ram; 321 unsigned long mapped_vram; 322 int vram_width; 323 int vram_ddr; 324 325 int pitch, bpp, depth; 326 327 int has_CRTC2; 328 int is_mobility; 329 int is_IGP; 330 int reversed_DAC; 331 int reversed_TMDS; 332 struct panel_info panel_info; 333 int mon1_type; 334 u8 *mon1_EDID; 335 struct fb_videomode *mon1_modedb; 336 int mon1_dbsize; 337 int mon2_type; 338 u8 *mon2_EDID; 339 340 u32 dp_gui_master_cntl; 341 342 struct pll_info pll; 343 344 int wc_cookie; 345 346 u32 save_regs[100]; 347 int asleep; 348 int lock_blank; 349 int dynclk; 350 int no_schedule; 351 enum radeon_pm_mode pm_mode; 352 reinit_function_ptr reinit_func; 353 354 /* Lock on register access */ 355 spinlock_t reg_lock; 356 357 /* Timer used for delayed LVDS operations */ 358 struct timer_list lvds_timer; 359 u32 pending_lvds_gen_cntl; 360 361#ifdef CONFIG_FB_RADEON_I2C 362 struct radeon_i2c_chan i2c[4]; 363#endif 364}; 365 366 367#define PRIMARY_MONITOR(rinfo) (rinfo->mon1_type) 368 369 370/* 371 * IO macros 372 */ 373 374void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms); 375 376#define INREG8(addr) readb((rinfo->mmio_base)+addr) 377#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) 378#define INREG16(addr) readw((rinfo->mmio_base)+addr) 379#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr) 380#define INREG(addr) readl((rinfo->mmio_base)+addr) 381#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) 382 383void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, u32 val, u32 mask); 384 385#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask) 386 387/* 388 * Note about PLL register accesses: 389 * 390 * I have removed the spinlock on them on purpose. The driver now 391 * expects that it will only manipulate the PLL registers in normal 392 * task environment, where radeon_msleep() will be called, protected 393 * by a semaphore (currently the console semaphore) so that no conflict 394 * will happen on the PLL register index. 395 * 396 * With the latest changes to the VT layer, this is guaranteed for all 397 * calls except the actual drawing/blits which aren't supposed to use 398 * the PLL registers anyway 399 * 400 * This is very important for the workarounds to work properly. The only 401 * possible exception to this rule is the call to unblank(), which may 402 * be done at irq time if an oops is in progress. 403 */ 404void radeon_pll_errata_after_index_slow(struct radeonfb_info *rinfo); 405static inline void radeon_pll_errata_after_index(struct radeonfb_info *rinfo) 406{ 407 if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS) 408 radeon_pll_errata_after_index_slow(rinfo); 409} 410 411void radeon_pll_errata_after_data_slow(struct radeonfb_info *rinfo); 412static inline void radeon_pll_errata_after_data(struct radeonfb_info *rinfo) 413{ 414 if (rinfo->errata & (CHIP_ERRATA_PLL_DELAY|CHIP_ERRATA_R300_CG)) 415 radeon_pll_errata_after_data_slow(rinfo); 416} 417 418u32 __INPLL(struct radeonfb_info *rinfo, u32 addr); 419void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, u32 val); 420void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index, 421 u32 val, u32 mask); 422 423#define INPLL(addr) __INPLL(rinfo, addr) 424#define OUTPLL(index, val) __OUTPLL(rinfo, index, val) 425#define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask) 426 427 428#define BIOS_IN8(v) (readb(rinfo->bios_seg + (v))) 429#define BIOS_IN16(v) (readb(rinfo->bios_seg + (v)) | \ 430 (readb(rinfo->bios_seg + (v) + 1) << 8)) 431#define BIOS_IN32(v) (readb(rinfo->bios_seg + (v)) | \ 432 (readb(rinfo->bios_seg + (v) + 1) << 8) | \ 433 (readb(rinfo->bios_seg + (v) + 2) << 16) | \ 434 (readb(rinfo->bios_seg + (v) + 3) << 24)) 435 436/* 437 * Inline utilities 438 */ 439static inline int round_div(int num, int den) 440{ 441 return (num + (den / 2)) / den; 442} 443 444static inline int var_to_depth(const struct fb_var_screeninfo *var) 445{ 446 if (var->bits_per_pixel != 16) 447 return var->bits_per_pixel; 448 return (var->green.length == 5) ? 15 : 16; 449} 450 451static inline u32 radeon_get_dstbpp(u16 depth) 452{ 453 switch (depth) { 454 case 8: 455 return DST_8BPP; 456 case 15: 457 return DST_15BPP; 458 case 16: 459 return DST_16BPP; 460 case 32: 461 return DST_32BPP; 462 default: 463 return 0; 464 } 465} 466 467/* 468 * 2D Engine helper routines 469 */ 470 471void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries); 472void radeon_engine_flush(struct radeonfb_info *rinfo); 473void _radeon_engine_idle(struct radeonfb_info *rinfo); 474 475#define radeon_engine_idle() _radeon_engine_idle(rinfo) 476#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries) 477#define radeon_msleep(ms) _radeon_msleep(rinfo,ms) 478 479 480/* I2C Functions */ 481extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo); 482extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo); 483extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid); 484 485/* PM Functions */ 486extern const struct dev_pm_ops radeonfb_pci_pm_ops; 487extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep); 488extern void radeonfb_pm_exit(struct radeonfb_info *rinfo); 489 490/* Monitor probe functions */ 491extern void radeon_probe_screens(struct radeonfb_info *rinfo, 492 const char *monitor_layout, int ignore_edid); 493extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option); 494extern int radeon_match_mode(struct radeonfb_info *rinfo, 495 struct fb_var_screeninfo *dest, 496 const struct fb_var_screeninfo *src); 497 498/* Accel functions */ 499extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region); 500extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area); 501extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image); 502extern int radeonfb_sync(struct fb_info *info); 503extern void radeonfb_engine_init (struct radeonfb_info *rinfo); 504extern void radeonfb_engine_reset(struct radeonfb_info *rinfo); 505 506/* Other functions */ 507extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch); 508extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode, 509 int reg_only); 510 511/* Backlight functions */ 512#ifdef CONFIG_FB_RADEON_BACKLIGHT 513extern void radeonfb_bl_init(struct radeonfb_info *rinfo); 514extern void radeonfb_bl_exit(struct radeonfb_info *rinfo); 515#else 516static inline void radeonfb_bl_init(struct radeonfb_info *rinfo) {} 517static inline void radeonfb_bl_exit(struct radeonfb_info *rinfo) {} 518#endif 519 520#endif /* __RADEONFB_H__ */ 521