162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0+ */
262306a36Sopenharmony_ci/*****************************************************************************
362306a36Sopenharmony_ci *
462306a36Sopenharmony_ci *	Copyright (C) 1997-2002 Inside Out Networks, Inc.
562306a36Sopenharmony_ci *
662306a36Sopenharmony_ci *	Feb-16-2001	DMI	Added I2C structure definitions
762306a36Sopenharmony_ci *	May-29-2002	gkh	Ported to Linux
862306a36Sopenharmony_ci *
962306a36Sopenharmony_ci *
1062306a36Sopenharmony_ci ******************************************************************************/
1162306a36Sopenharmony_ci
1262306a36Sopenharmony_ci#ifndef _IO_TI_H_
1362306a36Sopenharmony_ci#define _IO_TI_H_
1462306a36Sopenharmony_ci
1562306a36Sopenharmony_ci/* Address Space */
1662306a36Sopenharmony_ci#define DTK_ADDR_SPACE_XDATA		0x03	/* Addr is placed in XDATA space */
1762306a36Sopenharmony_ci#define DTK_ADDR_SPACE_I2C_TYPE_II	0x82	/* Addr is placed in I2C area */
1862306a36Sopenharmony_ci#define DTK_ADDR_SPACE_I2C_TYPE_III	0x83	/* Addr is placed in I2C area */
1962306a36Sopenharmony_ci
2062306a36Sopenharmony_ci/* UART Defines */
2162306a36Sopenharmony_ci#define UMPMEM_BASE_UART1		0xFFA0	/* UMP UART1 base address */
2262306a36Sopenharmony_ci#define UMPMEM_BASE_UART2		0xFFB0	/* UMP UART2 base address */
2362306a36Sopenharmony_ci#define UMPMEM_OFFS_UART_LSR		0x05	/* UMP UART LSR register offset */
2462306a36Sopenharmony_ci
2562306a36Sopenharmony_ci/* Bits per character */
2662306a36Sopenharmony_ci#define UMP_UART_CHAR5BITS		0x00
2762306a36Sopenharmony_ci#define UMP_UART_CHAR6BITS		0x01
2862306a36Sopenharmony_ci#define UMP_UART_CHAR7BITS		0x02
2962306a36Sopenharmony_ci#define UMP_UART_CHAR8BITS		0x03
3062306a36Sopenharmony_ci
3162306a36Sopenharmony_ci/* Parity */
3262306a36Sopenharmony_ci#define UMP_UART_NOPARITY		0x00
3362306a36Sopenharmony_ci#define UMP_UART_ODDPARITY		0x01
3462306a36Sopenharmony_ci#define UMP_UART_EVENPARITY		0x02
3562306a36Sopenharmony_ci#define UMP_UART_MARKPARITY		0x03
3662306a36Sopenharmony_ci#define UMP_UART_SPACEPARITY		0x04
3762306a36Sopenharmony_ci
3862306a36Sopenharmony_ci/* Stop bits */
3962306a36Sopenharmony_ci#define UMP_UART_STOPBIT1		0x00
4062306a36Sopenharmony_ci#define UMP_UART_STOPBIT15		0x01
4162306a36Sopenharmony_ci#define UMP_UART_STOPBIT2		0x02
4262306a36Sopenharmony_ci
4362306a36Sopenharmony_ci/* Line status register masks */
4462306a36Sopenharmony_ci#define UMP_UART_LSR_OV_MASK		0x01
4562306a36Sopenharmony_ci#define UMP_UART_LSR_PE_MASK		0x02
4662306a36Sopenharmony_ci#define UMP_UART_LSR_FE_MASK		0x04
4762306a36Sopenharmony_ci#define UMP_UART_LSR_BR_MASK		0x08
4862306a36Sopenharmony_ci#define UMP_UART_LSR_ER_MASK		0x0F
4962306a36Sopenharmony_ci#define UMP_UART_LSR_RX_MASK		0x10
5062306a36Sopenharmony_ci#define UMP_UART_LSR_TX_MASK		0x20
5162306a36Sopenharmony_ci
5262306a36Sopenharmony_ci#define UMP_UART_LSR_DATA_MASK		(LSR_PAR_ERR | LSR_FRM_ERR | LSR_BREAK)
5362306a36Sopenharmony_ci
5462306a36Sopenharmony_ci/* Port Settings Constants) */
5562306a36Sopenharmony_ci#define UMP_MASK_UART_FLAGS_RTS_FLOW		0x0001
5662306a36Sopenharmony_ci#define UMP_MASK_UART_FLAGS_RTS_DISABLE		0x0002
5762306a36Sopenharmony_ci#define UMP_MASK_UART_FLAGS_PARITY		0x0008
5862306a36Sopenharmony_ci#define UMP_MASK_UART_FLAGS_OUT_X_DSR_FLOW	0x0010
5962306a36Sopenharmony_ci#define UMP_MASK_UART_FLAGS_OUT_X_CTS_FLOW	0x0020
6062306a36Sopenharmony_ci#define UMP_MASK_UART_FLAGS_OUT_X		0x0040
6162306a36Sopenharmony_ci#define UMP_MASK_UART_FLAGS_OUT_XA		0x0080
6262306a36Sopenharmony_ci#define UMP_MASK_UART_FLAGS_IN_X		0x0100
6362306a36Sopenharmony_ci#define UMP_MASK_UART_FLAGS_DTR_FLOW		0x0800
6462306a36Sopenharmony_ci#define UMP_MASK_UART_FLAGS_DTR_DISABLE		0x1000
6562306a36Sopenharmony_ci#define UMP_MASK_UART_FLAGS_RECEIVE_MS_INT	0x2000
6662306a36Sopenharmony_ci#define UMP_MASK_UART_FLAGS_AUTO_START_ON_ERR	0x4000
6762306a36Sopenharmony_ci
6862306a36Sopenharmony_ci#define UMP_DMA_MODE_CONTINOUS			0x01
6962306a36Sopenharmony_ci#define UMP_PIPE_TRANS_TIMEOUT_ENA		0x80
7062306a36Sopenharmony_ci#define UMP_PIPE_TRANSFER_MODE_MASK		0x03
7162306a36Sopenharmony_ci#define UMP_PIPE_TRANS_TIMEOUT_MASK		0x7C
7262306a36Sopenharmony_ci
7362306a36Sopenharmony_ci/* Purge port Direction Mask Bits */
7462306a36Sopenharmony_ci#define UMP_PORT_DIR_OUT			0x01
7562306a36Sopenharmony_ci#define UMP_PORT_DIR_IN				0x02
7662306a36Sopenharmony_ci
7762306a36Sopenharmony_ci/* Address of Port 0 */
7862306a36Sopenharmony_ci#define UMPM_UART1_PORT				0x03
7962306a36Sopenharmony_ci
8062306a36Sopenharmony_ci/* Commands */
8162306a36Sopenharmony_ci#define	UMPC_SET_CONFIG			0x05
8262306a36Sopenharmony_ci#define	UMPC_OPEN_PORT			0x06
8362306a36Sopenharmony_ci#define	UMPC_CLOSE_PORT			0x07
8462306a36Sopenharmony_ci#define	UMPC_START_PORT			0x08
8562306a36Sopenharmony_ci#define	UMPC_STOP_PORT			0x09
8662306a36Sopenharmony_ci#define	UMPC_TEST_PORT			0x0A
8762306a36Sopenharmony_ci#define	UMPC_PURGE_PORT			0x0B
8862306a36Sopenharmony_ci
8962306a36Sopenharmony_ci/* Force the Firmware to complete the current Read */
9062306a36Sopenharmony_ci#define	UMPC_COMPLETE_READ		0x80
9162306a36Sopenharmony_ci/* Force UMP back into BOOT Mode */
9262306a36Sopenharmony_ci#define	UMPC_HARDWARE_RESET		0x81
9362306a36Sopenharmony_ci/*
9462306a36Sopenharmony_ci * Copy current download image to type 0xf2 record in 16k I2C
9562306a36Sopenharmony_ci * firmware will change 0xff record to type 2 record when complete
9662306a36Sopenharmony_ci */
9762306a36Sopenharmony_ci#define	UMPC_COPY_DNLD_TO_I2C		0x82
9862306a36Sopenharmony_ci
9962306a36Sopenharmony_ci/*
10062306a36Sopenharmony_ci * Special function register commands
10162306a36Sopenharmony_ci * wIndex is register address
10262306a36Sopenharmony_ci * wValue is MSB/LSB mask/data
10362306a36Sopenharmony_ci */
10462306a36Sopenharmony_ci#define	UMPC_WRITE_SFR			0x83	/* Write SFR Register */
10562306a36Sopenharmony_ci
10662306a36Sopenharmony_ci/* wIndex is register address */
10762306a36Sopenharmony_ci#define	UMPC_READ_SFR			0x84	/* Read SRF Register */
10862306a36Sopenharmony_ci
10962306a36Sopenharmony_ci/* Set or Clear DTR (wValue bit 0 Set/Clear)	wIndex ModuleID (port) */
11062306a36Sopenharmony_ci#define	UMPC_SET_CLR_DTR		0x85
11162306a36Sopenharmony_ci
11262306a36Sopenharmony_ci/* Set or Clear RTS (wValue bit 0 Set/Clear)	wIndex ModuleID (port) */
11362306a36Sopenharmony_ci#define	UMPC_SET_CLR_RTS		0x86
11462306a36Sopenharmony_ci
11562306a36Sopenharmony_ci/* Set or Clear LOOPBACK (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
11662306a36Sopenharmony_ci#define	UMPC_SET_CLR_LOOPBACK		0x87
11762306a36Sopenharmony_ci
11862306a36Sopenharmony_ci/* Set or Clear BREAK (wValue bit 0 Set/Clear)	wIndex ModuleID (port) */
11962306a36Sopenharmony_ci#define	UMPC_SET_CLR_BREAK		0x88
12062306a36Sopenharmony_ci
12162306a36Sopenharmony_ci/* Read MSR wIndex ModuleID (port) */
12262306a36Sopenharmony_ci#define	UMPC_READ_MSR			0x89
12362306a36Sopenharmony_ci
12462306a36Sopenharmony_ci/* Toolkit commands */
12562306a36Sopenharmony_ci/* Read-write group */
12662306a36Sopenharmony_ci#define	UMPC_MEMORY_READ		0x92
12762306a36Sopenharmony_ci#define	UMPC_MEMORY_WRITE		0x93
12862306a36Sopenharmony_ci
12962306a36Sopenharmony_ci/*
13062306a36Sopenharmony_ci *	UMP DMA Definitions
13162306a36Sopenharmony_ci */
13262306a36Sopenharmony_ci#define UMPD_OEDB1_ADDRESS		0xFF08
13362306a36Sopenharmony_ci#define UMPD_OEDB2_ADDRESS		0xFF10
13462306a36Sopenharmony_ci
13562306a36Sopenharmony_cistruct out_endpoint_desc_block {
13662306a36Sopenharmony_ci	u8 Configuration;
13762306a36Sopenharmony_ci	u8 XBufAddr;
13862306a36Sopenharmony_ci	u8 XByteCount;
13962306a36Sopenharmony_ci	u8 Unused1;
14062306a36Sopenharmony_ci	u8 Unused2;
14162306a36Sopenharmony_ci	u8 YBufAddr;
14262306a36Sopenharmony_ci	u8 YByteCount;
14362306a36Sopenharmony_ci	u8 BufferSize;
14462306a36Sopenharmony_ci};
14562306a36Sopenharmony_ci
14662306a36Sopenharmony_ci
14762306a36Sopenharmony_ci/*
14862306a36Sopenharmony_ci * TYPE DEFINITIONS
14962306a36Sopenharmony_ci * Structures for Firmware commands
15062306a36Sopenharmony_ci */
15162306a36Sopenharmony_ci/* UART settings */
15262306a36Sopenharmony_cistruct ump_uart_config {
15362306a36Sopenharmony_ci	u16 wBaudRate;		/* Baud rate                        */
15462306a36Sopenharmony_ci	u16 wFlags;		/* Bitmap mask of flags             */
15562306a36Sopenharmony_ci	u8 bDataBits;		/* 5..8 - data bits per character   */
15662306a36Sopenharmony_ci	u8 bParity;		/* Parity settings                  */
15762306a36Sopenharmony_ci	u8 bStopBits;		/* Stop bits settings               */
15862306a36Sopenharmony_ci	char cXon;		/* XON character                    */
15962306a36Sopenharmony_ci	char cXoff;		/* XOFF character                   */
16062306a36Sopenharmony_ci	u8 bUartMode;		/* Will be updated when a user      */
16162306a36Sopenharmony_ci				/* interface is defined             */
16262306a36Sopenharmony_ci};
16362306a36Sopenharmony_ci
16462306a36Sopenharmony_ci
16562306a36Sopenharmony_ci/*
16662306a36Sopenharmony_ci * TYPE DEFINITIONS
16762306a36Sopenharmony_ci * Structures for USB interrupts
16862306a36Sopenharmony_ci */
16962306a36Sopenharmony_ci/* Interrupt packet structure */
17062306a36Sopenharmony_cistruct ump_interrupt {
17162306a36Sopenharmony_ci	u8 bICode;			/* Interrupt code (interrupt num)   */
17262306a36Sopenharmony_ci	u8 bIInfo;			/* Interrupt information            */
17362306a36Sopenharmony_ci};
17462306a36Sopenharmony_ci
17562306a36Sopenharmony_ci
17662306a36Sopenharmony_ci#define TIUMP_GET_PORT_FROM_CODE(c)	(((c) >> 6) & 0x01)
17762306a36Sopenharmony_ci#define TIUMP_GET_FUNC_FROM_CODE(c)	((c) & 0x0f)
17862306a36Sopenharmony_ci#define TIUMP_INTERRUPT_CODE_LSR	0x03
17962306a36Sopenharmony_ci#define TIUMP_INTERRUPT_CODE_MSR	0x04
18062306a36Sopenharmony_ci
18162306a36Sopenharmony_ci#endif
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