162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0+ */
262306a36Sopenharmony_ci/************************************************************************
362306a36Sopenharmony_ci *
462306a36Sopenharmony_ci *	IONSP.H		Definitions for I/O Networks Serial Protocol
562306a36Sopenharmony_ci *
662306a36Sopenharmony_ci *	Copyright (C) 1997-1998 Inside Out Networks, Inc.
762306a36Sopenharmony_ci *
862306a36Sopenharmony_ci *	These definitions are used by both kernel-mode driver and the
962306a36Sopenharmony_ci *	peripheral firmware and MUST be kept in sync.
1062306a36Sopenharmony_ci *
1162306a36Sopenharmony_ci ************************************************************************/
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_ci/************************************************************************
1462306a36Sopenharmony_ci
1562306a36Sopenharmony_ciThe data to and from all ports on the peripheral is multiplexed
1662306a36Sopenharmony_cithrough a single endpoint pair (EP1 since it supports 64-byte
1762306a36Sopenharmony_ciMaxPacketSize). Therefore, the data, commands, and status for
1862306a36Sopenharmony_cieach port must be preceded by a short header identifying the
1962306a36Sopenharmony_cidestination port. The header also identifies the bytes that follow
2062306a36Sopenharmony_cias data or as command/status info.
2162306a36Sopenharmony_ci
2262306a36Sopenharmony_ciHeader format, first byte:
2362306a36Sopenharmony_ci
2462306a36Sopenharmony_ci    CLLLLPPP
2562306a36Sopenharmony_ci    --------
2662306a36Sopenharmony_ci    | |	 |------ Port Number:	0-7
2762306a36Sopenharmony_ci    | |--------- Length:	MSB bits of length
2862306a36Sopenharmony_ci    |----------- Data/Command:	0 = Data header
2962306a36Sopenharmony_ci				1 = Cmd / Status (Cmd if OUT, Status if IN)
3062306a36Sopenharmony_ci
3162306a36Sopenharmony_ciThis gives 2 possible formats:
3262306a36Sopenharmony_ci
3362306a36Sopenharmony_ci
3462306a36Sopenharmony_ci    Data header:		0LLLLPPP	LLLLLLLL
3562306a36Sopenharmony_ci    ============
3662306a36Sopenharmony_ci
3762306a36Sopenharmony_ci    Where (LLLL,LLLLLLL) is 12-bit length of data that follows for
3862306a36Sopenharmony_ci    port number (PPP). The length is 0-based (0-FFF means 0-4095
3962306a36Sopenharmony_ci    bytes). The ~4K limit allows the host driver (which deals in
4062306a36Sopenharmony_ci    transfer requests instead of individual packets) to write a
4162306a36Sopenharmony_ci    large chunk of data in a single request. Note, however, that
4262306a36Sopenharmony_ci    the length must always be <= the current TxCredits for a given
4362306a36Sopenharmony_ci    port due to buffering limitations on the peripheral.
4462306a36Sopenharmony_ci
4562306a36Sopenharmony_ci
4662306a36Sopenharmony_ci    Cmd/Status header:		1ccccPPP	[ CCCCCCCC,	 Params ]...
4762306a36Sopenharmony_ci    ==================
4862306a36Sopenharmony_ci
4962306a36Sopenharmony_ci    Where (cccc) or (cccc,CCCCCCCC) is the cmd or status identifier.
5062306a36Sopenharmony_ci    Frequently-used values are encoded as (cccc), longer ones using
5162306a36Sopenharmony_ci    (cccc,CCCCCCCC). Subsequent bytes are optional parameters and are
5262306a36Sopenharmony_ci    specific to the cmd or status code. This may include a length
5362306a36Sopenharmony_ci    for command and status codes that need variable-length parameters.
5462306a36Sopenharmony_ci
5562306a36Sopenharmony_ci
5662306a36Sopenharmony_ciIn addition, we use another interrupt pipe (endpoint) which the host polls
5762306a36Sopenharmony_ciperiodically for flow control information. The peripheral, when there has
5862306a36Sopenharmony_cibeen a change, sends the following 10-byte packet:
5962306a36Sopenharmony_ci
6062306a36Sopenharmony_ci	RRRRRRRRRRRRRRRR
6162306a36Sopenharmony_ci	T0T0T0T0T0T0T0T0
6262306a36Sopenharmony_ci	T1T1T1T1T1T1T1T1
6362306a36Sopenharmony_ci	T2T2T2T2T2T2T2T2
6462306a36Sopenharmony_ci	T3T3T3T3T3T3T3T3
6562306a36Sopenharmony_ci
6662306a36Sopenharmony_ciThe first field is the 16-bit RxBytesAvail field, which indicates the
6762306a36Sopenharmony_cinumber of bytes which may be read by the host from EP1. This is necessary:
6862306a36Sopenharmony_ci(a) because OSR2.1 has a bug which causes data loss if the peripheral returns
6962306a36Sopenharmony_cifewer bytes than the host expects to read, and (b) because, on Microsoft
7062306a36Sopenharmony_ciplatforms at least, an outstanding read posted on EP1 consumes about 35% of
7162306a36Sopenharmony_cithe CPU just polling the device for data.
7262306a36Sopenharmony_ci
7362306a36Sopenharmony_ciThe next 4 fields are the 16-bit TxCredits for each port, which indicate how
7462306a36Sopenharmony_cimany bytes the host is allowed to send on EP1 for transmit to a given port.
7562306a36Sopenharmony_ciAfter an OPEN_PORT command, the Edgeport sends the initial TxCredits for that
7662306a36Sopenharmony_ciport.
7762306a36Sopenharmony_ci
7862306a36Sopenharmony_ciAll 16-bit fields are sent in little-endian (Intel) format.
7962306a36Sopenharmony_ci
8062306a36Sopenharmony_ci************************************************************************/
8162306a36Sopenharmony_ci
8262306a36Sopenharmony_ci//
8362306a36Sopenharmony_ci// Define format of InterruptStatus packet returned from the
8462306a36Sopenharmony_ci// Interrupt pipe
8562306a36Sopenharmony_ci//
8662306a36Sopenharmony_ci
8762306a36Sopenharmony_cistruct int_status_pkt {
8862306a36Sopenharmony_ci	__u16 RxBytesAvail;			// Additional bytes available to
8962306a36Sopenharmony_ci						// be read from Bulk IN pipe
9062306a36Sopenharmony_ci	__u16 TxCredits[MAX_RS232_PORTS];	// Additional space available in
9162306a36Sopenharmony_ci						// given port's TxBuffer
9262306a36Sopenharmony_ci};
9362306a36Sopenharmony_ci
9462306a36Sopenharmony_ci
9562306a36Sopenharmony_ci#define GET_INT_STATUS_SIZE(NumPorts) (sizeof(__u16) + (sizeof(__u16) * (NumPorts)))
9662306a36Sopenharmony_ci
9762306a36Sopenharmony_ci
9862306a36Sopenharmony_ci
9962306a36Sopenharmony_ci//
10062306a36Sopenharmony_ci// Define cmd/status header values and macros to extract them.
10162306a36Sopenharmony_ci//
10262306a36Sopenharmony_ci//	Data:		0LLLLPPP LLLLLLLL
10362306a36Sopenharmony_ci//	Cmd/Stat:	1ccccPPP CCCCCCCC
10462306a36Sopenharmony_ci
10562306a36Sopenharmony_ci#define	IOSP_DATA_HDR_SIZE		2
10662306a36Sopenharmony_ci#define	IOSP_CMD_HDR_SIZE		2
10762306a36Sopenharmony_ci
10862306a36Sopenharmony_ci#define	IOSP_MAX_DATA_LENGTH		0x0FFF		// 12 bits -> 4K
10962306a36Sopenharmony_ci
11062306a36Sopenharmony_ci#define	IOSP_PORT_MASK			0x07		// Mask to isolate port number
11162306a36Sopenharmony_ci#define	IOSP_CMD_STAT_BIT		0x80		// If set, this is command/status header
11262306a36Sopenharmony_ci
11362306a36Sopenharmony_ci#define IS_CMD_STAT_HDR(Byte1)		((Byte1) & IOSP_CMD_STAT_BIT)
11462306a36Sopenharmony_ci#define IS_DATA_HDR(Byte1)		(!IS_CMD_STAT_HDR(Byte1))
11562306a36Sopenharmony_ci
11662306a36Sopenharmony_ci#define	IOSP_GET_HDR_PORT(Byte1)		((__u8) ((Byte1) & IOSP_PORT_MASK))
11762306a36Sopenharmony_ci#define	IOSP_GET_HDR_DATA_LEN(Byte1, Byte2)	((__u16) (((__u16)((Byte1) & 0x78)) << 5) | (Byte2))
11862306a36Sopenharmony_ci#define	IOSP_GET_STATUS_CODE(Byte1)		((__u8) (((Byte1) &  0x78) >> 3))
11962306a36Sopenharmony_ci
12062306a36Sopenharmony_ci
12162306a36Sopenharmony_ci//
12262306a36Sopenharmony_ci// These macros build the 1st and 2nd bytes for a data header
12362306a36Sopenharmony_ci//
12462306a36Sopenharmony_ci#define	IOSP_BUILD_DATA_HDR1(Port, Len)		((__u8) (((Port) | ((__u8) (((__u16) (Len)) >> 5) & 0x78))))
12562306a36Sopenharmony_ci#define	IOSP_BUILD_DATA_HDR2(Port, Len)		((__u8) (Len))
12662306a36Sopenharmony_ci
12762306a36Sopenharmony_ci
12862306a36Sopenharmony_ci//
12962306a36Sopenharmony_ci// These macros build the 1st and 2nd bytes for a command header
13062306a36Sopenharmony_ci//
13162306a36Sopenharmony_ci#define	IOSP_BUILD_CMD_HDR1(Port, Cmd)		((__u8) (IOSP_CMD_STAT_BIT | (Port) | ((__u8) ((Cmd) << 3))))
13262306a36Sopenharmony_ci
13362306a36Sopenharmony_ci
13462306a36Sopenharmony_ci//--------------------------------------------------------------
13562306a36Sopenharmony_ci//
13662306a36Sopenharmony_ci//	Define values for commands and command parameters
13762306a36Sopenharmony_ci//	(sent from Host to Edgeport)
13862306a36Sopenharmony_ci//
13962306a36Sopenharmony_ci//	1ccccPPP P1P1P1P1 [ P2P2P2P2P2 ]...
14062306a36Sopenharmony_ci//
14162306a36Sopenharmony_ci//	cccc:	00-07	2-byte commands. Write UART register 0-7 with
14262306a36Sopenharmony_ci//					value in P1. See 16650.H for definitions of
14362306a36Sopenharmony_ci//					UART register numbers and contents.
14462306a36Sopenharmony_ci//
14562306a36Sopenharmony_ci//		08-0B	3-byte commands:					==== P1 ====	==== P2 ====
14662306a36Sopenharmony_ci//					08	available for expansion
14762306a36Sopenharmony_ci//					09	1-param commands		Command Code	Param
14862306a36Sopenharmony_ci//					0A	available for expansion
14962306a36Sopenharmony_ci//					0B	available for expansion
15062306a36Sopenharmony_ci//
15162306a36Sopenharmony_ci//		0C-0D	4-byte commands.	P1 = extended cmd and P2,P3 = params
15262306a36Sopenharmony_ci//						Currently unimplemented.
15362306a36Sopenharmony_ci//
15462306a36Sopenharmony_ci//		0E-0F	N-byte commands:	P1 = num bytes after P1 (ie, TotalLen - 2)
15562306a36Sopenharmony_ci//						P2 = extended cmd, P3..Pn = parameters.
15662306a36Sopenharmony_ci//						Currently unimplemented.
15762306a36Sopenharmony_ci//
15862306a36Sopenharmony_ci
15962306a36Sopenharmony_ci#define	IOSP_WRITE_UART_REG(n)	((n) & 0x07)	// UartReg[ n ] := P1
16062306a36Sopenharmony_ci
16162306a36Sopenharmony_ci// Register numbers and contents
16262306a36Sopenharmony_ci// defined in 16554.H.
16362306a36Sopenharmony_ci
16462306a36Sopenharmony_ci//					0x08		// Available for expansion.
16562306a36Sopenharmony_ci#define	IOSP_EXT_CMD			0x09		// P1 = Command code (defined below)
16662306a36Sopenharmony_ci
16762306a36Sopenharmony_ci// P2 = Parameter
16862306a36Sopenharmony_ci
16962306a36Sopenharmony_ci//
17062306a36Sopenharmony_ci// Extended Command values, used with IOSP_EXT_CMD, may
17162306a36Sopenharmony_ci// or may not use parameter P2.
17262306a36Sopenharmony_ci//
17362306a36Sopenharmony_ci
17462306a36Sopenharmony_ci#define	IOSP_CMD_OPEN_PORT		0x00		// Enable ints, init UART. (NO PARAM)
17562306a36Sopenharmony_ci#define	IOSP_CMD_CLOSE_PORT		0x01		// Disable ints, flush buffers. (NO PARAM)
17662306a36Sopenharmony_ci#define	IOSP_CMD_CHASE_PORT		0x02		// Wait for Edgeport TX buffers to empty. (NO PARAM)
17762306a36Sopenharmony_ci#define IOSP_CMD_SET_RX_FLOW		0x03		// Set Rx Flow Control in Edgeport
17862306a36Sopenharmony_ci#define IOSP_CMD_SET_TX_FLOW		0x04		// Set Tx Flow Control in Edgeport
17962306a36Sopenharmony_ci#define IOSP_CMD_SET_XON_CHAR		0x05		// Set XON Character in Edgeport
18062306a36Sopenharmony_ci#define IOSP_CMD_SET_XOFF_CHAR		0x06		// Set XOFF Character in Edgeport
18162306a36Sopenharmony_ci#define IOSP_CMD_RX_CHECK_REQ		0x07		// Request Edgeport to insert a Checkpoint into
18262306a36Sopenharmony_ci
18362306a36Sopenharmony_ci// the receive data stream (Parameter = 1 byte sequence number)
18462306a36Sopenharmony_ci
18562306a36Sopenharmony_ci#define IOSP_CMD_SET_BREAK		0x08		// Turn on the BREAK (LCR bit 6)
18662306a36Sopenharmony_ci#define IOSP_CMD_CLEAR_BREAK		0x09		// Turn off the BREAK (LCR bit 6)
18762306a36Sopenharmony_ci
18862306a36Sopenharmony_ci
18962306a36Sopenharmony_ci//
19062306a36Sopenharmony_ci// Define macros to simplify building of IOSP cmds
19162306a36Sopenharmony_ci//
19262306a36Sopenharmony_ci
19362306a36Sopenharmony_ci#define MAKE_CMD_WRITE_REG(ppBuf, pLen, Port, Reg, Val)			\
19462306a36Sopenharmony_cido {									\
19562306a36Sopenharmony_ci	(*(ppBuf))[0] = IOSP_BUILD_CMD_HDR1((Port),			\
19662306a36Sopenharmony_ci					    IOSP_WRITE_UART_REG(Reg));	\
19762306a36Sopenharmony_ci	(*(ppBuf))[1] = (Val);						\
19862306a36Sopenharmony_ci									\
19962306a36Sopenharmony_ci	*ppBuf += 2;							\
20062306a36Sopenharmony_ci	*pLen  += 2;							\
20162306a36Sopenharmony_ci} while (0)
20262306a36Sopenharmony_ci
20362306a36Sopenharmony_ci#define MAKE_CMD_EXT_CMD(ppBuf, pLen, Port, ExtCmd, Param)		\
20462306a36Sopenharmony_cido {									\
20562306a36Sopenharmony_ci	(*(ppBuf))[0] = IOSP_BUILD_CMD_HDR1((Port), IOSP_EXT_CMD);	\
20662306a36Sopenharmony_ci	(*(ppBuf))[1] = (ExtCmd);					\
20762306a36Sopenharmony_ci	(*(ppBuf))[2] = (Param);					\
20862306a36Sopenharmony_ci									\
20962306a36Sopenharmony_ci	*ppBuf += 3;							\
21062306a36Sopenharmony_ci	*pLen  += 3;							\
21162306a36Sopenharmony_ci} while (0)
21262306a36Sopenharmony_ci
21362306a36Sopenharmony_ci
21462306a36Sopenharmony_ci
21562306a36Sopenharmony_ci//--------------------------------------------------------------
21662306a36Sopenharmony_ci//
21762306a36Sopenharmony_ci//	Define format of flow control commands
21862306a36Sopenharmony_ci//	(sent from Host to Edgeport)
21962306a36Sopenharmony_ci//
22062306a36Sopenharmony_ci//	11001PPP FlowCmd FlowTypes
22162306a36Sopenharmony_ci//
22262306a36Sopenharmony_ci//	Note that the 'FlowTypes' parameter is a bit mask; that is,
22362306a36Sopenharmony_ci//	more than one flow control type can be active at the same time.
22462306a36Sopenharmony_ci//	FlowTypes = 0 means 'no flow control'.
22562306a36Sopenharmony_ci//
22662306a36Sopenharmony_ci
22762306a36Sopenharmony_ci//
22862306a36Sopenharmony_ci//	IOSP_CMD_SET_RX_FLOW
22962306a36Sopenharmony_ci//
23062306a36Sopenharmony_ci//	Tells Edgeport how it can stop incoming UART data
23162306a36Sopenharmony_ci//
23262306a36Sopenharmony_ci//  Example for Port 0
23362306a36Sopenharmony_ci//	P0 = 11001000
23462306a36Sopenharmony_ci//  P1 = IOSP_CMD_SET_RX_FLOW
23562306a36Sopenharmony_ci//  P2 = Bit mask as follows:
23662306a36Sopenharmony_ci
23762306a36Sopenharmony_ci#define IOSP_RX_FLOW_RTS		0x01	// Edgeport drops RTS to stop incoming data
23862306a36Sopenharmony_ci#define IOSP_RX_FLOW_DTR		0x02	// Edgeport drops DTR to stop incoming data
23962306a36Sopenharmony_ci#define IOSP_RX_FLOW_DSR_SENSITIVITY	0x04	// Ignores Rx data unless DSR high
24062306a36Sopenharmony_ci
24162306a36Sopenharmony_ci// Not currently implemented by firmware.
24262306a36Sopenharmony_ci#define IOSP_RX_FLOW_XON_XOFF		0x08	// Edgeport sends XOFF char to stop incoming data.
24362306a36Sopenharmony_ci
24462306a36Sopenharmony_ci// Host must have previously programmed the
24562306a36Sopenharmony_ci// XON/XOFF values with SET_XON/SET_XOFF
24662306a36Sopenharmony_ci// before enabling this bit.
24762306a36Sopenharmony_ci
24862306a36Sopenharmony_ci//
24962306a36Sopenharmony_ci//	IOSP_CMD_SET_TX_FLOW
25062306a36Sopenharmony_ci//
25162306a36Sopenharmony_ci//	Tells Edgeport what signal(s) will stop it from transmitting UART data
25262306a36Sopenharmony_ci//
25362306a36Sopenharmony_ci//  Example for Port 0
25462306a36Sopenharmony_ci//	P0 = 11001000
25562306a36Sopenharmony_ci//  P1 = IOSP_CMD_SET_TX_FLOW
25662306a36Sopenharmony_ci//  P2 = Bit mask as follows:
25762306a36Sopenharmony_ci
25862306a36Sopenharmony_ci#define IOSP_TX_FLOW_CTS		0x01	// Edgeport stops Tx if CTS low
25962306a36Sopenharmony_ci#define IOSP_TX_FLOW_DSR		0x02	// Edgeport stops Tx if DSR low
26062306a36Sopenharmony_ci#define IOSP_TX_FLOW_DCD		0x04	// Edgeport stops Tx if DCD low
26162306a36Sopenharmony_ci#define IOSP_TX_FLOW_XON_XOFF		0x08	// Edgeport stops Tx upon receiving XOFF char.
26262306a36Sopenharmony_ci
26362306a36Sopenharmony_ci// Host must have previously programmed the
26462306a36Sopenharmony_ci// XON/XOFF values with SET_XON/SET_XOFF
26562306a36Sopenharmony_ci// before enabling this bit.
26662306a36Sopenharmony_ci#define IOSP_TX_FLOW_XOFF_CONTINUE	0x10	// If not set, Edgeport stops Tx when
26762306a36Sopenharmony_ci
26862306a36Sopenharmony_ci// sending XOFF in order to fix broken
26962306a36Sopenharmony_ci// systems that interpret the next
27062306a36Sopenharmony_ci// received char as XON.
27162306a36Sopenharmony_ci// If set, Edgeport continues Tx
27262306a36Sopenharmony_ci// normally after transmitting XOFF.
27362306a36Sopenharmony_ci// Not currently implemented by firmware.
27462306a36Sopenharmony_ci#define IOSP_TX_TOGGLE_RTS		0x20	// Edgeport drives RTS as a true half-duplex
27562306a36Sopenharmony_ci
27662306a36Sopenharmony_ci// Request-to-Send signal: it is raised before
27762306a36Sopenharmony_ci// beginning transmission and lowered after
27862306a36Sopenharmony_ci// the last Tx char leaves the UART.
27962306a36Sopenharmony_ci// Not currently implemented by firmware.
28062306a36Sopenharmony_ci
28162306a36Sopenharmony_ci//
28262306a36Sopenharmony_ci//	IOSP_CMD_SET_XON_CHAR
28362306a36Sopenharmony_ci//
28462306a36Sopenharmony_ci//	Sets the character which Edgeport transmits/interprets as XON.
28562306a36Sopenharmony_ci//	Note: This command MUST be sent before sending a SET_RX_FLOW or
28662306a36Sopenharmony_ci//	SET_TX_FLOW with the XON_XOFF bit set.
28762306a36Sopenharmony_ci//
28862306a36Sopenharmony_ci//  Example for Port 0
28962306a36Sopenharmony_ci//	P0 = 11001000
29062306a36Sopenharmony_ci//  P1 = IOSP_CMD_SET_XON_CHAR
29162306a36Sopenharmony_ci//  P2 = 0x11
29262306a36Sopenharmony_ci
29362306a36Sopenharmony_ci
29462306a36Sopenharmony_ci//
29562306a36Sopenharmony_ci//	IOSP_CMD_SET_XOFF_CHAR
29662306a36Sopenharmony_ci//
29762306a36Sopenharmony_ci//	Sets the character which Edgeport transmits/interprets as XOFF.
29862306a36Sopenharmony_ci//	Note: This command must be sent before sending a SET_RX_FLOW or
29962306a36Sopenharmony_ci//	SET_TX_FLOW with the XON_XOFF bit set.
30062306a36Sopenharmony_ci//
30162306a36Sopenharmony_ci//  Example for Port 0
30262306a36Sopenharmony_ci//	P0 = 11001000
30362306a36Sopenharmony_ci//  P1 = IOSP_CMD_SET_XOFF_CHAR
30462306a36Sopenharmony_ci//  P2 = 0x13
30562306a36Sopenharmony_ci
30662306a36Sopenharmony_ci
30762306a36Sopenharmony_ci//
30862306a36Sopenharmony_ci//	IOSP_CMD_RX_CHECK_REQ
30962306a36Sopenharmony_ci//
31062306a36Sopenharmony_ci//  This command is used to assist in the implementation of the
31162306a36Sopenharmony_ci//  IOCTL_SERIAL_PURGE Windows IOCTL.
31262306a36Sopenharmony_ci//  This IOSP command tries to place a marker at the end of the RX
31362306a36Sopenharmony_ci//  queue in the Edgeport. If the Edgeport RX queue is full then
31462306a36Sopenharmony_ci//  the Check will be discarded.
31562306a36Sopenharmony_ci//  It is up to the device driver to timeout waiting for the
31662306a36Sopenharmony_ci//  RX_CHECK_RSP.  If a RX_CHECK_RSP is received, the driver is
31762306a36Sopenharmony_ci//	sure that all data has been received from the edgeport and
31862306a36Sopenharmony_ci//	may now purge any internal RX buffers.
31962306a36Sopenharmony_ci//  Note tat the sequence numbers may be used to detect lost
32062306a36Sopenharmony_ci//  CHECK_REQs.
32162306a36Sopenharmony_ci
32262306a36Sopenharmony_ci//  Example for Port 0
32362306a36Sopenharmony_ci//	P0 = 11001000
32462306a36Sopenharmony_ci//  P1 = IOSP_CMD_RX_CHECK_REQ
32562306a36Sopenharmony_ci//  P2 = Sequence number
32662306a36Sopenharmony_ci
32762306a36Sopenharmony_ci
32862306a36Sopenharmony_ci//  Response will be:
32962306a36Sopenharmony_ci//  P1 = IOSP_EXT_RX_CHECK_RSP
33062306a36Sopenharmony_ci//  P2 = Request Sequence number
33162306a36Sopenharmony_ci
33262306a36Sopenharmony_ci
33362306a36Sopenharmony_ci
33462306a36Sopenharmony_ci//--------------------------------------------------------------
33562306a36Sopenharmony_ci//
33662306a36Sopenharmony_ci//	Define values for status and status parameters
33762306a36Sopenharmony_ci//	(received by Host from Edgeport)
33862306a36Sopenharmony_ci//
33962306a36Sopenharmony_ci//	1ssssPPP P1P1P1P1 [ P2P2P2P2P2 ]...
34062306a36Sopenharmony_ci//
34162306a36Sopenharmony_ci//	ssss:	00-07	2-byte status.	ssss identifies which UART register
34262306a36Sopenharmony_ci//					has changed value, and the new value is in P1.
34362306a36Sopenharmony_ci//					Note that the ssss values do not correspond to the
34462306a36Sopenharmony_ci//					16554 register numbers given in 16554.H. Instead,
34562306a36Sopenharmony_ci//					see below for definitions of the ssss numbers
34662306a36Sopenharmony_ci//					used in this status message.
34762306a36Sopenharmony_ci//
34862306a36Sopenharmony_ci//		08-0B	3-byte status:					==== P1 ====	==== P2 ====
34962306a36Sopenharmony_ci//					08	LSR_DATA:		New LSR		Errored byte
35062306a36Sopenharmony_ci//					09	1-param responses	Response Code	Param
35162306a36Sopenharmony_ci//					0A	OPEN_RSP:		InitialMsr	TxBufferSize
35262306a36Sopenharmony_ci//					0B	available for expansion
35362306a36Sopenharmony_ci//
35462306a36Sopenharmony_ci//		0C-0D	4-byte status.	P1 = extended status code and P2,P3 = params
35562306a36Sopenharmony_ci//					Not currently implemented.
35662306a36Sopenharmony_ci//
35762306a36Sopenharmony_ci//		0E-0F	N-byte status:	P1 = num bytes after P1 (ie, TotalLen - 2)
35862306a36Sopenharmony_ci//					P2 = extended status, P3..Pn = parameters.
35962306a36Sopenharmony_ci//					Not currently implemented.
36062306a36Sopenharmony_ci//
36162306a36Sopenharmony_ci
36262306a36Sopenharmony_ci/****************************************************
36362306a36Sopenharmony_ci *	SSSS values for 2-byte status messages (0-8)
36462306a36Sopenharmony_ci ****************************************************/
36562306a36Sopenharmony_ci
36662306a36Sopenharmony_ci#define	IOSP_STATUS_LSR			0x00	// P1 is new value of LSR register.
36762306a36Sopenharmony_ci
36862306a36Sopenharmony_ci// Bits defined in 16554.H. Edgeport
36962306a36Sopenharmony_ci// returns this in order to report
37062306a36Sopenharmony_ci// line status errors (overrun,
37162306a36Sopenharmony_ci// parity, framing, break). This form
37262306a36Sopenharmony_ci// is used when a errored receive data
37362306a36Sopenharmony_ci// character was NOT present in the
37462306a36Sopenharmony_ci// UART when the LSR error occurred
37562306a36Sopenharmony_ci// (ie, when LSR bit 0 = 0).
37662306a36Sopenharmony_ci
37762306a36Sopenharmony_ci#define	IOSP_STATUS_MSR			0x01	// P1 is new value of MSR register.
37862306a36Sopenharmony_ci
37962306a36Sopenharmony_ci// Bits defined in 16554.H. Edgeport
38062306a36Sopenharmony_ci// returns this in order to report
38162306a36Sopenharmony_ci// changes in modem status lines
38262306a36Sopenharmony_ci// (CTS, DSR, RI, CD)
38362306a36Sopenharmony_ci//
38462306a36Sopenharmony_ci
38562306a36Sopenharmony_ci//					0x02	// Available for future expansion
38662306a36Sopenharmony_ci//					0x03	//
38762306a36Sopenharmony_ci//					0x04	//
38862306a36Sopenharmony_ci//					0x05	//
38962306a36Sopenharmony_ci//					0x06	//
39062306a36Sopenharmony_ci//					0x07	//
39162306a36Sopenharmony_ci
39262306a36Sopenharmony_ci
39362306a36Sopenharmony_ci/****************************************************
39462306a36Sopenharmony_ci *	SSSS values for 3-byte status messages (8-A)
39562306a36Sopenharmony_ci ****************************************************/
39662306a36Sopenharmony_ci
39762306a36Sopenharmony_ci#define	IOSP_STATUS_LSR_DATA		0x08	// P1 is new value of LSR register (same as STATUS_LSR)
39862306a36Sopenharmony_ci
39962306a36Sopenharmony_ci// P2 is errored character read from
40062306a36Sopenharmony_ci//    RxFIFO after LSR reported an error.
40162306a36Sopenharmony_ci
40262306a36Sopenharmony_ci#define	IOSP_EXT_STATUS			0x09	// P1 is status/response code, param in P2.
40362306a36Sopenharmony_ci
40462306a36Sopenharmony_ci
40562306a36Sopenharmony_ci// Response Codes (P1 values) for 3-byte status messages
40662306a36Sopenharmony_ci
40762306a36Sopenharmony_ci#define	IOSP_EXT_STATUS_CHASE_RSP	0	// Reply to CHASE_PORT cmd. P2 is outcome:
40862306a36Sopenharmony_ci#define	IOSP_EXT_STATUS_CHASE_PASS	0	//	P2 = 0: All Tx data drained successfully
40962306a36Sopenharmony_ci#define	IOSP_EXT_STATUS_CHASE_FAIL	1	//	P2 = 1: Timed out (stuck due to flow
41062306a36Sopenharmony_ci
41162306a36Sopenharmony_ci//			control from remote device).
41262306a36Sopenharmony_ci
41362306a36Sopenharmony_ci#define	IOSP_EXT_STATUS_RX_CHECK_RSP	1	// Reply to RX_CHECK cmd. P2 is sequence number
41462306a36Sopenharmony_ci
41562306a36Sopenharmony_ci
41662306a36Sopenharmony_ci#define IOSP_STATUS_OPEN_RSP		0x0A	// Reply to OPEN_PORT cmd.
41762306a36Sopenharmony_ci
41862306a36Sopenharmony_ci// P1 is Initial MSR value
41962306a36Sopenharmony_ci// P2 is encoded TxBuffer Size:
42062306a36Sopenharmony_ci//	TxBufferSize = (P2 + 1) * 64
42162306a36Sopenharmony_ci
42262306a36Sopenharmony_ci//					0x0B	// Available for future expansion
42362306a36Sopenharmony_ci
42462306a36Sopenharmony_ci#define GET_TX_BUFFER_SIZE(P2) (((P2) + 1) * 64)
42562306a36Sopenharmony_ci
42662306a36Sopenharmony_ci
42762306a36Sopenharmony_ci
42862306a36Sopenharmony_ci
42962306a36Sopenharmony_ci/****************************************************
43062306a36Sopenharmony_ci *	SSSS values for 4-byte status messages
43162306a36Sopenharmony_ci ****************************************************/
43262306a36Sopenharmony_ci
43362306a36Sopenharmony_ci#define IOSP_EXT4_STATUS		0x0C	// Extended status code in P1,
43462306a36Sopenharmony_ci
43562306a36Sopenharmony_ci// Params in P2, P3
43662306a36Sopenharmony_ci// Currently unimplemented.
43762306a36Sopenharmony_ci
43862306a36Sopenharmony_ci//					0x0D	// Currently unused, available.
43962306a36Sopenharmony_ci
44062306a36Sopenharmony_ci
44162306a36Sopenharmony_ci
44262306a36Sopenharmony_ci//
44362306a36Sopenharmony_ci// Macros to parse status messages
44462306a36Sopenharmony_ci//
44562306a36Sopenharmony_ci
44662306a36Sopenharmony_ci#define	IOSP_GET_STATUS_LEN(code)	((code) < 8 ? 2 : ((code) < 0x0A ? 3 : 4))
44762306a36Sopenharmony_ci
44862306a36Sopenharmony_ci#define	IOSP_STATUS_IS_2BYTE(code)	((code) < 0x08)
44962306a36Sopenharmony_ci#define	IOSP_STATUS_IS_3BYTE(code)	(((code) >= 0x08) && ((code) <= 0x0B))
45062306a36Sopenharmony_ci#define	IOSP_STATUS_IS_4BYTE(code)	(((code) >= 0x0C) && ((code) <= 0x0D))
45162306a36Sopenharmony_ci
452