1// SPDX-License-Identifier: GPL-2.0
2/*
3 * xHCI host controller driver for R-Car SoCs
4 *
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 */
7
8#include <linux/firmware.h>
9#include <linux/iopoll.h>
10#include <linux/module.h>
11#include <linux/platform_device.h>
12#include <linux/of.h>
13#include <linux/usb/phy.h>
14
15#include "xhci.h"
16#include "xhci-plat.h"
17#include "xhci-rzv2m.h"
18
19#define XHCI_RCAR_FIRMWARE_NAME_V1	"r8a779x_usb3_v1.dlmem"
20#define XHCI_RCAR_FIRMWARE_NAME_V3	"r8a779x_usb3_v3.dlmem"
21
22/*
23* - The V3 firmware is for all R-Car Gen3
24* - The V2 firmware is possible to use on R-Car Gen2. However, the V2 causes
25*   performance degradation. So, this driver continues to use the V1 if R-Car
26*   Gen2.
27* - The V1 firmware is impossible to use on R-Car Gen3.
28*/
29MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V1);
30MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V3);
31
32/*** Register Offset ***/
33#define RCAR_USB3_AXH_STA	0x104	/* AXI Host Control Status */
34#define RCAR_USB3_INT_ENA	0x224	/* Interrupt Enable */
35#define RCAR_USB3_DL_CTRL	0x250	/* FW Download Control & Status */
36#define RCAR_USB3_FW_DATA0	0x258	/* FW Data0 */
37
38#define RCAR_USB3_LCLK		0xa44	/* LCLK Select */
39#define RCAR_USB3_CONF1		0xa48	/* USB3.0 Configuration1 */
40#define RCAR_USB3_CONF2		0xa5c	/* USB3.0 Configuration2 */
41#define RCAR_USB3_CONF3		0xaa8	/* USB3.0 Configuration3 */
42#define RCAR_USB3_RX_POL	0xab0	/* USB3.0 RX Polarity */
43#define RCAR_USB3_TX_POL	0xab8	/* USB3.0 TX Polarity */
44
45/*** Register Settings ***/
46/* AXI Host Control Status */
47#define RCAR_USB3_AXH_STA_B3_PLL_ACTIVE		0x00010000
48#define RCAR_USB3_AXH_STA_B2_PLL_ACTIVE		0x00000001
49#define RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK (RCAR_USB3_AXH_STA_B3_PLL_ACTIVE | \
50					   RCAR_USB3_AXH_STA_B2_PLL_ACTIVE)
51
52/* Interrupt Enable */
53#define RCAR_USB3_INT_XHC_ENA	0x00000001
54#define RCAR_USB3_INT_PME_ENA	0x00000002
55#define RCAR_USB3_INT_HSE_ENA	0x00000004
56#define RCAR_USB3_INT_ENA_VAL	(RCAR_USB3_INT_XHC_ENA | \
57				RCAR_USB3_INT_PME_ENA | RCAR_USB3_INT_HSE_ENA)
58
59/* FW Download Control & Status */
60#define RCAR_USB3_DL_CTRL_ENABLE	0x00000001
61#define RCAR_USB3_DL_CTRL_FW_SUCCESS	0x00000010
62#define RCAR_USB3_DL_CTRL_FW_SET_DATA0	0x00000100
63
64/* LCLK Select */
65#define RCAR_USB3_LCLK_ENA_VAL	0x01030001
66
67/* USB3.0 Configuration */
68#define RCAR_USB3_CONF1_VAL	0x00030204
69#define RCAR_USB3_CONF2_VAL	0x00030300
70#define RCAR_USB3_CONF3_VAL	0x13802007
71
72/* USB3.0 Polarity */
73#define RCAR_USB3_RX_POL_VAL	BIT(21)
74#define RCAR_USB3_TX_POL_VAL	BIT(4)
75
76static void xhci_rcar_start_gen2(struct usb_hcd *hcd)
77{
78	/* LCLK Select */
79	writel(RCAR_USB3_LCLK_ENA_VAL, hcd->regs + RCAR_USB3_LCLK);
80	/* USB3.0 Configuration */
81	writel(RCAR_USB3_CONF1_VAL, hcd->regs + RCAR_USB3_CONF1);
82	writel(RCAR_USB3_CONF2_VAL, hcd->regs + RCAR_USB3_CONF2);
83	writel(RCAR_USB3_CONF3_VAL, hcd->regs + RCAR_USB3_CONF3);
84	/* USB3.0 Polarity */
85	writel(RCAR_USB3_RX_POL_VAL, hcd->regs + RCAR_USB3_RX_POL);
86	writel(RCAR_USB3_TX_POL_VAL, hcd->regs + RCAR_USB3_TX_POL);
87}
88
89static int xhci_rcar_is_gen2(struct device *dev)
90{
91	struct device_node *node = dev->of_node;
92
93	return of_device_is_compatible(node, "renesas,xhci-r8a7790") ||
94		of_device_is_compatible(node, "renesas,xhci-r8a7791") ||
95		of_device_is_compatible(node, "renesas,xhci-r8a7793") ||
96		of_device_is_compatible(node, "renesas,rcar-gen2-xhci");
97}
98
99static void xhci_rcar_start(struct usb_hcd *hcd)
100{
101	u32 temp;
102
103	if (hcd->regs != NULL) {
104		/* Interrupt Enable */
105		temp = readl(hcd->regs + RCAR_USB3_INT_ENA);
106		temp |= RCAR_USB3_INT_ENA_VAL;
107		writel(temp, hcd->regs + RCAR_USB3_INT_ENA);
108		if (xhci_rcar_is_gen2(hcd->self.controller))
109			xhci_rcar_start_gen2(hcd);
110	}
111}
112
113static int xhci_rcar_download_firmware(struct usb_hcd *hcd)
114{
115	struct device *dev = hcd->self.controller;
116	void __iomem *regs = hcd->regs;
117	struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd);
118	const struct firmware *fw;
119	int retval, index, j;
120	u32 data, val, temp;
121
122	/*
123	 * According to the datasheet, "Upon the completion of FW Download,
124	 * there is no need to write or reload FW".
125	 */
126	if (readl(regs + RCAR_USB3_DL_CTRL) & RCAR_USB3_DL_CTRL_FW_SUCCESS)
127		return 0;
128
129	/* request R-Car USB3.0 firmware */
130	retval = request_firmware(&fw, priv->firmware_name, dev);
131	if (retval)
132		return retval;
133
134	/* download R-Car USB3.0 firmware */
135	temp = readl(regs + RCAR_USB3_DL_CTRL);
136	temp |= RCAR_USB3_DL_CTRL_ENABLE;
137	writel(temp, regs + RCAR_USB3_DL_CTRL);
138
139	for (index = 0; index < fw->size; index += 4) {
140		/* to avoid reading beyond the end of the buffer */
141		for (data = 0, j = 3; j >= 0; j--) {
142			if ((j + index) < fw->size)
143				data |= fw->data[index + j] << (8 * j);
144		}
145		writel(data, regs + RCAR_USB3_FW_DATA0);
146		temp = readl(regs + RCAR_USB3_DL_CTRL);
147		temp |= RCAR_USB3_DL_CTRL_FW_SET_DATA0;
148		writel(temp, regs + RCAR_USB3_DL_CTRL);
149
150		retval = readl_poll_timeout_atomic(regs + RCAR_USB3_DL_CTRL,
151				val, !(val & RCAR_USB3_DL_CTRL_FW_SET_DATA0),
152				1, 10000);
153		if (retval < 0)
154			break;
155	}
156
157	temp = readl(regs + RCAR_USB3_DL_CTRL);
158	temp &= ~RCAR_USB3_DL_CTRL_ENABLE;
159	writel(temp, regs + RCAR_USB3_DL_CTRL);
160
161	retval = readl_poll_timeout_atomic((regs + RCAR_USB3_DL_CTRL),
162			val, val & RCAR_USB3_DL_CTRL_FW_SUCCESS, 1, 10000);
163
164	release_firmware(fw);
165
166	return retval;
167}
168
169static bool xhci_rcar_wait_for_pll_active(struct usb_hcd *hcd)
170{
171	int retval;
172	u32 val, mask = RCAR_USB3_AXH_STA_PLL_ACTIVE_MASK;
173
174	retval = readl_poll_timeout_atomic(hcd->regs + RCAR_USB3_AXH_STA,
175			val, (val & mask) == mask, 1, 1000);
176	return !retval;
177}
178
179/* This function needs to initialize a "phy" of usb before */
180static int xhci_rcar_init_quirk(struct usb_hcd *hcd)
181{
182	/* If hcd->regs is NULL, we don't just call the following function */
183	if (!hcd->regs)
184		return 0;
185
186	if (!xhci_rcar_wait_for_pll_active(hcd))
187		return -ETIMEDOUT;
188
189	return xhci_rcar_download_firmware(hcd);
190}
191
192static int xhci_rcar_resume_quirk(struct usb_hcd *hcd)
193{
194	int ret;
195
196	ret = xhci_rcar_download_firmware(hcd);
197	if (!ret)
198		xhci_rcar_start(hcd);
199
200	return ret;
201}
202
203/*
204 * On R-Car Gen2 and Gen3, the AC64 bit (bit 0) of HCCPARAMS1 is set
205 * to 1. However, these SoCs don't support 64-bit address memory
206 * pointers. So, this driver clears the AC64 bit of xhci->hcc_params
207 * to call dma_set_coherent_mask(dev, DMA_BIT_MASK(32)) in
208 * xhci_gen_setup() by using the XHCI_NO_64BIT_SUPPORT quirk.
209 *
210 * And, since the firmware/internal CPU control the USBSTS.STS_HALT
211 * and the process speed is down when the roothub port enters U3,
212 * long delay for the handshake of STS_HALT is neeed in xhci_suspend()
213 * by using the XHCI_SLOW_SUSPEND quirk.
214 */
215#define SET_XHCI_PLAT_PRIV_FOR_RCAR(firmware)				\
216	.firmware_name = firmware,					\
217	.quirks = XHCI_NO_64BIT_SUPPORT | XHCI_TRUST_TX_LENGTH |	\
218		  XHCI_SLOW_SUSPEND,					\
219	.init_quirk = xhci_rcar_init_quirk,				\
220	.plat_start = xhci_rcar_start,					\
221	.resume_quirk = xhci_rcar_resume_quirk,
222
223static const struct xhci_plat_priv xhci_plat_renesas_rcar_gen2 = {
224	SET_XHCI_PLAT_PRIV_FOR_RCAR(XHCI_RCAR_FIRMWARE_NAME_V1)
225};
226
227static const struct xhci_plat_priv xhci_plat_renesas_rcar_gen3 = {
228	SET_XHCI_PLAT_PRIV_FOR_RCAR(XHCI_RCAR_FIRMWARE_NAME_V3)
229};
230
231static const struct xhci_plat_priv xhci_plat_renesas_rzv2m = {
232	.quirks = XHCI_NO_64BIT_SUPPORT | XHCI_TRUST_TX_LENGTH |
233		  XHCI_SLOW_SUSPEND,
234	.init_quirk = xhci_rzv2m_init_quirk,
235	.plat_start = xhci_rzv2m_start,
236};
237
238static const struct of_device_id usb_xhci_of_match[] = {
239	{
240		.compatible = "renesas,xhci-r8a7790",
241		.data = &xhci_plat_renesas_rcar_gen2,
242	}, {
243		.compatible = "renesas,xhci-r8a7791",
244		.data = &xhci_plat_renesas_rcar_gen2,
245	}, {
246		.compatible = "renesas,xhci-r8a7793",
247		.data = &xhci_plat_renesas_rcar_gen2,
248	}, {
249		.compatible = "renesas,xhci-r8a7795",
250		.data = &xhci_plat_renesas_rcar_gen3,
251	}, {
252		.compatible = "renesas,xhci-r8a7796",
253		.data = &xhci_plat_renesas_rcar_gen3,
254	}, {
255		.compatible = "renesas,rcar-gen2-xhci",
256		.data = &xhci_plat_renesas_rcar_gen2,
257	}, {
258		.compatible = "renesas,rcar-gen3-xhci",
259		.data = &xhci_plat_renesas_rcar_gen3,
260	}, {
261		.compatible = "renesas,rzv2m-xhci",
262		.data = &xhci_plat_renesas_rzv2m,
263	},
264	{ },
265};
266MODULE_DEVICE_TABLE(of, usb_xhci_of_match);
267
268static int xhci_renesas_probe(struct platform_device *pdev)
269{
270	const struct xhci_plat_priv *priv_match;
271
272	priv_match = of_device_get_match_data(&pdev->dev);
273
274	return xhci_plat_probe(pdev, NULL, priv_match);
275}
276
277static struct platform_driver usb_xhci_renesas_driver = {
278	.probe = xhci_renesas_probe,
279	.remove_new = xhci_plat_remove,
280	.shutdown = usb_hcd_platform_shutdown,
281	.driver = {
282		.name = "xhci-renesas-hcd",
283		.pm = &xhci_plat_pm_ops,
284		.of_match_table = usb_xhci_of_match,
285	},
286};
287module_platform_driver(usb_xhci_renesas_driver);
288
289MODULE_DESCRIPTION("xHCI Platform Host Controller Driver for Renesas R-Car and RZ");
290MODULE_LICENSE("GPL");
291