1// SPDX-License-Identifier: GPL-2.0 2/* 3 * This file contains code to reset and initialize USB host controllers. 4 * Some of it includes work-arounds for PCI hardware and BIOS quirks. 5 * It may need to run early during booting -- before USB would normally 6 * initialize -- to ensure that Linux doesn't use any legacy modes. 7 * 8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 9 * (and others) 10 */ 11 12#include <linux/types.h> 13#include <linux/kernel.h> 14#include <linux/pci.h> 15#include <linux/delay.h> 16#include <linux/export.h> 17#include <linux/acpi.h> 18#include <linux/dmi.h> 19#include <linux/of.h> 20#include <linux/iopoll.h> 21 22#include "pci-quirks.h" 23#include "xhci-ext-caps.h" 24 25 26#define UHCI_USBLEGSUP 0xc0 /* legacy support */ 27#define UHCI_USBCMD 0 /* command register */ 28#define UHCI_USBINTR 4 /* interrupt register */ 29#define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */ 30#define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */ 31#define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */ 32#define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */ 33#define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */ 34#define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */ 35#define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */ 36 37#define OHCI_CONTROL 0x04 38#define OHCI_CMDSTATUS 0x08 39#define OHCI_INTRSTATUS 0x0c 40#define OHCI_INTRENABLE 0x10 41#define OHCI_INTRDISABLE 0x14 42#define OHCI_FMINTERVAL 0x34 43#define OHCI_HCFS (3 << 6) /* hc functional state */ 44#define OHCI_HCR (1 << 0) /* host controller reset */ 45#define OHCI_OCR (1 << 3) /* ownership change request */ 46#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ 47#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ 48#define OHCI_INTR_OC (1 << 30) /* ownership change */ 49 50#define EHCI_HCC_PARAMS 0x08 /* extended capabilities */ 51#define EHCI_USBCMD 0 /* command register */ 52#define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */ 53#define EHCI_USBSTS 4 /* status register */ 54#define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */ 55#define EHCI_USBINTR 8 /* interrupt register */ 56#define EHCI_CONFIGFLAG 0x40 /* configured flag register */ 57#define EHCI_USBLEGSUP 0 /* legacy support register */ 58#define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */ 59#define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */ 60#define EHCI_USBLEGCTLSTS 4 /* legacy control/status */ 61#define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */ 62 63/* AMD quirk use */ 64#define AB_REG_BAR_LOW 0xe0 65#define AB_REG_BAR_HIGH 0xe1 66#define AB_REG_BAR_SB700 0xf0 67#define AB_INDX(addr) ((addr) + 0x00) 68#define AB_DATA(addr) ((addr) + 0x04) 69#define AX_INDXC 0x30 70#define AX_DATAC 0x34 71 72#define PT_ADDR_INDX 0xE8 73#define PT_READ_INDX 0xE4 74#define PT_SIG_1_ADDR 0xA520 75#define PT_SIG_2_ADDR 0xA521 76#define PT_SIG_3_ADDR 0xA522 77#define PT_SIG_4_ADDR 0xA523 78#define PT_SIG_1_DATA 0x78 79#define PT_SIG_2_DATA 0x56 80#define PT_SIG_3_DATA 0x34 81#define PT_SIG_4_DATA 0x12 82#define PT4_P1_REG 0xB521 83#define PT4_P2_REG 0xB522 84#define PT2_P1_REG 0xD520 85#define PT2_P2_REG 0xD521 86#define PT1_P1_REG 0xD522 87#define PT1_P2_REG 0xD523 88 89#define NB_PCIE_INDX_ADDR 0xe0 90#define NB_PCIE_INDX_DATA 0xe4 91#define PCIE_P_CNTL 0x10040 92#define BIF_NB 0x10002 93#define NB_PIF0_PWRDOWN_0 0x01100012 94#define NB_PIF0_PWRDOWN_1 0x01100013 95 96#define USB_INTEL_XUSB2PR 0xD0 97#define USB_INTEL_USB2PRM 0xD4 98#define USB_INTEL_USB3_PSSEN 0xD8 99#define USB_INTEL_USB3PRM 0xDC 100 101/* ASMEDIA quirk use */ 102#define ASMT_DATA_WRITE0_REG 0xF8 103#define ASMT_DATA_WRITE1_REG 0xFC 104#define ASMT_CONTROL_REG 0xE0 105#define ASMT_CONTROL_WRITE_BIT 0x02 106#define ASMT_WRITEREG_CMD 0x10423 107#define ASMT_FLOWCTL_ADDR 0xFA30 108#define ASMT_FLOWCTL_DATA 0xBA 109#define ASMT_PSEUDO_DATA 0 110 111/* 112 * amd_chipset_gen values represent AMD different chipset generations 113 */ 114enum amd_chipset_gen { 115 NOT_AMD_CHIPSET = 0, 116 AMD_CHIPSET_SB600, 117 AMD_CHIPSET_SB700, 118 AMD_CHIPSET_SB800, 119 AMD_CHIPSET_HUDSON2, 120 AMD_CHIPSET_BOLTON, 121 AMD_CHIPSET_YANGTZE, 122 AMD_CHIPSET_TAISHAN, 123 AMD_CHIPSET_UNKNOWN, 124}; 125 126struct amd_chipset_type { 127 enum amd_chipset_gen gen; 128 u8 rev; 129}; 130 131static struct amd_chipset_info { 132 struct pci_dev *nb_dev; 133 struct pci_dev *smbus_dev; 134 int nb_type; 135 struct amd_chipset_type sb_type; 136 int isoc_reqs; 137 int probe_count; 138 bool need_pll_quirk; 139} amd_chipset; 140 141static DEFINE_SPINLOCK(amd_lock); 142 143/* 144 * amd_chipset_sb_type_init - initialize amd chipset southbridge type 145 * 146 * AMD FCH/SB generation and revision is identified by SMBus controller 147 * vendor, device and revision IDs. 148 * 149 * Returns: 1 if it is an AMD chipset, 0 otherwise. 150 */ 151static int amd_chipset_sb_type_init(struct amd_chipset_info *pinfo) 152{ 153 u8 rev = 0; 154 pinfo->sb_type.gen = AMD_CHIPSET_UNKNOWN; 155 156 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI, 157 PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL); 158 if (pinfo->smbus_dev) { 159 rev = pinfo->smbus_dev->revision; 160 if (rev >= 0x10 && rev <= 0x1f) 161 pinfo->sb_type.gen = AMD_CHIPSET_SB600; 162 else if (rev >= 0x30 && rev <= 0x3f) 163 pinfo->sb_type.gen = AMD_CHIPSET_SB700; 164 else if (rev >= 0x40 && rev <= 0x4f) 165 pinfo->sb_type.gen = AMD_CHIPSET_SB800; 166 } else { 167 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 168 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 169 170 if (pinfo->smbus_dev) { 171 rev = pinfo->smbus_dev->revision; 172 if (rev >= 0x11 && rev <= 0x14) 173 pinfo->sb_type.gen = AMD_CHIPSET_HUDSON2; 174 else if (rev >= 0x15 && rev <= 0x18) 175 pinfo->sb_type.gen = AMD_CHIPSET_BOLTON; 176 else if (rev >= 0x39 && rev <= 0x3a) 177 pinfo->sb_type.gen = AMD_CHIPSET_YANGTZE; 178 } else { 179 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 180 0x145c, NULL); 181 if (pinfo->smbus_dev) { 182 rev = pinfo->smbus_dev->revision; 183 pinfo->sb_type.gen = AMD_CHIPSET_TAISHAN; 184 } else { 185 pinfo->sb_type.gen = NOT_AMD_CHIPSET; 186 return 0; 187 } 188 } 189 } 190 pinfo->sb_type.rev = rev; 191 return 1; 192} 193 194void sb800_prefetch(struct device *dev, int on) 195{ 196 u16 misc; 197 struct pci_dev *pdev = to_pci_dev(dev); 198 199 pci_read_config_word(pdev, 0x50, &misc); 200 if (on == 0) 201 pci_write_config_word(pdev, 0x50, misc & 0xfcff); 202 else 203 pci_write_config_word(pdev, 0x50, misc | 0x0300); 204} 205EXPORT_SYMBOL_GPL(sb800_prefetch); 206 207static void usb_amd_find_chipset_info(void) 208{ 209 unsigned long flags; 210 struct amd_chipset_info info = { }; 211 212 spin_lock_irqsave(&amd_lock, flags); 213 214 /* probe only once */ 215 if (amd_chipset.probe_count > 0) { 216 amd_chipset.probe_count++; 217 spin_unlock_irqrestore(&amd_lock, flags); 218 return; 219 } 220 spin_unlock_irqrestore(&amd_lock, flags); 221 222 if (!amd_chipset_sb_type_init(&info)) { 223 goto commit; 224 } 225 226 switch (info.sb_type.gen) { 227 case AMD_CHIPSET_SB700: 228 info.need_pll_quirk = info.sb_type.rev <= 0x3B; 229 break; 230 case AMD_CHIPSET_SB800: 231 case AMD_CHIPSET_HUDSON2: 232 case AMD_CHIPSET_BOLTON: 233 info.need_pll_quirk = true; 234 break; 235 default: 236 info.need_pll_quirk = false; 237 break; 238 } 239 240 if (!info.need_pll_quirk) { 241 if (info.smbus_dev) { 242 pci_dev_put(info.smbus_dev); 243 info.smbus_dev = NULL; 244 } 245 goto commit; 246 } 247 248 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL); 249 if (info.nb_dev) { 250 info.nb_type = 1; 251 } else { 252 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL); 253 if (info.nb_dev) { 254 info.nb_type = 2; 255 } else { 256 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 257 0x9600, NULL); 258 if (info.nb_dev) 259 info.nb_type = 3; 260 } 261 } 262 263 printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n"); 264 265commit: 266 267 spin_lock_irqsave(&amd_lock, flags); 268 if (amd_chipset.probe_count > 0) { 269 /* race - someone else was faster - drop devices */ 270 271 /* Mark that we where here */ 272 amd_chipset.probe_count++; 273 274 spin_unlock_irqrestore(&amd_lock, flags); 275 276 pci_dev_put(info.nb_dev); 277 pci_dev_put(info.smbus_dev); 278 279 } else { 280 /* no race - commit the result */ 281 info.probe_count++; 282 amd_chipset = info; 283 spin_unlock_irqrestore(&amd_lock, flags); 284 } 285} 286 287int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev) 288{ 289 /* Make sure amd chipset type has already been initialized */ 290 usb_amd_find_chipset_info(); 291 if (amd_chipset.sb_type.gen == AMD_CHIPSET_YANGTZE || 292 amd_chipset.sb_type.gen == AMD_CHIPSET_TAISHAN) { 293 dev_dbg(&pdev->dev, "QUIRK: Enable AMD remote wakeup fix\n"); 294 return 1; 295 } 296 return 0; 297} 298EXPORT_SYMBOL_GPL(usb_hcd_amd_remote_wakeup_quirk); 299 300bool usb_amd_hang_symptom_quirk(void) 301{ 302 u8 rev; 303 304 usb_amd_find_chipset_info(); 305 rev = amd_chipset.sb_type.rev; 306 /* SB600 and old version of SB700 have hang symptom bug */ 307 return amd_chipset.sb_type.gen == AMD_CHIPSET_SB600 || 308 (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 && 309 rev >= 0x3a && rev <= 0x3b); 310} 311EXPORT_SYMBOL_GPL(usb_amd_hang_symptom_quirk); 312 313bool usb_amd_prefetch_quirk(void) 314{ 315 usb_amd_find_chipset_info(); 316 /* SB800 needs pre-fetch fix */ 317 return amd_chipset.sb_type.gen == AMD_CHIPSET_SB800; 318} 319EXPORT_SYMBOL_GPL(usb_amd_prefetch_quirk); 320 321bool usb_amd_quirk_pll_check(void) 322{ 323 usb_amd_find_chipset_info(); 324 return amd_chipset.need_pll_quirk; 325} 326EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_check); 327 328/* 329 * The hardware normally enables the A-link power management feature, which 330 * lets the system lower the power consumption in idle states. 331 * 332 * This USB quirk prevents the link going into that lower power state 333 * during isochronous transfers. 334 * 335 * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of 336 * some AMD platforms may stutter or have breaks occasionally. 337 */ 338static void usb_amd_quirk_pll(int disable) 339{ 340 u32 addr, addr_low, addr_high, val; 341 u32 bit = disable ? 0 : 1; 342 unsigned long flags; 343 344 spin_lock_irqsave(&amd_lock, flags); 345 346 if (disable) { 347 amd_chipset.isoc_reqs++; 348 if (amd_chipset.isoc_reqs > 1) { 349 spin_unlock_irqrestore(&amd_lock, flags); 350 return; 351 } 352 } else { 353 amd_chipset.isoc_reqs--; 354 if (amd_chipset.isoc_reqs > 0) { 355 spin_unlock_irqrestore(&amd_lock, flags); 356 return; 357 } 358 } 359 360 if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB800 || 361 amd_chipset.sb_type.gen == AMD_CHIPSET_HUDSON2 || 362 amd_chipset.sb_type.gen == AMD_CHIPSET_BOLTON) { 363 outb_p(AB_REG_BAR_LOW, 0xcd6); 364 addr_low = inb_p(0xcd7); 365 outb_p(AB_REG_BAR_HIGH, 0xcd6); 366 addr_high = inb_p(0xcd7); 367 addr = addr_high << 8 | addr_low; 368 369 outl_p(0x30, AB_INDX(addr)); 370 outl_p(0x40, AB_DATA(addr)); 371 outl_p(0x34, AB_INDX(addr)); 372 val = inl_p(AB_DATA(addr)); 373 } else if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 && 374 amd_chipset.sb_type.rev <= 0x3b) { 375 pci_read_config_dword(amd_chipset.smbus_dev, 376 AB_REG_BAR_SB700, &addr); 377 outl(AX_INDXC, AB_INDX(addr)); 378 outl(0x40, AB_DATA(addr)); 379 outl(AX_DATAC, AB_INDX(addr)); 380 val = inl(AB_DATA(addr)); 381 } else { 382 spin_unlock_irqrestore(&amd_lock, flags); 383 return; 384 } 385 386 if (disable) { 387 val &= ~0x08; 388 val |= (1 << 4) | (1 << 9); 389 } else { 390 val |= 0x08; 391 val &= ~((1 << 4) | (1 << 9)); 392 } 393 outl_p(val, AB_DATA(addr)); 394 395 if (!amd_chipset.nb_dev) { 396 spin_unlock_irqrestore(&amd_lock, flags); 397 return; 398 } 399 400 if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) { 401 addr = PCIE_P_CNTL; 402 pci_write_config_dword(amd_chipset.nb_dev, 403 NB_PCIE_INDX_ADDR, addr); 404 pci_read_config_dword(amd_chipset.nb_dev, 405 NB_PCIE_INDX_DATA, &val); 406 407 val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12)); 408 val |= bit | (bit << 3) | (bit << 12); 409 val |= ((!bit) << 4) | ((!bit) << 9); 410 pci_write_config_dword(amd_chipset.nb_dev, 411 NB_PCIE_INDX_DATA, val); 412 413 addr = BIF_NB; 414 pci_write_config_dword(amd_chipset.nb_dev, 415 NB_PCIE_INDX_ADDR, addr); 416 pci_read_config_dword(amd_chipset.nb_dev, 417 NB_PCIE_INDX_DATA, &val); 418 val &= ~(1 << 8); 419 val |= bit << 8; 420 421 pci_write_config_dword(amd_chipset.nb_dev, 422 NB_PCIE_INDX_DATA, val); 423 } else if (amd_chipset.nb_type == 2) { 424 addr = NB_PIF0_PWRDOWN_0; 425 pci_write_config_dword(amd_chipset.nb_dev, 426 NB_PCIE_INDX_ADDR, addr); 427 pci_read_config_dword(amd_chipset.nb_dev, 428 NB_PCIE_INDX_DATA, &val); 429 if (disable) 430 val &= ~(0x3f << 7); 431 else 432 val |= 0x3f << 7; 433 434 pci_write_config_dword(amd_chipset.nb_dev, 435 NB_PCIE_INDX_DATA, val); 436 437 addr = NB_PIF0_PWRDOWN_1; 438 pci_write_config_dword(amd_chipset.nb_dev, 439 NB_PCIE_INDX_ADDR, addr); 440 pci_read_config_dword(amd_chipset.nb_dev, 441 NB_PCIE_INDX_DATA, &val); 442 if (disable) 443 val &= ~(0x3f << 7); 444 else 445 val |= 0x3f << 7; 446 447 pci_write_config_dword(amd_chipset.nb_dev, 448 NB_PCIE_INDX_DATA, val); 449 } 450 451 spin_unlock_irqrestore(&amd_lock, flags); 452 return; 453} 454 455void usb_amd_quirk_pll_disable(void) 456{ 457 usb_amd_quirk_pll(1); 458} 459EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable); 460 461static int usb_asmedia_wait_write(struct pci_dev *pdev) 462{ 463 unsigned long retry_count; 464 unsigned char value; 465 466 for (retry_count = 1000; retry_count > 0; --retry_count) { 467 468 pci_read_config_byte(pdev, ASMT_CONTROL_REG, &value); 469 470 if (value == 0xff) { 471 dev_err(&pdev->dev, "%s: check_ready ERROR", __func__); 472 return -EIO; 473 } 474 475 if ((value & ASMT_CONTROL_WRITE_BIT) == 0) 476 return 0; 477 478 udelay(50); 479 } 480 481 dev_warn(&pdev->dev, "%s: check_write_ready timeout", __func__); 482 return -ETIMEDOUT; 483} 484 485void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev) 486{ 487 if (usb_asmedia_wait_write(pdev) != 0) 488 return; 489 490 /* send command and address to device */ 491 pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_WRITEREG_CMD); 492 pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_FLOWCTL_ADDR); 493 pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT); 494 495 if (usb_asmedia_wait_write(pdev) != 0) 496 return; 497 498 /* send data to device */ 499 pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_FLOWCTL_DATA); 500 pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_PSEUDO_DATA); 501 pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT); 502} 503EXPORT_SYMBOL_GPL(usb_asmedia_modifyflowcontrol); 504 505void usb_amd_quirk_pll_enable(void) 506{ 507 usb_amd_quirk_pll(0); 508} 509EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable); 510 511void usb_amd_dev_put(void) 512{ 513 struct pci_dev *nb, *smbus; 514 unsigned long flags; 515 516 spin_lock_irqsave(&amd_lock, flags); 517 518 amd_chipset.probe_count--; 519 if (amd_chipset.probe_count > 0) { 520 spin_unlock_irqrestore(&amd_lock, flags); 521 return; 522 } 523 524 /* save them to pci_dev_put outside of spinlock */ 525 nb = amd_chipset.nb_dev; 526 smbus = amd_chipset.smbus_dev; 527 528 amd_chipset.nb_dev = NULL; 529 amd_chipset.smbus_dev = NULL; 530 amd_chipset.nb_type = 0; 531 memset(&amd_chipset.sb_type, 0, sizeof(amd_chipset.sb_type)); 532 amd_chipset.isoc_reqs = 0; 533 amd_chipset.need_pll_quirk = false; 534 535 spin_unlock_irqrestore(&amd_lock, flags); 536 537 pci_dev_put(nb); 538 pci_dev_put(smbus); 539} 540EXPORT_SYMBOL_GPL(usb_amd_dev_put); 541 542/* 543 * Check if port is disabled in BIOS on AMD Promontory host. 544 * BIOS Disabled ports may wake on connect/disconnect and need 545 * driver workaround to keep them disabled. 546 * Returns true if port is marked disabled. 547 */ 548bool usb_amd_pt_check_port(struct device *device, int port) 549{ 550 unsigned char value, port_shift; 551 struct pci_dev *pdev; 552 u16 reg; 553 554 pdev = to_pci_dev(device); 555 pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_1_ADDR); 556 557 pci_read_config_byte(pdev, PT_READ_INDX, &value); 558 if (value != PT_SIG_1_DATA) 559 return false; 560 561 pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_2_ADDR); 562 563 pci_read_config_byte(pdev, PT_READ_INDX, &value); 564 if (value != PT_SIG_2_DATA) 565 return false; 566 567 pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_3_ADDR); 568 569 pci_read_config_byte(pdev, PT_READ_INDX, &value); 570 if (value != PT_SIG_3_DATA) 571 return false; 572 573 pci_write_config_word(pdev, PT_ADDR_INDX, PT_SIG_4_ADDR); 574 575 pci_read_config_byte(pdev, PT_READ_INDX, &value); 576 if (value != PT_SIG_4_DATA) 577 return false; 578 579 /* Check disabled port setting, if bit is set port is enabled */ 580 switch (pdev->device) { 581 case 0x43b9: 582 case 0x43ba: 583 /* 584 * device is AMD_PROMONTORYA_4(0x43b9) or PROMONTORYA_3(0x43ba) 585 * PT4_P1_REG bits[7..1] represents USB2.0 ports 6 to 0 586 * PT4_P2_REG bits[6..0] represents ports 13 to 7 587 */ 588 if (port > 6) { 589 reg = PT4_P2_REG; 590 port_shift = port - 7; 591 } else { 592 reg = PT4_P1_REG; 593 port_shift = port + 1; 594 } 595 break; 596 case 0x43bb: 597 /* 598 * device is AMD_PROMONTORYA_2(0x43bb) 599 * PT2_P1_REG bits[7..5] represents USB2.0 ports 2 to 0 600 * PT2_P2_REG bits[5..0] represents ports 9 to 3 601 */ 602 if (port > 2) { 603 reg = PT2_P2_REG; 604 port_shift = port - 3; 605 } else { 606 reg = PT2_P1_REG; 607 port_shift = port + 5; 608 } 609 break; 610 case 0x43bc: 611 /* 612 * device is AMD_PROMONTORYA_1(0x43bc) 613 * PT1_P1_REG[7..4] represents USB2.0 ports 3 to 0 614 * PT1_P2_REG[5..0] represents ports 9 to 4 615 */ 616 if (port > 3) { 617 reg = PT1_P2_REG; 618 port_shift = port - 4; 619 } else { 620 reg = PT1_P1_REG; 621 port_shift = port + 4; 622 } 623 break; 624 default: 625 return false; 626 } 627 pci_write_config_word(pdev, PT_ADDR_INDX, reg); 628 pci_read_config_byte(pdev, PT_READ_INDX, &value); 629 630 return !(value & BIT(port_shift)); 631} 632EXPORT_SYMBOL_GPL(usb_amd_pt_check_port); 633 634/* 635 * Make sure the controller is completely inactive, unable to 636 * generate interrupts or do DMA. 637 */ 638void uhci_reset_hc(struct pci_dev *pdev, unsigned long base) 639{ 640 /* Turn off PIRQ enable and SMI enable. (This also turns off the 641 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too. 642 */ 643 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC); 644 645 /* Reset the HC - this will force us to get a 646 * new notification of any already connected 647 * ports due to the virtual disconnect that it 648 * implies. 649 */ 650 outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD); 651 mb(); 652 udelay(5); 653 if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET) 654 dev_warn(&pdev->dev, "HCRESET not completed yet!\n"); 655 656 /* Just to be safe, disable interrupt requests and 657 * make sure the controller is stopped. 658 */ 659 outw(0, base + UHCI_USBINTR); 660 outw(0, base + UHCI_USBCMD); 661} 662EXPORT_SYMBOL_GPL(uhci_reset_hc); 663 664/* 665 * Initialize a controller that was newly discovered or has just been 666 * resumed. In either case we can't be sure of its previous state. 667 * 668 * Returns: 1 if the controller was reset, 0 otherwise. 669 */ 670int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base) 671{ 672 u16 legsup; 673 unsigned int cmd, intr; 674 675 /* 676 * When restarting a suspended controller, we expect all the 677 * settings to be the same as we left them: 678 * 679 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP; 680 * Controller is stopped and configured with EGSM set; 681 * No interrupts enabled except possibly Resume Detect. 682 * 683 * If any of these conditions are violated we do a complete reset. 684 */ 685 pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup); 686 if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) { 687 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n", 688 __func__, legsup); 689 goto reset_needed; 690 } 691 692 cmd = inw(base + UHCI_USBCMD); 693 if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) || 694 !(cmd & UHCI_USBCMD_EGSM)) { 695 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n", 696 __func__, cmd); 697 goto reset_needed; 698 } 699 700 intr = inw(base + UHCI_USBINTR); 701 if (intr & (~UHCI_USBINTR_RESUME)) { 702 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n", 703 __func__, intr); 704 goto reset_needed; 705 } 706 return 0; 707 708reset_needed: 709 dev_dbg(&pdev->dev, "Performing full reset\n"); 710 uhci_reset_hc(pdev, base); 711 return 1; 712} 713EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc); 714 715static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask) 716{ 717 u16 cmd; 718 return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask); 719} 720 721#define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO) 722#define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY) 723 724static void quirk_usb_handoff_uhci(struct pci_dev *pdev) 725{ 726 unsigned long base = 0; 727 int i; 728 729 if (!pio_enabled(pdev)) 730 return; 731 732 for (i = 0; i < PCI_STD_NUM_BARS; i++) 733 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) { 734 base = pci_resource_start(pdev, i); 735 break; 736 } 737 738 if (base) 739 uhci_check_and_reset_hc(pdev, base); 740} 741 742static int mmio_resource_enabled(struct pci_dev *pdev, int idx) 743{ 744 return pci_resource_start(pdev, idx) && mmio_enabled(pdev); 745} 746 747static void quirk_usb_handoff_ohci(struct pci_dev *pdev) 748{ 749 void __iomem *base; 750 u32 control; 751 u32 fminterval = 0; 752 bool no_fminterval = false; 753 int cnt; 754 755 if (!mmio_resource_enabled(pdev, 0)) 756 return; 757 758 base = pci_ioremap_bar(pdev, 0); 759 if (base == NULL) 760 return; 761 762 /* 763 * ULi M5237 OHCI controller locks the whole system when accessing 764 * the OHCI_FMINTERVAL offset. 765 */ 766 if (pdev->vendor == PCI_VENDOR_ID_AL && pdev->device == 0x5237) 767 no_fminterval = true; 768 769 control = readl(base + OHCI_CONTROL); 770 771/* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ 772#ifdef __hppa__ 773#define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR) 774#else 775#define OHCI_CTRL_MASK OHCI_CTRL_RWC 776 777 if (control & OHCI_CTRL_IR) { 778 int wait_time = 500; /* arbitrary; 5 seconds */ 779 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE); 780 writel(OHCI_OCR, base + OHCI_CMDSTATUS); 781 while (wait_time > 0 && 782 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) { 783 wait_time -= 10; 784 msleep(10); 785 } 786 if (wait_time <= 0) 787 dev_warn(&pdev->dev, 788 "OHCI: BIOS handoff failed (BIOS bug?) %08x\n", 789 readl(base + OHCI_CONTROL)); 790 } 791#endif 792 793 /* disable interrupts */ 794 writel((u32) ~0, base + OHCI_INTRDISABLE); 795 796 /* Go into the USB_RESET state, preserving RWC (and possibly IR) */ 797 writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL); 798 readl(base + OHCI_CONTROL); 799 800 /* software reset of the controller, preserving HcFmInterval */ 801 if (!no_fminterval) 802 fminterval = readl(base + OHCI_FMINTERVAL); 803 804 writel(OHCI_HCR, base + OHCI_CMDSTATUS); 805 806 /* reset requires max 10 us delay */ 807 for (cnt = 30; cnt > 0; --cnt) { /* ... allow extra time */ 808 if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0) 809 break; 810 udelay(1); 811 } 812 813 if (!no_fminterval) 814 writel(fminterval, base + OHCI_FMINTERVAL); 815 816 /* Now the controller is safely in SUSPEND and nothing can wake it up */ 817 iounmap(base); 818} 819 820static const struct dmi_system_id ehci_dmi_nohandoff_table[] = { 821 { 822 /* Pegatron Lucid (ExoPC) */ 823 .matches = { 824 DMI_MATCH(DMI_BOARD_NAME, "EXOPG06411"), 825 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-CE-133"), 826 }, 827 }, 828 { 829 /* Pegatron Lucid (Ordissimo AIRIS) */ 830 .matches = { 831 DMI_MATCH(DMI_BOARD_NAME, "M11JB"), 832 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"), 833 }, 834 }, 835 { 836 /* Pegatron Lucid (Ordissimo) */ 837 .matches = { 838 DMI_MATCH(DMI_BOARD_NAME, "Ordissimo"), 839 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"), 840 }, 841 }, 842 { 843 /* HASEE E200 */ 844 .matches = { 845 DMI_MATCH(DMI_BOARD_VENDOR, "HASEE"), 846 DMI_MATCH(DMI_BOARD_NAME, "E210"), 847 DMI_MATCH(DMI_BIOS_VERSION, "6.00"), 848 }, 849 }, 850 { } 851}; 852 853static void ehci_bios_handoff(struct pci_dev *pdev, 854 void __iomem *op_reg_base, 855 u32 cap, u8 offset) 856{ 857 int try_handoff = 1, tried_handoff = 0; 858 859 /* 860 * The Pegatron Lucid tablet sporadically waits for 98 seconds trying 861 * the handoff on its unused controller. Skip it. 862 * 863 * The HASEE E200 hangs when the semaphore is set (bugzilla #77021). 864 */ 865 if (pdev->vendor == 0x8086 && (pdev->device == 0x283a || 866 pdev->device == 0x27cc)) { 867 if (dmi_check_system(ehci_dmi_nohandoff_table)) 868 try_handoff = 0; 869 } 870 871 if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) { 872 dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n"); 873 874#if 0 875/* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on, 876 * but that seems dubious in general (the BIOS left it off intentionally) 877 * and is known to prevent some systems from booting. so we won't do this 878 * unless maybe we can determine when we're on a system that needs SMI forced. 879 */ 880 /* BIOS workaround (?): be sure the pre-Linux code 881 * receives the SMI 882 */ 883 pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val); 884 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 885 val | EHCI_USBLEGCTLSTS_SOOE); 886#endif 887 888 /* some systems get upset if this semaphore is 889 * set for any other reason than forcing a BIOS 890 * handoff.. 891 */ 892 pci_write_config_byte(pdev, offset + 3, 1); 893 } 894 895 /* if boot firmware now owns EHCI, spin till it hands it over. */ 896 if (try_handoff) { 897 int msec = 1000; 898 while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) { 899 tried_handoff = 1; 900 msleep(10); 901 msec -= 10; 902 pci_read_config_dword(pdev, offset, &cap); 903 } 904 } 905 906 if (cap & EHCI_USBLEGSUP_BIOS) { 907 /* well, possibly buggy BIOS... try to shut it down, 908 * and hope nothing goes too wrong 909 */ 910 if (try_handoff) 911 dev_warn(&pdev->dev, 912 "EHCI: BIOS handoff failed (BIOS bug?) %08x\n", 913 cap); 914 pci_write_config_byte(pdev, offset + 2, 0); 915 } 916 917 /* just in case, always disable EHCI SMIs */ 918 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0); 919 920 /* If the BIOS ever owned the controller then we can't expect 921 * any power sessions to remain intact. 922 */ 923 if (tried_handoff) 924 writel(0, op_reg_base + EHCI_CONFIGFLAG); 925} 926 927static void quirk_usb_disable_ehci(struct pci_dev *pdev) 928{ 929 void __iomem *base, *op_reg_base; 930 u32 hcc_params, cap, val; 931 u8 offset, cap_length; 932 int wait_time, count = 256/4; 933 934 if (!mmio_resource_enabled(pdev, 0)) 935 return; 936 937 base = pci_ioremap_bar(pdev, 0); 938 if (base == NULL) 939 return; 940 941 cap_length = readb(base); 942 op_reg_base = base + cap_length; 943 944 /* EHCI 0.96 and later may have "extended capabilities" 945 * spec section 5.1 explains the bios handoff, e.g. for 946 * booting from USB disk or using a usb keyboard 947 */ 948 hcc_params = readl(base + EHCI_HCC_PARAMS); 949 offset = (hcc_params >> 8) & 0xff; 950 while (offset && --count) { 951 pci_read_config_dword(pdev, offset, &cap); 952 953 switch (cap & 0xff) { 954 case 1: 955 ehci_bios_handoff(pdev, op_reg_base, cap, offset); 956 break; 957 case 0: /* Illegal reserved cap, set cap=0 so we exit */ 958 cap = 0; 959 fallthrough; 960 default: 961 dev_warn(&pdev->dev, 962 "EHCI: unrecognized capability %02x\n", 963 cap & 0xff); 964 } 965 offset = (cap >> 8) & 0xff; 966 } 967 if (!count) 968 dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n"); 969 970 /* 971 * halt EHCI & disable its interrupts in any case 972 */ 973 val = readl(op_reg_base + EHCI_USBSTS); 974 if ((val & EHCI_USBSTS_HALTED) == 0) { 975 val = readl(op_reg_base + EHCI_USBCMD); 976 val &= ~EHCI_USBCMD_RUN; 977 writel(val, op_reg_base + EHCI_USBCMD); 978 979 wait_time = 2000; 980 do { 981 writel(0x3f, op_reg_base + EHCI_USBSTS); 982 udelay(100); 983 wait_time -= 100; 984 val = readl(op_reg_base + EHCI_USBSTS); 985 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) { 986 break; 987 } 988 } while (wait_time > 0); 989 } 990 writel(0, op_reg_base + EHCI_USBINTR); 991 writel(0x3f, op_reg_base + EHCI_USBSTS); 992 993 iounmap(base); 994} 995 996/* 997 * handshake - spin reading a register until handshake completes 998 * @ptr: address of hc register to be read 999 * @mask: bits to look at in result of read 1000 * @done: value of those bits when handshake succeeds 1001 * @wait_usec: timeout in microseconds 1002 * @delay_usec: delay in microseconds to wait between polling 1003 * 1004 * Polls a register every delay_usec microseconds. 1005 * Returns 0 when the mask bits have the value done. 1006 * Returns -ETIMEDOUT if this condition is not true after 1007 * wait_usec microseconds have passed. 1008 */ 1009static int handshake(void __iomem *ptr, u32 mask, u32 done, 1010 int wait_usec, int delay_usec) 1011{ 1012 u32 result; 1013 1014 return readl_poll_timeout_atomic(ptr, result, 1015 ((result & mask) == done), 1016 delay_usec, wait_usec); 1017} 1018 1019/* 1020 * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that 1021 * share some number of ports. These ports can be switched between either 1022 * controller. Not all of the ports under the EHCI host controller may be 1023 * switchable. 1024 * 1025 * The ports should be switched over to xHCI before PCI probes for any device 1026 * start. This avoids active devices under EHCI being disconnected during the 1027 * port switchover, which could cause loss of data on USB storage devices, or 1028 * failed boot when the root file system is on a USB mass storage device and is 1029 * enumerated under EHCI first. 1030 * 1031 * We write into the xHC's PCI configuration space in some Intel-specific 1032 * registers to switch the ports over. The USB 3.0 terminations and the USB 1033 * 2.0 data wires are switched separately. We want to enable the SuperSpeed 1034 * terminations before switching the USB 2.0 wires over, so that USB 3.0 1035 * devices connect at SuperSpeed, rather than at USB 2.0 speeds. 1036 */ 1037void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev) 1038{ 1039 u32 ports_available; 1040 bool ehci_found = false; 1041 struct pci_dev *companion = NULL; 1042 1043 /* Sony VAIO t-series with subsystem device ID 90a8 is not capable of 1044 * switching ports from EHCI to xHCI 1045 */ 1046 if (xhci_pdev->subsystem_vendor == PCI_VENDOR_ID_SONY && 1047 xhci_pdev->subsystem_device == 0x90a8) 1048 return; 1049 1050 /* make sure an intel EHCI controller exists */ 1051 for_each_pci_dev(companion) { 1052 if (companion->class == PCI_CLASS_SERIAL_USB_EHCI && 1053 companion->vendor == PCI_VENDOR_ID_INTEL) { 1054 ehci_found = true; 1055 break; 1056 } 1057 } 1058 1059 if (!ehci_found) 1060 return; 1061 1062 /* Don't switchover the ports if the user hasn't compiled the xHCI 1063 * driver. Otherwise they will see "dead" USB ports that don't power 1064 * the devices. 1065 */ 1066 if (!IS_ENABLED(CONFIG_USB_XHCI_HCD)) { 1067 dev_warn(&xhci_pdev->dev, 1068 "CONFIG_USB_XHCI_HCD is turned off, defaulting to EHCI.\n"); 1069 dev_warn(&xhci_pdev->dev, 1070 "USB 3.0 devices will work at USB 2.0 speeds.\n"); 1071 usb_disable_xhci_ports(xhci_pdev); 1072 return; 1073 } 1074 1075 /* Read USB3PRM, the USB 3.0 Port Routing Mask Register 1076 * Indicate the ports that can be changed from OS. 1077 */ 1078 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3PRM, 1079 &ports_available); 1080 1081 dev_dbg(&xhci_pdev->dev, "Configurable ports to enable SuperSpeed: 0x%x\n", 1082 ports_available); 1083 1084 /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable 1085 * Register, to turn on SuperSpeed terminations for the 1086 * switchable ports. 1087 */ 1088 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 1089 ports_available); 1090 1091 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 1092 &ports_available); 1093 dev_dbg(&xhci_pdev->dev, 1094 "USB 3.0 ports that are now enabled under xHCI: 0x%x\n", 1095 ports_available); 1096 1097 /* Read XUSB2PRM, xHCI USB 2.0 Port Routing Mask Register 1098 * Indicate the USB 2.0 ports to be controlled by the xHCI host. 1099 */ 1100 1101 pci_read_config_dword(xhci_pdev, USB_INTEL_USB2PRM, 1102 &ports_available); 1103 1104 dev_dbg(&xhci_pdev->dev, "Configurable USB 2.0 ports to hand over to xCHI: 0x%x\n", 1105 ports_available); 1106 1107 /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to 1108 * switch the USB 2.0 power and data lines over to the xHCI 1109 * host. 1110 */ 1111 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 1112 ports_available); 1113 1114 pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 1115 &ports_available); 1116 dev_dbg(&xhci_pdev->dev, 1117 "USB 2.0 ports that are now switched over to xHCI: 0x%x\n", 1118 ports_available); 1119} 1120EXPORT_SYMBOL_GPL(usb_enable_intel_xhci_ports); 1121 1122void usb_disable_xhci_ports(struct pci_dev *xhci_pdev) 1123{ 1124 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 0x0); 1125 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 0x0); 1126} 1127EXPORT_SYMBOL_GPL(usb_disable_xhci_ports); 1128 1129/* 1130 * PCI Quirks for xHCI. 1131 * 1132 * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS. 1133 * It signals to the BIOS that the OS wants control of the host controller, 1134 * and then waits 1 second for the BIOS to hand over control. 1135 * If we timeout, assume the BIOS is broken and take control anyway. 1136 */ 1137static void quirk_usb_handoff_xhci(struct pci_dev *pdev) 1138{ 1139 void __iomem *base; 1140 int ext_cap_offset; 1141 void __iomem *op_reg_base; 1142 u32 val; 1143 int timeout; 1144 int len = pci_resource_len(pdev, 0); 1145 1146 if (!mmio_resource_enabled(pdev, 0)) 1147 return; 1148 1149 base = ioremap(pci_resource_start(pdev, 0), len); 1150 if (base == NULL) 1151 return; 1152 1153 /* 1154 * Find the Legacy Support Capability register - 1155 * this is optional for xHCI host controllers. 1156 */ 1157 ext_cap_offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_LEGACY); 1158 1159 if (!ext_cap_offset) 1160 goto hc_init; 1161 1162 if ((ext_cap_offset + sizeof(val)) > len) { 1163 /* We're reading garbage from the controller */ 1164 dev_warn(&pdev->dev, "xHCI controller failing to respond"); 1165 goto iounmap; 1166 } 1167 val = readl(base + ext_cap_offset); 1168 1169 /* Auto handoff never worked for these devices. Force it and continue */ 1170 if ((pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) || 1171 (pdev->vendor == PCI_VENDOR_ID_RENESAS 1172 && pdev->device == 0x0014)) { 1173 val = (val | XHCI_HC_OS_OWNED) & ~XHCI_HC_BIOS_OWNED; 1174 writel(val, base + ext_cap_offset); 1175 } 1176 1177 /* If the BIOS owns the HC, signal that the OS wants it, and wait */ 1178 if (val & XHCI_HC_BIOS_OWNED) { 1179 writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset); 1180 1181 /* Wait for 1 second with 10 microsecond polling interval */ 1182 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED, 1183 0, 1000000, 10); 1184 1185 /* Assume a buggy BIOS and take HC ownership anyway */ 1186 if (timeout) { 1187 dev_warn(&pdev->dev, 1188 "xHCI BIOS handoff failed (BIOS bug ?) %08x\n", 1189 val); 1190 writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset); 1191 } 1192 } 1193 1194 val = readl(base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); 1195 /* Mask off (turn off) any enabled SMIs */ 1196 val &= XHCI_LEGACY_DISABLE_SMI; 1197 /* Mask all SMI events bits, RW1C */ 1198 val |= XHCI_LEGACY_SMI_EVENTS; 1199 /* Disable any BIOS SMIs and clear all SMI events*/ 1200 writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET); 1201 1202hc_init: 1203 if (pdev->vendor == PCI_VENDOR_ID_INTEL) 1204 usb_enable_intel_xhci_ports(pdev); 1205 1206 op_reg_base = base + XHCI_HC_LENGTH(readl(base)); 1207 1208 /* Wait for the host controller to be ready before writing any 1209 * operational or runtime registers. Wait 5 seconds and no more. 1210 */ 1211 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0, 1212 5000000, 10); 1213 /* Assume a buggy HC and start HC initialization anyway */ 1214 if (timeout) { 1215 val = readl(op_reg_base + XHCI_STS_OFFSET); 1216 dev_warn(&pdev->dev, 1217 "xHCI HW not ready after 5 sec (HC bug?) status = 0x%x\n", 1218 val); 1219 } 1220 1221 /* Send the halt and disable interrupts command */ 1222 val = readl(op_reg_base + XHCI_CMD_OFFSET); 1223 val &= ~(XHCI_CMD_RUN | XHCI_IRQS); 1224 writel(val, op_reg_base + XHCI_CMD_OFFSET); 1225 1226 /* Wait for the HC to halt - poll every 125 usec (one microframe). */ 1227 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1, 1228 XHCI_MAX_HALT_USEC, 125); 1229 if (timeout) { 1230 val = readl(op_reg_base + XHCI_STS_OFFSET); 1231 dev_warn(&pdev->dev, 1232 "xHCI HW did not halt within %d usec status = 0x%x\n", 1233 XHCI_MAX_HALT_USEC, val); 1234 } 1235 1236iounmap: 1237 iounmap(base); 1238} 1239 1240static void quirk_usb_early_handoff(struct pci_dev *pdev) 1241{ 1242 struct device_node *parent; 1243 bool is_rpi; 1244 1245 /* Skip Netlogic mips SoC's internal PCI USB controller. 1246 * This device does not need/support EHCI/OHCI handoff 1247 */ 1248 if (pdev->vendor == 0x184e) /* vendor Netlogic */ 1249 return; 1250 1251 /* 1252 * Bypass the Raspberry Pi 4 controller xHCI controller, things are 1253 * taken care of by the board's co-processor. 1254 */ 1255 if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) { 1256 parent = of_get_parent(pdev->bus->dev.of_node); 1257 is_rpi = of_device_is_compatible(parent, "brcm,bcm2711-pcie"); 1258 of_node_put(parent); 1259 if (is_rpi) 1260 return; 1261 } 1262 1263 if (pdev->class != PCI_CLASS_SERIAL_USB_UHCI && 1264 pdev->class != PCI_CLASS_SERIAL_USB_OHCI && 1265 pdev->class != PCI_CLASS_SERIAL_USB_EHCI && 1266 pdev->class != PCI_CLASS_SERIAL_USB_XHCI) 1267 return; 1268 1269 if (pci_enable_device(pdev) < 0) { 1270 dev_warn(&pdev->dev, 1271 "Can't enable PCI device, BIOS handoff failed.\n"); 1272 return; 1273 } 1274 if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI) 1275 quirk_usb_handoff_uhci(pdev); 1276 else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI) 1277 quirk_usb_handoff_ohci(pdev); 1278 else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI) 1279 quirk_usb_disable_ehci(pdev); 1280 else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI) 1281 quirk_usb_handoff_xhci(pdev); 1282 pci_disable_device(pdev); 1283} 1284DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1285 PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff); 1286