1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2018, The Linux Foundation. All rights reserved. 3 * 4 * Inspired by dwc3-of-simple.c 5 */ 6 7#include <linux/acpi.h> 8#include <linux/io.h> 9#include <linux/of.h> 10#include <linux/clk.h> 11#include <linux/irq.h> 12#include <linux/of_clk.h> 13#include <linux/module.h> 14#include <linux/kernel.h> 15#include <linux/extcon.h> 16#include <linux/interconnect.h> 17#include <linux/of_platform.h> 18#include <linux/platform_device.h> 19#include <linux/phy/phy.h> 20#include <linux/usb/of.h> 21#include <linux/reset.h> 22#include <linux/iopoll.h> 23#include <linux/usb/hcd.h> 24#include <linux/usb.h> 25#include "core.h" 26 27/* USB QSCRATCH Hardware registers */ 28#define QSCRATCH_HS_PHY_CTRL 0x10 29#define UTMI_OTG_VBUS_VALID BIT(20) 30#define SW_SESSVLD_SEL BIT(28) 31 32#define QSCRATCH_SS_PHY_CTRL 0x30 33#define LANE0_PWR_PRESENT BIT(24) 34 35#define QSCRATCH_GENERAL_CFG 0x08 36#define PIPE_UTMI_CLK_SEL BIT(0) 37#define PIPE3_PHYSTATUS_SW BIT(3) 38#define PIPE_UTMI_CLK_DIS BIT(8) 39 40#define PWR_EVNT_IRQ_STAT_REG 0x58 41#define PWR_EVNT_LPM_IN_L2_MASK BIT(4) 42#define PWR_EVNT_LPM_OUT_L2_MASK BIT(5) 43 44#define SDM845_QSCRATCH_BASE_OFFSET 0xf8800 45#define SDM845_QSCRATCH_SIZE 0x400 46#define SDM845_DWC3_CORE_SIZE 0xcd00 47 48/* Interconnect path bandwidths in MBps */ 49#define USB_MEMORY_AVG_HS_BW MBps_to_icc(240) 50#define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700) 51#define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000) 52#define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500) 53#define APPS_USB_AVG_BW 0 54#define APPS_USB_PEAK_BW MBps_to_icc(40) 55 56struct dwc3_acpi_pdata { 57 u32 qscratch_base_offset; 58 u32 qscratch_base_size; 59 u32 dwc3_core_base_size; 60 int hs_phy_irq_index; 61 int dp_hs_phy_irq_index; 62 int dm_hs_phy_irq_index; 63 int ss_phy_irq_index; 64 bool is_urs; 65}; 66 67struct dwc3_qcom { 68 struct device *dev; 69 void __iomem *qscratch_base; 70 struct platform_device *dwc3; 71 struct platform_device *urs_usb; 72 struct clk **clks; 73 int num_clocks; 74 struct reset_control *resets; 75 76 int hs_phy_irq; 77 int dp_hs_phy_irq; 78 int dm_hs_phy_irq; 79 int ss_phy_irq; 80 enum usb_device_speed usb2_speed; 81 82 struct extcon_dev *edev; 83 struct extcon_dev *host_edev; 84 struct notifier_block vbus_nb; 85 struct notifier_block host_nb; 86 87 const struct dwc3_acpi_pdata *acpi_pdata; 88 89 enum usb_dr_mode mode; 90 bool is_suspended; 91 bool pm_suspended; 92 struct icc_path *icc_path_ddr; 93 struct icc_path *icc_path_apps; 94}; 95 96static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val) 97{ 98 u32 reg; 99 100 reg = readl(base + offset); 101 reg |= val; 102 writel(reg, base + offset); 103 104 /* ensure that above write is through */ 105 readl(base + offset); 106} 107 108static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val) 109{ 110 u32 reg; 111 112 reg = readl(base + offset); 113 reg &= ~val; 114 writel(reg, base + offset); 115 116 /* ensure that above write is through */ 117 readl(base + offset); 118} 119 120static void dwc3_qcom_vbus_override_enable(struct dwc3_qcom *qcom, bool enable) 121{ 122 if (enable) { 123 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, 124 LANE0_PWR_PRESENT); 125 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, 126 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL); 127 } else { 128 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, 129 LANE0_PWR_PRESENT); 130 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, 131 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL); 132 } 133} 134 135static int dwc3_qcom_vbus_notifier(struct notifier_block *nb, 136 unsigned long event, void *ptr) 137{ 138 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb); 139 140 /* enable vbus override for device mode */ 141 dwc3_qcom_vbus_override_enable(qcom, event); 142 qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST; 143 144 return NOTIFY_DONE; 145} 146 147static int dwc3_qcom_host_notifier(struct notifier_block *nb, 148 unsigned long event, void *ptr) 149{ 150 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb); 151 152 /* disable vbus override in host mode */ 153 dwc3_qcom_vbus_override_enable(qcom, !event); 154 qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL; 155 156 return NOTIFY_DONE; 157} 158 159static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom) 160{ 161 struct device *dev = qcom->dev; 162 struct extcon_dev *host_edev; 163 int ret; 164 165 if (!of_property_read_bool(dev->of_node, "extcon")) 166 return 0; 167 168 qcom->edev = extcon_get_edev_by_phandle(dev, 0); 169 if (IS_ERR(qcom->edev)) 170 return dev_err_probe(dev, PTR_ERR(qcom->edev), 171 "Failed to get extcon\n"); 172 173 qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier; 174 175 qcom->host_edev = extcon_get_edev_by_phandle(dev, 1); 176 if (IS_ERR(qcom->host_edev)) 177 qcom->host_edev = NULL; 178 179 ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB, 180 &qcom->vbus_nb); 181 if (ret < 0) { 182 dev_err(dev, "VBUS notifier register failed\n"); 183 return ret; 184 } 185 186 if (qcom->host_edev) 187 host_edev = qcom->host_edev; 188 else 189 host_edev = qcom->edev; 190 191 qcom->host_nb.notifier_call = dwc3_qcom_host_notifier; 192 ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST, 193 &qcom->host_nb); 194 if (ret < 0) { 195 dev_err(dev, "Host notifier register failed\n"); 196 return ret; 197 } 198 199 /* Update initial VBUS override based on extcon state */ 200 if (extcon_get_state(qcom->edev, EXTCON_USB) || 201 !extcon_get_state(host_edev, EXTCON_USB_HOST)) 202 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev); 203 else 204 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev); 205 206 return 0; 207} 208 209static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom) 210{ 211 int ret; 212 213 ret = icc_enable(qcom->icc_path_ddr); 214 if (ret) 215 return ret; 216 217 ret = icc_enable(qcom->icc_path_apps); 218 if (ret) 219 icc_disable(qcom->icc_path_ddr); 220 221 return ret; 222} 223 224static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom) 225{ 226 int ret; 227 228 ret = icc_disable(qcom->icc_path_ddr); 229 if (ret) 230 return ret; 231 232 ret = icc_disable(qcom->icc_path_apps); 233 if (ret) 234 icc_enable(qcom->icc_path_ddr); 235 236 return ret; 237} 238 239/** 240 * dwc3_qcom_interconnect_init() - Get interconnect path handles 241 * and set bandwidth. 242 * @qcom: Pointer to the concerned usb core. 243 * 244 */ 245static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom) 246{ 247 enum usb_device_speed max_speed; 248 struct device *dev = qcom->dev; 249 int ret; 250 251 if (has_acpi_companion(dev)) 252 return 0; 253 254 qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr"); 255 if (IS_ERR(qcom->icc_path_ddr)) { 256 return dev_err_probe(dev, PTR_ERR(qcom->icc_path_ddr), 257 "failed to get usb-ddr path\n"); 258 } 259 260 qcom->icc_path_apps = of_icc_get(dev, "apps-usb"); 261 if (IS_ERR(qcom->icc_path_apps)) { 262 ret = dev_err_probe(dev, PTR_ERR(qcom->icc_path_apps), 263 "failed to get apps-usb path\n"); 264 goto put_path_ddr; 265 } 266 267 max_speed = usb_get_maximum_speed(&qcom->dwc3->dev); 268 if (max_speed >= USB_SPEED_SUPER || max_speed == USB_SPEED_UNKNOWN) { 269 ret = icc_set_bw(qcom->icc_path_ddr, 270 USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW); 271 } else { 272 ret = icc_set_bw(qcom->icc_path_ddr, 273 USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW); 274 } 275 if (ret) { 276 dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret); 277 goto put_path_apps; 278 } 279 280 ret = icc_set_bw(qcom->icc_path_apps, APPS_USB_AVG_BW, APPS_USB_PEAK_BW); 281 if (ret) { 282 dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret); 283 goto put_path_apps; 284 } 285 286 return 0; 287 288put_path_apps: 289 icc_put(qcom->icc_path_apps); 290put_path_ddr: 291 icc_put(qcom->icc_path_ddr); 292 return ret; 293} 294 295/** 296 * dwc3_qcom_interconnect_exit() - Release interconnect path handles 297 * @qcom: Pointer to the concerned usb core. 298 * 299 * This function is used to release interconnect path handle. 300 */ 301static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom) 302{ 303 icc_put(qcom->icc_path_ddr); 304 icc_put(qcom->icc_path_apps); 305} 306 307/* Only usable in contexts where the role can not change. */ 308static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom) 309{ 310 struct dwc3 *dwc; 311 312 /* 313 * FIXME: Fix this layering violation. 314 */ 315 dwc = platform_get_drvdata(qcom->dwc3); 316 317 /* Core driver may not have probed yet. */ 318 if (!dwc) 319 return false; 320 321 return dwc->xhci; 322} 323 324static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom) 325{ 326 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); 327 struct usb_device *udev; 328 struct usb_hcd __maybe_unused *hcd; 329 330 /* 331 * FIXME: Fix this layering violation. 332 */ 333 hcd = platform_get_drvdata(dwc->xhci); 334 335 /* 336 * It is possible to query the speed of all children of 337 * USB2.0 root hub via usb_hub_for_each_child(). DWC3 code 338 * currently supports only 1 port per controller. So 339 * this is sufficient. 340 */ 341#ifdef CONFIG_USB 342 udev = usb_hub_find_child(hcd->self.root_hub, 1); 343#else 344 udev = NULL; 345#endif 346 if (!udev) 347 return USB_SPEED_UNKNOWN; 348 349 return udev->speed; 350} 351 352static void dwc3_qcom_enable_wakeup_irq(int irq, unsigned int polarity) 353{ 354 if (!irq) 355 return; 356 357 if (polarity) 358 irq_set_irq_type(irq, polarity); 359 360 enable_irq(irq); 361 enable_irq_wake(irq); 362} 363 364static void dwc3_qcom_disable_wakeup_irq(int irq) 365{ 366 if (!irq) 367 return; 368 369 disable_irq_wake(irq); 370 disable_irq_nosync(irq); 371} 372 373static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom) 374{ 375 dwc3_qcom_disable_wakeup_irq(qcom->hs_phy_irq); 376 377 if (qcom->usb2_speed == USB_SPEED_LOW) { 378 dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq); 379 } else if ((qcom->usb2_speed == USB_SPEED_HIGH) || 380 (qcom->usb2_speed == USB_SPEED_FULL)) { 381 dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq); 382 } else { 383 dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq); 384 dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq); 385 } 386 387 dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq); 388} 389 390static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) 391{ 392 dwc3_qcom_enable_wakeup_irq(qcom->hs_phy_irq, 0); 393 394 /* 395 * Configure DP/DM line interrupts based on the USB2 device attached to 396 * the root hub port. When HS/FS device is connected, configure the DP line 397 * as falling edge to detect both disconnect and remote wakeup scenarios. When 398 * LS device is connected, configure DM line as falling edge to detect both 399 * disconnect and remote wakeup. When no device is connected, configure both 400 * DP and DM lines as rising edge to detect HS/HS/LS device connect scenario. 401 */ 402 403 if (qcom->usb2_speed == USB_SPEED_LOW) { 404 dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq, 405 IRQ_TYPE_EDGE_FALLING); 406 } else if ((qcom->usb2_speed == USB_SPEED_HIGH) || 407 (qcom->usb2_speed == USB_SPEED_FULL)) { 408 dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq, 409 IRQ_TYPE_EDGE_FALLING); 410 } else { 411 dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq, 412 IRQ_TYPE_EDGE_RISING); 413 dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq, 414 IRQ_TYPE_EDGE_RISING); 415 } 416 417 dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq, 0); 418} 419 420static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) 421{ 422 u32 val; 423 int i, ret; 424 425 if (qcom->is_suspended) 426 return 0; 427 428 val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG); 429 if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) 430 dev_err(qcom->dev, "HS-PHY not in L2\n"); 431 432 for (i = qcom->num_clocks - 1; i >= 0; i--) 433 clk_disable_unprepare(qcom->clks[i]); 434 435 ret = dwc3_qcom_interconnect_disable(qcom); 436 if (ret) 437 dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret); 438 439 /* 440 * The role is stable during suspend as role switching is done from a 441 * freezable workqueue. 442 */ 443 if (dwc3_qcom_is_host(qcom) && wakeup) { 444 qcom->usb2_speed = dwc3_qcom_read_usb2_speed(qcom); 445 dwc3_qcom_enable_interrupts(qcom); 446 } 447 448 qcom->is_suspended = true; 449 450 return 0; 451} 452 453static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup) 454{ 455 int ret; 456 int i; 457 458 if (!qcom->is_suspended) 459 return 0; 460 461 if (dwc3_qcom_is_host(qcom) && wakeup) 462 dwc3_qcom_disable_interrupts(qcom); 463 464 for (i = 0; i < qcom->num_clocks; i++) { 465 ret = clk_prepare_enable(qcom->clks[i]); 466 if (ret < 0) { 467 while (--i >= 0) 468 clk_disable_unprepare(qcom->clks[i]); 469 return ret; 470 } 471 } 472 473 ret = dwc3_qcom_interconnect_enable(qcom); 474 if (ret) 475 dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret); 476 477 /* Clear existing events from PHY related to L2 in/out */ 478 dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG, 479 PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); 480 481 qcom->is_suspended = false; 482 483 return 0; 484} 485 486static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data) 487{ 488 struct dwc3_qcom *qcom = data; 489 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); 490 491 /* If pm_suspended then let pm_resume take care of resuming h/w */ 492 if (qcom->pm_suspended) 493 return IRQ_HANDLED; 494 495 /* 496 * This is safe as role switching is done from a freezable workqueue 497 * and the wakeup interrupts are disabled as part of resume. 498 */ 499 if (dwc3_qcom_is_host(qcom)) 500 pm_runtime_resume(&dwc->xhci->dev); 501 502 return IRQ_HANDLED; 503} 504 505static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom) 506{ 507 /* Configure dwc3 to use UTMI clock as PIPE clock not present */ 508 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, 509 PIPE_UTMI_CLK_DIS); 510 511 usleep_range(100, 1000); 512 513 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, 514 PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW); 515 516 usleep_range(100, 1000); 517 518 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, 519 PIPE_UTMI_CLK_DIS); 520} 521 522static int dwc3_qcom_get_irq(struct platform_device *pdev, 523 const char *name, int num) 524{ 525 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 526 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : pdev; 527 struct device_node *np = pdev->dev.of_node; 528 int ret; 529 530 if (np) 531 ret = platform_get_irq_byname_optional(pdev_irq, name); 532 else 533 ret = platform_get_irq_optional(pdev_irq, num); 534 535 return ret; 536} 537 538static int dwc3_qcom_setup_irq(struct platform_device *pdev) 539{ 540 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 541 const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata; 542 int irq; 543 int ret; 544 545 irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq", 546 pdata ? pdata->hs_phy_irq_index : -1); 547 if (irq > 0) { 548 /* Keep wakeup interrupts disabled until suspend */ 549 irq_set_status_flags(irq, IRQ_NOAUTOEN); 550 ret = devm_request_threaded_irq(qcom->dev, irq, NULL, 551 qcom_dwc3_resume_irq, 552 IRQF_ONESHOT, 553 "qcom_dwc3 HS", qcom); 554 if (ret) { 555 dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret); 556 return ret; 557 } 558 qcom->hs_phy_irq = irq; 559 } 560 561 irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq", 562 pdata ? pdata->dp_hs_phy_irq_index : -1); 563 if (irq > 0) { 564 irq_set_status_flags(irq, IRQ_NOAUTOEN); 565 ret = devm_request_threaded_irq(qcom->dev, irq, NULL, 566 qcom_dwc3_resume_irq, 567 IRQF_ONESHOT, 568 "qcom_dwc3 DP_HS", qcom); 569 if (ret) { 570 dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret); 571 return ret; 572 } 573 qcom->dp_hs_phy_irq = irq; 574 } 575 576 irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq", 577 pdata ? pdata->dm_hs_phy_irq_index : -1); 578 if (irq > 0) { 579 irq_set_status_flags(irq, IRQ_NOAUTOEN); 580 ret = devm_request_threaded_irq(qcom->dev, irq, NULL, 581 qcom_dwc3_resume_irq, 582 IRQF_ONESHOT, 583 "qcom_dwc3 DM_HS", qcom); 584 if (ret) { 585 dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret); 586 return ret; 587 } 588 qcom->dm_hs_phy_irq = irq; 589 } 590 591 irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq", 592 pdata ? pdata->ss_phy_irq_index : -1); 593 if (irq > 0) { 594 irq_set_status_flags(irq, IRQ_NOAUTOEN); 595 ret = devm_request_threaded_irq(qcom->dev, irq, NULL, 596 qcom_dwc3_resume_irq, 597 IRQF_ONESHOT, 598 "qcom_dwc3 SS", qcom); 599 if (ret) { 600 dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret); 601 return ret; 602 } 603 qcom->ss_phy_irq = irq; 604 } 605 606 return 0; 607} 608 609static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count) 610{ 611 struct device *dev = qcom->dev; 612 struct device_node *np = dev->of_node; 613 int i; 614 615 if (!np || !count) 616 return 0; 617 618 if (count < 0) 619 return count; 620 621 qcom->num_clocks = count; 622 623 qcom->clks = devm_kcalloc(dev, qcom->num_clocks, 624 sizeof(struct clk *), GFP_KERNEL); 625 if (!qcom->clks) 626 return -ENOMEM; 627 628 for (i = 0; i < qcom->num_clocks; i++) { 629 struct clk *clk; 630 int ret; 631 632 clk = of_clk_get(np, i); 633 if (IS_ERR(clk)) { 634 while (--i >= 0) 635 clk_put(qcom->clks[i]); 636 return PTR_ERR(clk); 637 } 638 639 ret = clk_prepare_enable(clk); 640 if (ret < 0) { 641 while (--i >= 0) { 642 clk_disable_unprepare(qcom->clks[i]); 643 clk_put(qcom->clks[i]); 644 } 645 clk_put(clk); 646 647 return ret; 648 } 649 650 qcom->clks[i] = clk; 651 } 652 653 return 0; 654} 655 656static const struct property_entry dwc3_qcom_acpi_properties[] = { 657 PROPERTY_ENTRY_STRING("dr_mode", "host"), 658 {} 659}; 660 661static const struct software_node dwc3_qcom_swnode = { 662 .properties = dwc3_qcom_acpi_properties, 663}; 664 665static int dwc3_qcom_acpi_register_core(struct platform_device *pdev) 666{ 667 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 668 struct device *dev = &pdev->dev; 669 struct resource *res, *child_res = NULL; 670 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : 671 pdev; 672 int irq; 673 int ret; 674 675 qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); 676 if (!qcom->dwc3) 677 return -ENOMEM; 678 679 qcom->dwc3->dev.parent = dev; 680 qcom->dwc3->dev.type = dev->type; 681 qcom->dwc3->dev.dma_mask = dev->dma_mask; 682 qcom->dwc3->dev.dma_parms = dev->dma_parms; 683 qcom->dwc3->dev.coherent_dma_mask = dev->coherent_dma_mask; 684 685 child_res = kcalloc(2, sizeof(*child_res), GFP_KERNEL); 686 if (!child_res) { 687 platform_device_put(qcom->dwc3); 688 return -ENOMEM; 689 } 690 691 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 692 if (!res) { 693 dev_err(&pdev->dev, "failed to get memory resource\n"); 694 ret = -ENODEV; 695 goto out; 696 } 697 698 child_res[0].flags = res->flags; 699 child_res[0].start = res->start; 700 child_res[0].end = child_res[0].start + 701 qcom->acpi_pdata->dwc3_core_base_size; 702 703 irq = platform_get_irq(pdev_irq, 0); 704 if (irq < 0) { 705 ret = irq; 706 goto out; 707 } 708 child_res[1].flags = IORESOURCE_IRQ; 709 child_res[1].start = child_res[1].end = irq; 710 711 ret = platform_device_add_resources(qcom->dwc3, child_res, 2); 712 if (ret) { 713 dev_err(&pdev->dev, "failed to add resources\n"); 714 goto out; 715 } 716 717 ret = device_add_software_node(&qcom->dwc3->dev, &dwc3_qcom_swnode); 718 if (ret < 0) { 719 dev_err(&pdev->dev, "failed to add properties\n"); 720 goto out; 721 } 722 723 ret = platform_device_add(qcom->dwc3); 724 if (ret) { 725 dev_err(&pdev->dev, "failed to add device\n"); 726 device_remove_software_node(&qcom->dwc3->dev); 727 goto out; 728 } 729 kfree(child_res); 730 return 0; 731 732out: 733 platform_device_put(qcom->dwc3); 734 kfree(child_res); 735 return ret; 736} 737 738static int dwc3_qcom_of_register_core(struct platform_device *pdev) 739{ 740 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 741 struct device_node *np = pdev->dev.of_node, *dwc3_np; 742 struct device *dev = &pdev->dev; 743 int ret; 744 745 dwc3_np = of_get_compatible_child(np, "snps,dwc3"); 746 if (!dwc3_np) { 747 dev_err(dev, "failed to find dwc3 core child\n"); 748 return -ENODEV; 749 } 750 751 ret = of_platform_populate(np, NULL, NULL, dev); 752 if (ret) { 753 dev_err(dev, "failed to register dwc3 core - %d\n", ret); 754 goto node_put; 755 } 756 757 qcom->dwc3 = of_find_device_by_node(dwc3_np); 758 if (!qcom->dwc3) { 759 ret = -ENODEV; 760 dev_err(dev, "failed to get dwc3 platform device\n"); 761 of_platform_depopulate(dev); 762 } 763 764node_put: 765 of_node_put(dwc3_np); 766 767 return ret; 768} 769 770static struct platform_device *dwc3_qcom_create_urs_usb_platdev(struct device *dev) 771{ 772 struct platform_device *urs_usb = NULL; 773 struct fwnode_handle *fwh; 774 struct acpi_device *adev; 775 char name[8]; 776 int ret; 777 int id; 778 779 /* Figure out device id */ 780 ret = sscanf(fwnode_get_name(dev->fwnode), "URS%d", &id); 781 if (!ret) 782 return NULL; 783 784 /* Find the child using name */ 785 snprintf(name, sizeof(name), "USB%d", id); 786 fwh = fwnode_get_named_child_node(dev->fwnode, name); 787 if (!fwh) 788 return NULL; 789 790 adev = to_acpi_device_node(fwh); 791 if (!adev) 792 goto err_put_handle; 793 794 urs_usb = acpi_create_platform_device(adev, NULL); 795 if (IS_ERR_OR_NULL(urs_usb)) 796 goto err_put_handle; 797 798 return urs_usb; 799 800err_put_handle: 801 fwnode_handle_put(fwh); 802 803 return urs_usb; 804} 805 806static void dwc3_qcom_destroy_urs_usb_platdev(struct platform_device *urs_usb) 807{ 808 struct fwnode_handle *fwh = urs_usb->dev.fwnode; 809 810 platform_device_unregister(urs_usb); 811 fwnode_handle_put(fwh); 812} 813 814static int dwc3_qcom_probe(struct platform_device *pdev) 815{ 816 struct device_node *np = pdev->dev.of_node; 817 struct device *dev = &pdev->dev; 818 struct dwc3_qcom *qcom; 819 struct resource *res, *parent_res = NULL; 820 struct resource local_res; 821 int ret, i; 822 bool ignore_pipe_clk; 823 bool wakeup_source; 824 825 qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL); 826 if (!qcom) 827 return -ENOMEM; 828 829 platform_set_drvdata(pdev, qcom); 830 qcom->dev = &pdev->dev; 831 832 if (has_acpi_companion(dev)) { 833 qcom->acpi_pdata = acpi_device_get_match_data(dev); 834 if (!qcom->acpi_pdata) { 835 dev_err(&pdev->dev, "no supporting ACPI device data\n"); 836 return -EINVAL; 837 } 838 } 839 840 qcom->resets = devm_reset_control_array_get_optional_exclusive(dev); 841 if (IS_ERR(qcom->resets)) { 842 return dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets), 843 "failed to get resets\n"); 844 } 845 846 ret = reset_control_assert(qcom->resets); 847 if (ret) { 848 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret); 849 return ret; 850 } 851 852 usleep_range(10, 1000); 853 854 ret = reset_control_deassert(qcom->resets); 855 if (ret) { 856 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret); 857 goto reset_assert; 858 } 859 860 ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np)); 861 if (ret) { 862 dev_err_probe(dev, ret, "failed to get clocks\n"); 863 goto reset_assert; 864 } 865 866 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 867 868 if (np) { 869 parent_res = res; 870 } else { 871 memcpy(&local_res, res, sizeof(struct resource)); 872 parent_res = &local_res; 873 874 parent_res->start = res->start + 875 qcom->acpi_pdata->qscratch_base_offset; 876 parent_res->end = parent_res->start + 877 qcom->acpi_pdata->qscratch_base_size; 878 879 if (qcom->acpi_pdata->is_urs) { 880 qcom->urs_usb = dwc3_qcom_create_urs_usb_platdev(dev); 881 if (IS_ERR_OR_NULL(qcom->urs_usb)) { 882 dev_err(dev, "failed to create URS USB platdev\n"); 883 if (!qcom->urs_usb) 884 ret = -ENODEV; 885 else 886 ret = PTR_ERR(qcom->urs_usb); 887 goto clk_disable; 888 } 889 } 890 } 891 892 qcom->qscratch_base = devm_ioremap_resource(dev, parent_res); 893 if (IS_ERR(qcom->qscratch_base)) { 894 ret = PTR_ERR(qcom->qscratch_base); 895 goto free_urs; 896 } 897 898 ret = dwc3_qcom_setup_irq(pdev); 899 if (ret) { 900 dev_err(dev, "failed to setup IRQs, err=%d\n", ret); 901 goto free_urs; 902 } 903 904 /* 905 * Disable pipe_clk requirement if specified. Used when dwc3 906 * operates without SSPHY and only HS/FS/LS modes are supported. 907 */ 908 ignore_pipe_clk = device_property_read_bool(dev, 909 "qcom,select-utmi-as-pipe-clk"); 910 if (ignore_pipe_clk) 911 dwc3_qcom_select_utmi_clk(qcom); 912 913 if (np) 914 ret = dwc3_qcom_of_register_core(pdev); 915 else 916 ret = dwc3_qcom_acpi_register_core(pdev); 917 918 if (ret) { 919 dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret); 920 goto free_urs; 921 } 922 923 ret = dwc3_qcom_interconnect_init(qcom); 924 if (ret) 925 goto depopulate; 926 927 qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev); 928 929 /* enable vbus override for device mode */ 930 if (qcom->mode != USB_DR_MODE_HOST) 931 dwc3_qcom_vbus_override_enable(qcom, true); 932 933 /* register extcon to override sw_vbus on Vbus change later */ 934 ret = dwc3_qcom_register_extcon(qcom); 935 if (ret) 936 goto interconnect_exit; 937 938 wakeup_source = of_property_read_bool(dev->of_node, "wakeup-source"); 939 device_init_wakeup(&pdev->dev, wakeup_source); 940 device_init_wakeup(&qcom->dwc3->dev, wakeup_source); 941 942 qcom->is_suspended = false; 943 pm_runtime_set_active(dev); 944 pm_runtime_enable(dev); 945 pm_runtime_forbid(dev); 946 947 return 0; 948 949interconnect_exit: 950 dwc3_qcom_interconnect_exit(qcom); 951depopulate: 952 if (np) { 953 of_platform_depopulate(&pdev->dev); 954 } else { 955 device_remove_software_node(&qcom->dwc3->dev); 956 platform_device_del(qcom->dwc3); 957 } 958 platform_device_put(qcom->dwc3); 959free_urs: 960 if (qcom->urs_usb) 961 dwc3_qcom_destroy_urs_usb_platdev(qcom->urs_usb); 962clk_disable: 963 for (i = qcom->num_clocks - 1; i >= 0; i--) { 964 clk_disable_unprepare(qcom->clks[i]); 965 clk_put(qcom->clks[i]); 966 } 967reset_assert: 968 reset_control_assert(qcom->resets); 969 970 return ret; 971} 972 973static void dwc3_qcom_remove(struct platform_device *pdev) 974{ 975 struct dwc3_qcom *qcom = platform_get_drvdata(pdev); 976 struct device_node *np = pdev->dev.of_node; 977 struct device *dev = &pdev->dev; 978 int i; 979 980 if (np) { 981 of_platform_depopulate(&pdev->dev); 982 } else { 983 device_remove_software_node(&qcom->dwc3->dev); 984 platform_device_del(qcom->dwc3); 985 } 986 platform_device_put(qcom->dwc3); 987 988 if (qcom->urs_usb) 989 dwc3_qcom_destroy_urs_usb_platdev(qcom->urs_usb); 990 991 for (i = qcom->num_clocks - 1; i >= 0; i--) { 992 clk_disable_unprepare(qcom->clks[i]); 993 clk_put(qcom->clks[i]); 994 } 995 qcom->num_clocks = 0; 996 997 dwc3_qcom_interconnect_exit(qcom); 998 reset_control_assert(qcom->resets); 999 1000 pm_runtime_allow(dev); 1001 pm_runtime_disable(dev); 1002} 1003 1004static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev) 1005{ 1006 struct dwc3_qcom *qcom = dev_get_drvdata(dev); 1007 bool wakeup = device_may_wakeup(dev); 1008 int ret; 1009 1010 ret = dwc3_qcom_suspend(qcom, wakeup); 1011 if (ret) 1012 return ret; 1013 1014 qcom->pm_suspended = true; 1015 1016 return 0; 1017} 1018 1019static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev) 1020{ 1021 struct dwc3_qcom *qcom = dev_get_drvdata(dev); 1022 bool wakeup = device_may_wakeup(dev); 1023 int ret; 1024 1025 ret = dwc3_qcom_resume(qcom, wakeup); 1026 if (ret) 1027 return ret; 1028 1029 qcom->pm_suspended = false; 1030 1031 return 0; 1032} 1033 1034static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev) 1035{ 1036 struct dwc3_qcom *qcom = dev_get_drvdata(dev); 1037 1038 return dwc3_qcom_suspend(qcom, true); 1039} 1040 1041static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev) 1042{ 1043 struct dwc3_qcom *qcom = dev_get_drvdata(dev); 1044 1045 return dwc3_qcom_resume(qcom, true); 1046} 1047 1048static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = { 1049 SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume) 1050 SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume, 1051 NULL) 1052}; 1053 1054static const struct of_device_id dwc3_qcom_of_match[] = { 1055 { .compatible = "qcom,dwc3" }, 1056 { } 1057}; 1058MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match); 1059 1060#ifdef CONFIG_ACPI 1061static const struct dwc3_acpi_pdata sdm845_acpi_pdata = { 1062 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET, 1063 .qscratch_base_size = SDM845_QSCRATCH_SIZE, 1064 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE, 1065 .hs_phy_irq_index = 1, 1066 .dp_hs_phy_irq_index = 4, 1067 .dm_hs_phy_irq_index = 3, 1068 .ss_phy_irq_index = 2 1069}; 1070 1071static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = { 1072 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET, 1073 .qscratch_base_size = SDM845_QSCRATCH_SIZE, 1074 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE, 1075 .hs_phy_irq_index = 1, 1076 .dp_hs_phy_irq_index = 4, 1077 .dm_hs_phy_irq_index = 3, 1078 .ss_phy_irq_index = 2, 1079 .is_urs = true, 1080}; 1081 1082static const struct acpi_device_id dwc3_qcom_acpi_match[] = { 1083 { "QCOM2430", (unsigned long)&sdm845_acpi_pdata }, 1084 { "QCOM0304", (unsigned long)&sdm845_acpi_urs_pdata }, 1085 { "QCOM0497", (unsigned long)&sdm845_acpi_urs_pdata }, 1086 { "QCOM04A6", (unsigned long)&sdm845_acpi_pdata }, 1087 { }, 1088}; 1089MODULE_DEVICE_TABLE(acpi, dwc3_qcom_acpi_match); 1090#endif 1091 1092static struct platform_driver dwc3_qcom_driver = { 1093 .probe = dwc3_qcom_probe, 1094 .remove_new = dwc3_qcom_remove, 1095 .driver = { 1096 .name = "dwc3-qcom", 1097 .pm = &dwc3_qcom_dev_pm_ops, 1098 .of_match_table = dwc3_qcom_of_match, 1099 .acpi_match_table = ACPI_PTR(dwc3_qcom_acpi_match), 1100 }, 1101}; 1102 1103module_platform_driver(dwc3_qcom_driver); 1104 1105MODULE_LICENSE("GPL v2"); 1106MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver"); 1107