1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * core.c - DesignWare HS OTG Controller common routines 4 * 5 * Copyright (C) 2004-2013 Synopsys, Inc. 6 */ 7 8/* 9 * The Core code provides basic services for accessing and managing the 10 * DWC_otg hardware. These services are used by both the Host Controller 11 * Driver and the Peripheral Controller Driver. 12 */ 13#include <linux/kernel.h> 14#include <linux/module.h> 15#include <linux/moduleparam.h> 16#include <linux/spinlock.h> 17#include <linux/interrupt.h> 18#include <linux/dma-mapping.h> 19#include <linux/delay.h> 20#include <linux/io.h> 21#include <linux/slab.h> 22#include <linux/usb.h> 23 24#include <linux/usb/hcd.h> 25#include <linux/usb/ch11.h> 26 27#include "core.h" 28#include "hcd.h" 29 30/** 31 * dwc2_backup_global_registers() - Backup global controller registers. 32 * When suspending usb bus, registers needs to be backuped 33 * if controller power is disabled once suspended. 34 * 35 * @hsotg: Programming view of the DWC_otg controller 36 */ 37int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg) 38{ 39 struct dwc2_gregs_backup *gr; 40 41 dev_dbg(hsotg->dev, "%s\n", __func__); 42 43 /* Backup global regs */ 44 gr = &hsotg->gr_backup; 45 46 gr->gotgctl = dwc2_readl(hsotg, GOTGCTL); 47 gr->gintmsk = dwc2_readl(hsotg, GINTMSK); 48 gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG); 49 gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG); 50 gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ); 51 gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); 52 gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG); 53 gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1); 54 gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG); 55 gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL); 56 gr->pcgcctl = dwc2_readl(hsotg, PCGCTL); 57 58 gr->valid = true; 59 return 0; 60} 61 62/** 63 * dwc2_restore_global_registers() - Restore controller global registers. 64 * When resuming usb bus, device registers needs to be restored 65 * if controller power were disabled. 66 * 67 * @hsotg: Programming view of the DWC_otg controller 68 */ 69int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg) 70{ 71 struct dwc2_gregs_backup *gr; 72 73 dev_dbg(hsotg->dev, "%s\n", __func__); 74 75 /* Restore global regs */ 76 gr = &hsotg->gr_backup; 77 if (!gr->valid) { 78 dev_err(hsotg->dev, "%s: no global registers to restore\n", 79 __func__); 80 return -EINVAL; 81 } 82 gr->valid = false; 83 84 dwc2_writel(hsotg, 0xffffffff, GINTSTS); 85 dwc2_writel(hsotg, gr->gotgctl, GOTGCTL); 86 dwc2_writel(hsotg, gr->gintmsk, GINTMSK); 87 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); 88 dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG); 89 dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ); 90 dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ); 91 dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG); 92 dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1); 93 dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG); 94 dwc2_writel(hsotg, gr->pcgcctl, PCGCTL); 95 dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL); 96 97 return 0; 98} 99 100/** 101 * dwc2_exit_partial_power_down() - Exit controller from Partial Power Down. 102 * 103 * @hsotg: Programming view of the DWC_otg controller 104 * @rem_wakeup: indicates whether resume is initiated by Reset. 105 * @restore: Controller registers need to be restored 106 */ 107int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup, 108 bool restore) 109{ 110 struct dwc2_gregs_backup *gr; 111 112 gr = &hsotg->gr_backup; 113 114 /* 115 * Restore host or device regisers with the same mode core enterted 116 * to partial power down by checking "GOTGCTL_CURMODE_HOST" backup 117 * value of the "gotgctl" register. 118 */ 119 if (gr->gotgctl & GOTGCTL_CURMODE_HOST) 120 return dwc2_host_exit_partial_power_down(hsotg, rem_wakeup, 121 restore); 122 else 123 return dwc2_gadget_exit_partial_power_down(hsotg, restore); 124} 125 126/** 127 * dwc2_enter_partial_power_down() - Put controller in Partial Power Down. 128 * 129 * @hsotg: Programming view of the DWC_otg controller 130 */ 131int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg) 132{ 133 if (dwc2_is_host_mode(hsotg)) 134 return dwc2_host_enter_partial_power_down(hsotg); 135 else 136 return dwc2_gadget_enter_partial_power_down(hsotg); 137} 138 139/** 140 * dwc2_restore_essential_regs() - Restore essiential regs of core. 141 * 142 * @hsotg: Programming view of the DWC_otg controller 143 * @rmode: Restore mode, enabled in case of remote-wakeup. 144 * @is_host: Host or device mode. 145 */ 146static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode, 147 int is_host) 148{ 149 u32 pcgcctl; 150 struct dwc2_gregs_backup *gr; 151 struct dwc2_dregs_backup *dr; 152 struct dwc2_hregs_backup *hr; 153 154 gr = &hsotg->gr_backup; 155 dr = &hsotg->dr_backup; 156 hr = &hsotg->hr_backup; 157 158 dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__); 159 160 /* Load restore values for [31:14] bits */ 161 pcgcctl = (gr->pcgcctl & 0xffffc000); 162 /* If High Speed */ 163 if (is_host) { 164 if (!(pcgcctl & PCGCTL_P2HD_PRT_SPD_MASK)) 165 pcgcctl |= BIT(17); 166 } else { 167 if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK)) 168 pcgcctl |= BIT(17); 169 } 170 dwc2_writel(hsotg, pcgcctl, PCGCTL); 171 172 /* Umnask global Interrupt in GAHBCFG and restore it */ 173 dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG); 174 175 /* Clear all pending interupts */ 176 dwc2_writel(hsotg, 0xffffffff, GINTSTS); 177 178 /* Unmask restore done interrupt */ 179 dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTMSK); 180 181 /* Restore GUSBCFG and HCFG/DCFG */ 182 dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); 183 184 if (is_host) { 185 dwc2_writel(hsotg, hr->hcfg, HCFG); 186 if (rmode) 187 pcgcctl |= PCGCTL_RESTOREMODE; 188 dwc2_writel(hsotg, pcgcctl, PCGCTL); 189 udelay(10); 190 191 pcgcctl |= PCGCTL_ESS_REG_RESTORED; 192 dwc2_writel(hsotg, pcgcctl, PCGCTL); 193 udelay(10); 194 } else { 195 dwc2_writel(hsotg, dr->dcfg, DCFG); 196 if (!rmode) 197 pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE; 198 dwc2_writel(hsotg, pcgcctl, PCGCTL); 199 udelay(10); 200 201 pcgcctl |= PCGCTL_ESS_REG_RESTORED; 202 dwc2_writel(hsotg, pcgcctl, PCGCTL); 203 udelay(10); 204 } 205} 206 207/** 208 * dwc2_hib_restore_common() - Common part of restore routine. 209 * 210 * @hsotg: Programming view of the DWC_otg controller 211 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup. 212 * @is_host: Host or device mode. 213 */ 214void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup, 215 int is_host) 216{ 217 u32 gpwrdn; 218 219 /* Switch-on voltage to the core */ 220 gpwrdn = dwc2_readl(hsotg, GPWRDN); 221 gpwrdn &= ~GPWRDN_PWRDNSWTCH; 222 dwc2_writel(hsotg, gpwrdn, GPWRDN); 223 udelay(10); 224 225 /* Reset core */ 226 gpwrdn = dwc2_readl(hsotg, GPWRDN); 227 gpwrdn &= ~GPWRDN_PWRDNRSTN; 228 dwc2_writel(hsotg, gpwrdn, GPWRDN); 229 udelay(10); 230 231 /* Enable restore from PMU */ 232 gpwrdn = dwc2_readl(hsotg, GPWRDN); 233 gpwrdn |= GPWRDN_RESTORE; 234 dwc2_writel(hsotg, gpwrdn, GPWRDN); 235 udelay(10); 236 237 /* Disable Power Down Clamp */ 238 gpwrdn = dwc2_readl(hsotg, GPWRDN); 239 gpwrdn &= ~GPWRDN_PWRDNCLMP; 240 dwc2_writel(hsotg, gpwrdn, GPWRDN); 241 udelay(50); 242 243 if (!is_host && rem_wakeup) 244 udelay(70); 245 246 /* Deassert reset core */ 247 gpwrdn = dwc2_readl(hsotg, GPWRDN); 248 gpwrdn |= GPWRDN_PWRDNRSTN; 249 dwc2_writel(hsotg, gpwrdn, GPWRDN); 250 udelay(10); 251 252 /* Disable PMU interrupt */ 253 gpwrdn = dwc2_readl(hsotg, GPWRDN); 254 gpwrdn &= ~GPWRDN_PMUINTSEL; 255 dwc2_writel(hsotg, gpwrdn, GPWRDN); 256 udelay(10); 257 258 /* Set Restore Essential Regs bit in PCGCCTL register */ 259 dwc2_restore_essential_regs(hsotg, rem_wakeup, is_host); 260 261 /* 262 * Wait For Restore_done Interrupt. This mechanism of polling the 263 * interrupt is introduced to avoid any possible race conditions 264 */ 265 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_RESTOREDONE, 266 20000)) { 267 dev_dbg(hsotg->dev, 268 "%s: Restore Done wasn't generated here\n", 269 __func__); 270 } else { 271 dev_dbg(hsotg->dev, "restore done generated here\n"); 272 273 /* 274 * To avoid restore done interrupt storm after restore is 275 * generated clear GINTSTS_RESTOREDONE bit. 276 */ 277 dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTSTS); 278 } 279} 280 281/** 282 * dwc2_wait_for_mode() - Waits for the controller mode. 283 * @hsotg: Programming view of the DWC_otg controller. 284 * @host_mode: If true, waits for host mode, otherwise device mode. 285 */ 286static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg, 287 bool host_mode) 288{ 289 ktime_t start; 290 ktime_t end; 291 unsigned int timeout = 110; 292 293 dev_vdbg(hsotg->dev, "Waiting for %s mode\n", 294 host_mode ? "host" : "device"); 295 296 start = ktime_get(); 297 298 while (1) { 299 s64 ms; 300 301 if (dwc2_is_host_mode(hsotg) == host_mode) { 302 dev_vdbg(hsotg->dev, "%s mode set\n", 303 host_mode ? "Host" : "Device"); 304 break; 305 } 306 307 end = ktime_get(); 308 ms = ktime_to_ms(ktime_sub(end, start)); 309 310 if (ms >= (s64)timeout) { 311 dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n", 312 __func__, host_mode ? "host" : "device"); 313 break; 314 } 315 316 usleep_range(1000, 2000); 317 } 318} 319 320/** 321 * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce 322 * filter is enabled. 323 * 324 * @hsotg: Programming view of DWC_otg controller 325 */ 326static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg) 327{ 328 u32 gsnpsid; 329 u32 ghwcfg4; 330 331 if (!dwc2_hw_is_otg(hsotg)) 332 return false; 333 334 /* Check if core configuration includes the IDDIG filter. */ 335 ghwcfg4 = dwc2_readl(hsotg, GHWCFG4); 336 if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN)) 337 return false; 338 339 /* 340 * Check if the IDDIG debounce filter is bypassed. Available 341 * in core version >= 3.10a. 342 */ 343 gsnpsid = dwc2_readl(hsotg, GSNPSID); 344 if (gsnpsid >= DWC2_CORE_REV_3_10a) { 345 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL); 346 347 if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS) 348 return false; 349 } 350 351 return true; 352} 353 354/* 355 * dwc2_enter_hibernation() - Common function to enter hibernation. 356 * 357 * @hsotg: Programming view of the DWC_otg controller 358 * @is_host: True if core is in host mode. 359 * 360 * Return: 0 if successful, negative error code otherwise 361 */ 362int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host) 363{ 364 if (is_host) 365 return dwc2_host_enter_hibernation(hsotg); 366 else 367 return dwc2_gadget_enter_hibernation(hsotg); 368} 369 370/* 371 * dwc2_exit_hibernation() - Common function to exit from hibernation. 372 * 373 * @hsotg: Programming view of the DWC_otg controller 374 * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup. 375 * @reset: Enabled in case of restore with reset. 376 * @is_host: True if core is in host mode. 377 * 378 * Return: 0 if successful, negative error code otherwise 379 */ 380int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, 381 int reset, int is_host) 382{ 383 if (is_host) 384 return dwc2_host_exit_hibernation(hsotg, rem_wakeup, reset); 385 else 386 return dwc2_gadget_exit_hibernation(hsotg, rem_wakeup, reset); 387} 388 389/* 390 * Do core a soft reset of the core. Be careful with this because it 391 * resets all the internal state machines of the core. 392 */ 393int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait) 394{ 395 u32 greset; 396 bool wait_for_host_mode = false; 397 398 dev_vdbg(hsotg->dev, "%s()\n", __func__); 399 400 /* 401 * If the current mode is host, either due to the force mode 402 * bit being set (which persists after core reset) or the 403 * connector id pin, a core soft reset will temporarily reset 404 * the mode to device. A delay from the IDDIG debounce filter 405 * will occur before going back to host mode. 406 * 407 * Determine whether we will go back into host mode after a 408 * reset and account for this delay after the reset. 409 */ 410 if (dwc2_iddig_filter_enabled(hsotg)) { 411 u32 gotgctl = dwc2_readl(hsotg, GOTGCTL); 412 u32 gusbcfg = dwc2_readl(hsotg, GUSBCFG); 413 414 if (!(gotgctl & GOTGCTL_CONID_B) || 415 (gusbcfg & GUSBCFG_FORCEHOSTMODE)) { 416 wait_for_host_mode = true; 417 } 418 } 419 420 /* Core Soft Reset */ 421 greset = dwc2_readl(hsotg, GRSTCTL); 422 greset |= GRSTCTL_CSFTRST; 423 dwc2_writel(hsotg, greset, GRSTCTL); 424 425 if ((hsotg->hw_params.snpsid & DWC2_CORE_REV_MASK) < 426 (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) { 427 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, 428 GRSTCTL_CSFTRST, 10000)) { 429 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST\n", 430 __func__); 431 return -EBUSY; 432 } 433 } else { 434 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, 435 GRSTCTL_CSFTRST_DONE, 10000)) { 436 dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST_DONE\n", 437 __func__); 438 return -EBUSY; 439 } 440 greset = dwc2_readl(hsotg, GRSTCTL); 441 greset &= ~GRSTCTL_CSFTRST; 442 greset |= GRSTCTL_CSFTRST_DONE; 443 dwc2_writel(hsotg, greset, GRSTCTL); 444 } 445 446 /* 447 * Switching from device mode to host mode by disconnecting 448 * device cable core enters and exits form hibernation. 449 * However, the fifo map remains not cleared. It results 450 * to a WARNING (WARNING: CPU: 5 PID: 0 at drivers/usb/dwc2/ 451 * gadget.c:307 dwc2_hsotg_init_fifo+0x12/0x152 [dwc2]) 452 * if in host mode we disconnect the micro a to b host 453 * cable. Because core reset occurs. 454 * To avoid the WARNING, fifo_map should be cleared 455 * in dwc2_core_reset() function by taking into account configs. 456 * fifo_map must be cleared only if driver is configured in 457 * "CONFIG_USB_DWC2_PERIPHERAL" or "CONFIG_USB_DWC2_DUAL_ROLE" 458 * mode. 459 */ 460 dwc2_clear_fifo_map(hsotg); 461 462 /* Wait for AHB master IDLE state */ 463 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) { 464 dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n", 465 __func__); 466 return -EBUSY; 467 } 468 469 if (wait_for_host_mode && !skip_wait) 470 dwc2_wait_for_mode(hsotg, true); 471 472 return 0; 473} 474 475/** 476 * dwc2_force_mode() - Force the mode of the controller. 477 * 478 * Forcing the mode is needed for two cases: 479 * 480 * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the 481 * controller to stay in a particular mode regardless of ID pin 482 * changes. We do this once during probe. 483 * 484 * 2) During probe we want to read reset values of the hw 485 * configuration registers that are only available in either host or 486 * device mode. We may need to force the mode if the current mode does 487 * not allow us to access the register in the mode that we want. 488 * 489 * In either case it only makes sense to force the mode if the 490 * controller hardware is OTG capable. 491 * 492 * Checks are done in this function to determine whether doing a force 493 * would be valid or not. 494 * 495 * If a force is done, it requires a IDDIG debounce filter delay if 496 * the filter is configured and enabled. We poll the current mode of 497 * the controller to account for this delay. 498 * 499 * @hsotg: Programming view of DWC_otg controller 500 * @host: Host mode flag 501 */ 502void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host) 503{ 504 u32 gusbcfg; 505 u32 set; 506 u32 clear; 507 508 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device"); 509 510 /* 511 * Force mode has no effect if the hardware is not OTG. 512 */ 513 if (!dwc2_hw_is_otg(hsotg)) 514 return; 515 516 /* 517 * If dr_mode is either peripheral or host only, there is no 518 * need to ever force the mode to the opposite mode. 519 */ 520 if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)) 521 return; 522 523 if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST)) 524 return; 525 526 gusbcfg = dwc2_readl(hsotg, GUSBCFG); 527 528 set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE; 529 clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE; 530 531 gusbcfg &= ~clear; 532 gusbcfg |= set; 533 dwc2_writel(hsotg, gusbcfg, GUSBCFG); 534 535 dwc2_wait_for_mode(hsotg, host); 536 return; 537} 538 539/** 540 * dwc2_clear_force_mode() - Clears the force mode bits. 541 * 542 * After clearing the bits, wait up to 100 ms to account for any 543 * potential IDDIG filter delay. We can't know if we expect this delay 544 * or not because the value of the connector ID status is affected by 545 * the force mode. We only need to call this once during probe if 546 * dr_mode == OTG. 547 * 548 * @hsotg: Programming view of DWC_otg controller 549 */ 550static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg) 551{ 552 u32 gusbcfg; 553 554 if (!dwc2_hw_is_otg(hsotg)) 555 return; 556 557 dev_dbg(hsotg->dev, "Clearing force mode bits\n"); 558 559 gusbcfg = dwc2_readl(hsotg, GUSBCFG); 560 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; 561 gusbcfg &= ~GUSBCFG_FORCEDEVMODE; 562 dwc2_writel(hsotg, gusbcfg, GUSBCFG); 563 564 if (dwc2_iddig_filter_enabled(hsotg)) 565 msleep(100); 566} 567 568/* 569 * Sets or clears force mode based on the dr_mode parameter. 570 */ 571void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg) 572{ 573 switch (hsotg->dr_mode) { 574 case USB_DR_MODE_HOST: 575 /* 576 * NOTE: This is required for some rockchip soc based 577 * platforms on their host-only dwc2. 578 */ 579 if (!dwc2_hw_is_otg(hsotg)) 580 msleep(50); 581 582 break; 583 case USB_DR_MODE_PERIPHERAL: 584 dwc2_force_mode(hsotg, false); 585 break; 586 case USB_DR_MODE_OTG: 587 dwc2_clear_force_mode(hsotg); 588 break; 589 default: 590 dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n", 591 __func__, hsotg->dr_mode); 592 break; 593 } 594} 595 596/* 597 * dwc2_enable_acg - enable active clock gating feature 598 */ 599void dwc2_enable_acg(struct dwc2_hsotg *hsotg) 600{ 601 if (hsotg->params.acg_enable) { 602 u32 pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1); 603 604 dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n"); 605 pcgcctl1 |= PCGCCTL1_GATEEN; 606 dwc2_writel(hsotg, pcgcctl1, PCGCCTL1); 607 } 608} 609 610/** 611 * dwc2_dump_host_registers() - Prints the host registers 612 * 613 * @hsotg: Programming view of DWC_otg controller 614 * 615 * NOTE: This function will be removed once the peripheral controller code 616 * is integrated and the driver is stable 617 */ 618void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg) 619{ 620#ifdef DEBUG 621 u32 __iomem *addr; 622 int i; 623 624 dev_dbg(hsotg->dev, "Host Global Registers\n"); 625 addr = hsotg->regs + HCFG; 626 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", 627 (unsigned long)addr, dwc2_readl(hsotg, HCFG)); 628 addr = hsotg->regs + HFIR; 629 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", 630 (unsigned long)addr, dwc2_readl(hsotg, HFIR)); 631 addr = hsotg->regs + HFNUM; 632 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", 633 (unsigned long)addr, dwc2_readl(hsotg, HFNUM)); 634 addr = hsotg->regs + HPTXSTS; 635 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", 636 (unsigned long)addr, dwc2_readl(hsotg, HPTXSTS)); 637 addr = hsotg->regs + HAINT; 638 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", 639 (unsigned long)addr, dwc2_readl(hsotg, HAINT)); 640 addr = hsotg->regs + HAINTMSK; 641 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", 642 (unsigned long)addr, dwc2_readl(hsotg, HAINTMSK)); 643 if (hsotg->params.dma_desc_enable) { 644 addr = hsotg->regs + HFLBADDR; 645 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", 646 (unsigned long)addr, dwc2_readl(hsotg, HFLBADDR)); 647 } 648 649 addr = hsotg->regs + HPRT0; 650 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", 651 (unsigned long)addr, dwc2_readl(hsotg, HPRT0)); 652 653 for (i = 0; i < hsotg->params.host_channels; i++) { 654 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); 655 addr = hsotg->regs + HCCHAR(i); 656 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", 657 (unsigned long)addr, dwc2_readl(hsotg, HCCHAR(i))); 658 addr = hsotg->regs + HCSPLT(i); 659 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", 660 (unsigned long)addr, dwc2_readl(hsotg, HCSPLT(i))); 661 addr = hsotg->regs + HCINT(i); 662 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", 663 (unsigned long)addr, dwc2_readl(hsotg, HCINT(i))); 664 addr = hsotg->regs + HCINTMSK(i); 665 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", 666 (unsigned long)addr, dwc2_readl(hsotg, HCINTMSK(i))); 667 addr = hsotg->regs + HCTSIZ(i); 668 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", 669 (unsigned long)addr, dwc2_readl(hsotg, HCTSIZ(i))); 670 addr = hsotg->regs + HCDMA(i); 671 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", 672 (unsigned long)addr, dwc2_readl(hsotg, HCDMA(i))); 673 if (hsotg->params.dma_desc_enable) { 674 addr = hsotg->regs + HCDMAB(i); 675 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", 676 (unsigned long)addr, dwc2_readl(hsotg, 677 HCDMAB(i))); 678 } 679 } 680#endif 681} 682 683/** 684 * dwc2_dump_global_registers() - Prints the core global registers 685 * 686 * @hsotg: Programming view of DWC_otg controller 687 * 688 * NOTE: This function will be removed once the peripheral controller code 689 * is integrated and the driver is stable 690 */ 691void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg) 692{ 693#ifdef DEBUG 694 u32 __iomem *addr; 695 696 dev_dbg(hsotg->dev, "Core Global Registers\n"); 697 addr = hsotg->regs + GOTGCTL; 698 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", 699 (unsigned long)addr, dwc2_readl(hsotg, GOTGCTL)); 700 addr = hsotg->regs + GOTGINT; 701 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", 702 (unsigned long)addr, dwc2_readl(hsotg, GOTGINT)); 703 addr = hsotg->regs + GAHBCFG; 704 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", 705 (unsigned long)addr, dwc2_readl(hsotg, GAHBCFG)); 706 addr = hsotg->regs + GUSBCFG; 707 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", 708 (unsigned long)addr, dwc2_readl(hsotg, GUSBCFG)); 709 addr = hsotg->regs + GRSTCTL; 710 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", 711 (unsigned long)addr, dwc2_readl(hsotg, GRSTCTL)); 712 addr = hsotg->regs + GINTSTS; 713 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", 714 (unsigned long)addr, dwc2_readl(hsotg, GINTSTS)); 715 addr = hsotg->regs + GINTMSK; 716 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", 717 (unsigned long)addr, dwc2_readl(hsotg, GINTMSK)); 718 addr = hsotg->regs + GRXSTSR; 719 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", 720 (unsigned long)addr, dwc2_readl(hsotg, GRXSTSR)); 721 addr = hsotg->regs + GRXFSIZ; 722 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", 723 (unsigned long)addr, dwc2_readl(hsotg, GRXFSIZ)); 724 addr = hsotg->regs + GNPTXFSIZ; 725 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", 726 (unsigned long)addr, dwc2_readl(hsotg, GNPTXFSIZ)); 727 addr = hsotg->regs + GNPTXSTS; 728 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", 729 (unsigned long)addr, dwc2_readl(hsotg, GNPTXSTS)); 730 addr = hsotg->regs + GI2CCTL; 731 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", 732 (unsigned long)addr, dwc2_readl(hsotg, GI2CCTL)); 733 addr = hsotg->regs + GPVNDCTL; 734 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", 735 (unsigned long)addr, dwc2_readl(hsotg, GPVNDCTL)); 736 addr = hsotg->regs + GGPIO; 737 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", 738 (unsigned long)addr, dwc2_readl(hsotg, GGPIO)); 739 addr = hsotg->regs + GUID; 740 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", 741 (unsigned long)addr, dwc2_readl(hsotg, GUID)); 742 addr = hsotg->regs + GSNPSID; 743 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", 744 (unsigned long)addr, dwc2_readl(hsotg, GSNPSID)); 745 addr = hsotg->regs + GHWCFG1; 746 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", 747 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG1)); 748 addr = hsotg->regs + GHWCFG2; 749 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", 750 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG2)); 751 addr = hsotg->regs + GHWCFG3; 752 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", 753 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG3)); 754 addr = hsotg->regs + GHWCFG4; 755 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", 756 (unsigned long)addr, dwc2_readl(hsotg, GHWCFG4)); 757 addr = hsotg->regs + GLPMCFG; 758 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", 759 (unsigned long)addr, dwc2_readl(hsotg, GLPMCFG)); 760 addr = hsotg->regs + GPWRDN; 761 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", 762 (unsigned long)addr, dwc2_readl(hsotg, GPWRDN)); 763 addr = hsotg->regs + GDFIFOCFG; 764 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", 765 (unsigned long)addr, dwc2_readl(hsotg, GDFIFOCFG)); 766 addr = hsotg->regs + HPTXFSIZ; 767 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", 768 (unsigned long)addr, dwc2_readl(hsotg, HPTXFSIZ)); 769 770 addr = hsotg->regs + PCGCTL; 771 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", 772 (unsigned long)addr, dwc2_readl(hsotg, PCGCTL)); 773#endif 774} 775 776/** 777 * dwc2_flush_tx_fifo() - Flushes a Tx FIFO 778 * 779 * @hsotg: Programming view of DWC_otg controller 780 * @num: Tx FIFO to flush 781 */ 782void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num) 783{ 784 u32 greset; 785 786 dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num); 787 788 /* Wait for AHB master IDLE state */ 789 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) 790 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n", 791 __func__); 792 793 greset = GRSTCTL_TXFFLSH; 794 greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK; 795 dwc2_writel(hsotg, greset, GRSTCTL); 796 797 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000)) 798 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n", 799 __func__); 800 801 /* Wait for at least 3 PHY Clocks */ 802 udelay(1); 803} 804 805/** 806 * dwc2_flush_rx_fifo() - Flushes the Rx FIFO 807 * 808 * @hsotg: Programming view of DWC_otg controller 809 */ 810void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg) 811{ 812 u32 greset; 813 814 dev_vdbg(hsotg->dev, "%s()\n", __func__); 815 816 /* Wait for AHB master IDLE state */ 817 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) 818 dev_warn(hsotg->dev, "%s: HANG! AHB Idle GRSCTL\n", 819 __func__); 820 821 greset = GRSTCTL_RXFFLSH; 822 dwc2_writel(hsotg, greset, GRSTCTL); 823 824 /* Wait for RxFIFO flush done */ 825 if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000)) 826 dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_RXFFLSH\n", 827 __func__); 828 829 /* Wait for at least 3 PHY Clocks */ 830 udelay(1); 831} 832 833bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) 834{ 835 if (dwc2_readl(hsotg, GSNPSID) == 0xffffffff) 836 return false; 837 else 838 return true; 839} 840 841/** 842 * dwc2_enable_global_interrupts() - Enables the controller's Global 843 * Interrupt in the AHB Config register 844 * 845 * @hsotg: Programming view of DWC_otg controller 846 */ 847void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) 848{ 849 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG); 850 851 ahbcfg |= GAHBCFG_GLBL_INTR_EN; 852 dwc2_writel(hsotg, ahbcfg, GAHBCFG); 853} 854 855/** 856 * dwc2_disable_global_interrupts() - Disables the controller's Global 857 * Interrupt in the AHB Config register 858 * 859 * @hsotg: Programming view of DWC_otg controller 860 */ 861void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) 862{ 863 u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG); 864 865 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; 866 dwc2_writel(hsotg, ahbcfg, GAHBCFG); 867} 868 869/* Returns the controller's GHWCFG2.OTG_MODE. */ 870unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg) 871{ 872 u32 ghwcfg2 = dwc2_readl(hsotg, GHWCFG2); 873 874 return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >> 875 GHWCFG2_OP_MODE_SHIFT; 876} 877 878/* Returns true if the controller is capable of DRD. */ 879bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg) 880{ 881 unsigned int op_mode = dwc2_op_mode(hsotg); 882 883 return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) || 884 (op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) || 885 (op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE); 886} 887 888/* Returns true if the controller is host-only. */ 889bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg) 890{ 891 unsigned int op_mode = dwc2_op_mode(hsotg); 892 893 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) || 894 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST); 895} 896 897/* Returns true if the controller is device-only. */ 898bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg) 899{ 900 unsigned int op_mode = dwc2_op_mode(hsotg); 901 902 return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) || 903 (op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE); 904} 905 906/** 907 * dwc2_hsotg_wait_bit_set - Waits for bit to be set. 908 * @hsotg: Programming view of DWC_otg controller. 909 * @offset: Register's offset where bit/bits must be set. 910 * @mask: Mask of the bit/bits which must be set. 911 * @timeout: Timeout to wait. 912 * 913 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout. 914 */ 915int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask, 916 u32 timeout) 917{ 918 u32 i; 919 920 for (i = 0; i < timeout; i++) { 921 if (dwc2_readl(hsotg, offset) & mask) 922 return 0; 923 udelay(1); 924 } 925 926 return -ETIMEDOUT; 927} 928 929/** 930 * dwc2_hsotg_wait_bit_clear - Waits for bit to be clear. 931 * @hsotg: Programming view of DWC_otg controller. 932 * @offset: Register's offset where bit/bits must be set. 933 * @mask: Mask of the bit/bits which must be set. 934 * @timeout: Timeout to wait. 935 * 936 * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout. 937 */ 938int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask, 939 u32 timeout) 940{ 941 u32 i; 942 943 for (i = 0; i < timeout; i++) { 944 if (!(dwc2_readl(hsotg, offset) & mask)) 945 return 0; 946 udelay(1); 947 } 948 949 return -ETIMEDOUT; 950} 951 952/* 953 * Initializes the FSLSPClkSel field of the HCFG register depending on the 954 * PHY type 955 */ 956void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) 957{ 958 u32 hcfg, val; 959 960 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 961 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 962 hsotg->params.ulpi_fs_ls) || 963 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { 964 /* Full speed PHY */ 965 val = HCFG_FSLSPCLKSEL_48_MHZ; 966 } else { 967 /* High speed PHY running at full speed or high speed */ 968 val = HCFG_FSLSPCLKSEL_30_60_MHZ; 969 } 970 971 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); 972 hcfg = dwc2_readl(hsotg, HCFG); 973 hcfg &= ~HCFG_FSLSPCLKSEL_MASK; 974 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; 975 dwc2_writel(hsotg, hcfg, HCFG); 976} 977 978static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 979{ 980 u32 usbcfg, ggpio, i2cctl; 981 int retval = 0; 982 983 /* 984 * core_init() is now called on every switch so only call the 985 * following for the first time through 986 */ 987 if (select_phy) { 988 dev_dbg(hsotg->dev, "FS PHY selected\n"); 989 990 usbcfg = dwc2_readl(hsotg, GUSBCFG); 991 if (!(usbcfg & GUSBCFG_PHYSEL)) { 992 usbcfg |= GUSBCFG_PHYSEL; 993 dwc2_writel(hsotg, usbcfg, GUSBCFG); 994 995 /* Reset after a PHY select */ 996 retval = dwc2_core_reset(hsotg, false); 997 998 if (retval) { 999 dev_err(hsotg->dev, 1000 "%s: Reset failed, aborting", __func__); 1001 return retval; 1002 } 1003 } 1004 1005 if (hsotg->params.activate_stm_fs_transceiver) { 1006 ggpio = dwc2_readl(hsotg, GGPIO); 1007 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) { 1008 dev_dbg(hsotg->dev, "Activating transceiver\n"); 1009 /* 1010 * STM32F4x9 uses the GGPIO register as general 1011 * core configuration register. 1012 */ 1013 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN; 1014 dwc2_writel(hsotg, ggpio, GGPIO); 1015 } 1016 } 1017 } 1018 1019 /* 1020 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also 1021 * do this on HNP Dev/Host mode switches (done in dev_init and 1022 * host_init). 1023 */ 1024 if (dwc2_is_host_mode(hsotg)) 1025 dwc2_init_fs_ls_pclk_sel(hsotg); 1026 1027 if (hsotg->params.i2c_enable) { 1028 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); 1029 1030 /* Program GUSBCFG.OtgUtmiFsSel to I2C */ 1031 usbcfg = dwc2_readl(hsotg, GUSBCFG); 1032 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; 1033 dwc2_writel(hsotg, usbcfg, GUSBCFG); 1034 1035 /* Program GI2CCTL.I2CEn */ 1036 i2cctl = dwc2_readl(hsotg, GI2CCTL); 1037 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; 1038 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; 1039 i2cctl &= ~GI2CCTL_I2CEN; 1040 dwc2_writel(hsotg, i2cctl, GI2CCTL); 1041 i2cctl |= GI2CCTL_I2CEN; 1042 dwc2_writel(hsotg, i2cctl, GI2CCTL); 1043 } 1044 1045 return retval; 1046} 1047 1048static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 1049{ 1050 u32 usbcfg, usbcfg_old; 1051 int retval = 0; 1052 1053 if (!select_phy) 1054 return 0; 1055 1056 usbcfg = dwc2_readl(hsotg, GUSBCFG); 1057 usbcfg_old = usbcfg; 1058 1059 /* 1060 * HS PHY parameters. These parameters are preserved during soft reset 1061 * so only program the first time. Do a soft reset immediately after 1062 * setting phyif. 1063 */ 1064 switch (hsotg->params.phy_type) { 1065 case DWC2_PHY_TYPE_PARAM_ULPI: 1066 /* ULPI interface */ 1067 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); 1068 usbcfg |= GUSBCFG_ULPI_UTMI_SEL; 1069 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); 1070 if (hsotg->params.phy_ulpi_ddr) 1071 usbcfg |= GUSBCFG_DDRSEL; 1072 1073 /* Set external VBUS indicator as needed. */ 1074 if (hsotg->params.oc_disable) 1075 usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND | 1076 GUSBCFG_INDICATORPASSTHROUGH); 1077 break; 1078 case DWC2_PHY_TYPE_PARAM_UTMI: 1079 /* UTMI+ interface */ 1080 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); 1081 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); 1082 if (hsotg->params.phy_utmi_width == 16) 1083 usbcfg |= GUSBCFG_PHYIF16; 1084 break; 1085 default: 1086 dev_err(hsotg->dev, "FS PHY selected at HS!\n"); 1087 break; 1088 } 1089 1090 if (usbcfg != usbcfg_old) { 1091 dwc2_writel(hsotg, usbcfg, GUSBCFG); 1092 1093 /* Reset after setting the PHY parameters */ 1094 retval = dwc2_core_reset(hsotg, false); 1095 if (retval) { 1096 dev_err(hsotg->dev, 1097 "%s: Reset failed, aborting", __func__); 1098 return retval; 1099 } 1100 } 1101 1102 return retval; 1103} 1104 1105static void dwc2_set_turnaround_time(struct dwc2_hsotg *hsotg) 1106{ 1107 u32 usbcfg; 1108 1109 if (hsotg->params.phy_type != DWC2_PHY_TYPE_PARAM_UTMI) 1110 return; 1111 1112 usbcfg = dwc2_readl(hsotg, GUSBCFG); 1113 1114 usbcfg &= ~GUSBCFG_USBTRDTIM_MASK; 1115 if (hsotg->params.phy_utmi_width == 16) 1116 usbcfg |= 5 << GUSBCFG_USBTRDTIM_SHIFT; 1117 else 1118 usbcfg |= 9 << GUSBCFG_USBTRDTIM_SHIFT; 1119 1120 dwc2_writel(hsotg, usbcfg, GUSBCFG); 1121} 1122 1123int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) 1124{ 1125 u32 usbcfg; 1126 u32 otgctl; 1127 int retval = 0; 1128 1129 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL || 1130 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) && 1131 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) { 1132 /* If FS/LS mode with FS/LS PHY */ 1133 retval = dwc2_fs_phy_init(hsotg, select_phy); 1134 if (retval) 1135 return retval; 1136 } else { 1137 /* High speed PHY */ 1138 retval = dwc2_hs_phy_init(hsotg, select_phy); 1139 if (retval) 1140 return retval; 1141 1142 if (dwc2_is_device_mode(hsotg)) 1143 dwc2_set_turnaround_time(hsotg); 1144 } 1145 1146 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && 1147 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && 1148 hsotg->params.ulpi_fs_ls) { 1149 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); 1150 usbcfg = dwc2_readl(hsotg, GUSBCFG); 1151 usbcfg |= GUSBCFG_ULPI_FS_LS; 1152 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; 1153 dwc2_writel(hsotg, usbcfg, GUSBCFG); 1154 } else { 1155 usbcfg = dwc2_readl(hsotg, GUSBCFG); 1156 usbcfg &= ~GUSBCFG_ULPI_FS_LS; 1157 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; 1158 dwc2_writel(hsotg, usbcfg, GUSBCFG); 1159 } 1160 1161 if (!hsotg->params.activate_ingenic_overcurrent_detection) { 1162 if (dwc2_is_host_mode(hsotg)) { 1163 otgctl = readl(hsotg->regs + GOTGCTL); 1164 otgctl |= GOTGCTL_VBVALOEN | GOTGCTL_VBVALOVAL; 1165 writel(otgctl, hsotg->regs + GOTGCTL); 1166 } 1167 } 1168 1169 return retval; 1170} 1171 1172MODULE_DESCRIPTION("DESIGNWARE HS OTG Core"); 1173MODULE_AUTHOR("Synopsys, Inc."); 1174MODULE_LICENSE("Dual BSD/GPL"); 1175