1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2016, NVIDIA Corporation
4 */
5
6#include <linux/clk.h>
7#include <linux/io.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/platform_device.h>
11#include <linux/pm_runtime.h>
12#include <linux/reset.h>
13
14#include <linux/usb.h>
15#include <linux/usb/chipidea.h>
16#include <linux/usb/hcd.h>
17#include <linux/usb/of.h>
18#include <linux/usb/phy.h>
19
20#include <soc/tegra/common.h>
21
22#include "../host/ehci.h"
23
24#include "ci.h"
25
26struct tegra_usb {
27	struct ci_hdrc_platform_data data;
28	struct platform_device *dev;
29
30	const struct tegra_usb_soc_info *soc;
31	struct usb_phy *phy;
32	struct clk *clk;
33
34	bool needs_double_reset;
35};
36
37struct tegra_usb_soc_info {
38	unsigned long flags;
39	unsigned int txfifothresh;
40	enum usb_dr_mode dr_mode;
41};
42
43static const struct tegra_usb_soc_info tegra20_ehci_soc_info = {
44	.flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
45		 CI_HDRC_OVERRIDE_PHY_CONTROL |
46		 CI_HDRC_SUPPORTS_RUNTIME_PM,
47	.dr_mode = USB_DR_MODE_HOST,
48	.txfifothresh = 10,
49};
50
51static const struct tegra_usb_soc_info tegra30_ehci_soc_info = {
52	.flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
53		 CI_HDRC_OVERRIDE_PHY_CONTROL |
54		 CI_HDRC_SUPPORTS_RUNTIME_PM,
55	.dr_mode = USB_DR_MODE_HOST,
56	.txfifothresh = 16,
57};
58
59static const struct tegra_usb_soc_info tegra20_udc_soc_info = {
60	.flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
61		 CI_HDRC_OVERRIDE_PHY_CONTROL |
62		 CI_HDRC_SUPPORTS_RUNTIME_PM,
63	.dr_mode = USB_DR_MODE_UNKNOWN,
64	.txfifothresh = 10,
65};
66
67static const struct tegra_usb_soc_info tegra30_udc_soc_info = {
68	.flags = CI_HDRC_REQUIRES_ALIGNED_DMA |
69		 CI_HDRC_OVERRIDE_PHY_CONTROL |
70		 CI_HDRC_SUPPORTS_RUNTIME_PM,
71	.dr_mode = USB_DR_MODE_UNKNOWN,
72	.txfifothresh = 16,
73};
74
75static const struct of_device_id tegra_usb_of_match[] = {
76	{
77		.compatible = "nvidia,tegra20-ehci",
78		.data = &tegra20_ehci_soc_info,
79	}, {
80		.compatible = "nvidia,tegra30-ehci",
81		.data = &tegra30_ehci_soc_info,
82	}, {
83		.compatible = "nvidia,tegra20-udc",
84		.data = &tegra20_udc_soc_info,
85	}, {
86		.compatible = "nvidia,tegra30-udc",
87		.data = &tegra30_udc_soc_info,
88	}, {
89		.compatible = "nvidia,tegra114-udc",
90		.data = &tegra30_udc_soc_info,
91	}, {
92		.compatible = "nvidia,tegra124-udc",
93		.data = &tegra30_udc_soc_info,
94	}, {
95		/* sentinel */
96	}
97};
98MODULE_DEVICE_TABLE(of, tegra_usb_of_match);
99
100static int tegra_usb_reset_controller(struct device *dev)
101{
102	struct reset_control *rst, *rst_utmi;
103	struct device_node *phy_np;
104	int err;
105
106	rst = devm_reset_control_get_shared(dev, "usb");
107	if (IS_ERR(rst)) {
108		dev_err(dev, "can't get ehci reset: %pe\n", rst);
109		return PTR_ERR(rst);
110	}
111
112	phy_np = of_parse_phandle(dev->of_node, "nvidia,phy", 0);
113	if (!phy_np)
114		return -ENOENT;
115
116	/*
117	 * The 1st USB controller contains some UTMI pad registers that are
118	 * global for all the controllers on the chip. Those registers are
119	 * also cleared when reset is asserted to the 1st controller.
120	 */
121	rst_utmi = of_reset_control_get_shared(phy_np, "utmi-pads");
122	if (IS_ERR(rst_utmi)) {
123		dev_warn(dev, "can't get utmi-pads reset from the PHY\n");
124		dev_warn(dev, "continuing, but please update your DT\n");
125	} else {
126		/*
127		 * PHY driver performs UTMI-pads reset in a case of a
128		 * non-legacy DT.
129		 */
130		reset_control_put(rst_utmi);
131	}
132
133	of_node_put(phy_np);
134
135	/* reset control is shared, hence initialize it first */
136	err = reset_control_deassert(rst);
137	if (err)
138		return err;
139
140	err = reset_control_assert(rst);
141	if (err)
142		return err;
143
144	udelay(1);
145
146	err = reset_control_deassert(rst);
147	if (err)
148		return err;
149
150	return 0;
151}
152
153static int tegra_usb_notify_event(struct ci_hdrc *ci, unsigned int event)
154{
155	struct tegra_usb *usb = dev_get_drvdata(ci->dev->parent);
156	struct ehci_hcd *ehci;
157
158	switch (event) {
159	case CI_HDRC_CONTROLLER_RESET_EVENT:
160		if (ci->hcd) {
161			ehci = hcd_to_ehci(ci->hcd);
162			ehci->has_tdi_phy_lpm = false;
163			ehci_writel(ehci, usb->soc->txfifothresh << 16,
164				    &ehci->regs->txfill_tuning);
165		}
166		break;
167	}
168
169	return 0;
170}
171
172static int tegra_usb_internal_port_reset(struct ehci_hcd *ehci,
173					 u32 __iomem *portsc_reg,
174					 unsigned long *flags)
175{
176	u32 saved_usbintr, temp;
177	unsigned int i, tries;
178	int retval = 0;
179
180	saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
181	/* disable USB interrupt */
182	ehci_writel(ehci, 0, &ehci->regs->intr_enable);
183	spin_unlock_irqrestore(&ehci->lock, *flags);
184
185	/*
186	 * Here we have to do Port Reset at most twice for
187	 * Port Enable bit to be set.
188	 */
189	for (i = 0; i < 2; i++) {
190		temp = ehci_readl(ehci, portsc_reg);
191		temp |= PORT_RESET;
192		ehci_writel(ehci, temp, portsc_reg);
193		fsleep(10000);
194		temp &= ~PORT_RESET;
195		ehci_writel(ehci, temp, portsc_reg);
196		fsleep(1000);
197		tries = 100;
198		do {
199			fsleep(1000);
200			/*
201			 * Up to this point, Port Enable bit is
202			 * expected to be set after 2 ms waiting.
203			 * USB1 usually takes extra 45 ms, for safety,
204			 * we take 100 ms as timeout.
205			 */
206			temp = ehci_readl(ehci, portsc_reg);
207		} while (!(temp & PORT_PE) && tries--);
208		if (temp & PORT_PE)
209			break;
210	}
211	if (i == 2)
212		retval = -ETIMEDOUT;
213
214	/*
215	 * Clear Connect Status Change bit if it's set.
216	 * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
217	 */
218	if (temp & PORT_CSC)
219		ehci_writel(ehci, PORT_CSC, portsc_reg);
220
221	/*
222	 * Write to clear any interrupt status bits that might be set
223	 * during port reset.
224	 */
225	temp = ehci_readl(ehci, &ehci->regs->status);
226	ehci_writel(ehci, temp, &ehci->regs->status);
227
228	/* restore original interrupt-enable bits */
229	spin_lock_irqsave(&ehci->lock, *flags);
230	ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
231
232	return retval;
233}
234
235static int tegra_ehci_hub_control(struct ci_hdrc *ci, u16 typeReq, u16 wValue,
236				  u16 wIndex, char *buf, u16 wLength,
237				  bool *done, unsigned long *flags)
238{
239	struct tegra_usb *usb = dev_get_drvdata(ci->dev->parent);
240	struct ehci_hcd *ehci = hcd_to_ehci(ci->hcd);
241	u32 __iomem *status_reg;
242	int retval = 0;
243
244	status_reg = &ehci->regs->port_status[(wIndex & 0xff) - 1];
245
246	switch (typeReq) {
247	case SetPortFeature:
248		if (wValue != USB_PORT_FEAT_RESET || !usb->needs_double_reset)
249			break;
250
251		/* for USB1 port we need to issue Port Reset twice internally */
252		retval = tegra_usb_internal_port_reset(ehci, status_reg, flags);
253		*done  = true;
254		break;
255	}
256
257	return retval;
258}
259
260static void tegra_usb_enter_lpm(struct ci_hdrc *ci, bool enable)
261{
262	/*
263	 * Touching any register which belongs to AHB clock domain will
264	 * hang CPU if USB controller is put into low power mode because
265	 * AHB USB clock is gated on Tegra in the LPM.
266	 *
267	 * Tegra PHY has a separate register for checking the clock status
268	 * and usb_phy_set_suspend() takes care of gating/ungating the clocks
269	 * and restoring the PHY state on Tegra. Hence DEVLC/PORTSC registers
270	 * shouldn't be touched directly by the CI driver.
271	 */
272	usb_phy_set_suspend(ci->usb_phy, enable);
273}
274
275static int tegra_usb_probe(struct platform_device *pdev)
276{
277	const struct tegra_usb_soc_info *soc;
278	struct tegra_usb *usb;
279	int err;
280
281	usb = devm_kzalloc(&pdev->dev, sizeof(*usb), GFP_KERNEL);
282	if (!usb)
283		return -ENOMEM;
284
285	platform_set_drvdata(pdev, usb);
286
287	soc = of_device_get_match_data(&pdev->dev);
288	if (!soc) {
289		dev_err(&pdev->dev, "failed to match OF data\n");
290		return -EINVAL;
291	}
292
293	usb->phy = devm_usb_get_phy_by_phandle(&pdev->dev, "nvidia,phy", 0);
294	if (IS_ERR(usb->phy))
295		return dev_err_probe(&pdev->dev, PTR_ERR(usb->phy),
296				     "failed to get PHY\n");
297
298	usb->clk = devm_clk_get(&pdev->dev, NULL);
299	if (IS_ERR(usb->clk)) {
300		err = PTR_ERR(usb->clk);
301		dev_err(&pdev->dev, "failed to get clock: %d\n", err);
302		return err;
303	}
304
305	err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
306	if (err)
307		return err;
308
309	pm_runtime_enable(&pdev->dev);
310	err = pm_runtime_resume_and_get(&pdev->dev);
311	if (err)
312		return err;
313
314	if (device_property_present(&pdev->dev, "nvidia,needs-double-reset"))
315		usb->needs_double_reset = true;
316
317	err = tegra_usb_reset_controller(&pdev->dev);
318	if (err) {
319		dev_err(&pdev->dev, "failed to reset controller: %d\n", err);
320		goto fail_power_off;
321	}
322
323	/*
324	 * USB controller registers shouldn't be touched before PHY is
325	 * initialized, otherwise CPU will hang because clocks are gated.
326	 * PHY driver controls gating of internal USB clocks on Tegra.
327	 */
328	err = usb_phy_init(usb->phy);
329	if (err)
330		goto fail_power_off;
331
332	/* setup and register ChipIdea HDRC device */
333	usb->soc = soc;
334	usb->data.name = "tegra-usb";
335	usb->data.flags = soc->flags;
336	usb->data.usb_phy = usb->phy;
337	usb->data.dr_mode = soc->dr_mode;
338	usb->data.capoffset = DEF_CAPOFFSET;
339	usb->data.enter_lpm = tegra_usb_enter_lpm;
340	usb->data.hub_control = tegra_ehci_hub_control;
341	usb->data.notify_event = tegra_usb_notify_event;
342
343	/* Tegra PHY driver currently doesn't support LPM for ULPI */
344	if (of_usb_get_phy_mode(pdev->dev.of_node) == USBPHY_INTERFACE_MODE_ULPI)
345		usb->data.flags &= ~CI_HDRC_SUPPORTS_RUNTIME_PM;
346
347	usb->dev = ci_hdrc_add_device(&pdev->dev, pdev->resource,
348				      pdev->num_resources, &usb->data);
349	if (IS_ERR(usb->dev)) {
350		err = PTR_ERR(usb->dev);
351		dev_err(&pdev->dev, "failed to add HDRC device: %d\n", err);
352		goto phy_shutdown;
353	}
354
355	return 0;
356
357phy_shutdown:
358	usb_phy_shutdown(usb->phy);
359fail_power_off:
360	pm_runtime_put_sync_suspend(&pdev->dev);
361	pm_runtime_force_suspend(&pdev->dev);
362
363	return err;
364}
365
366static void tegra_usb_remove(struct platform_device *pdev)
367{
368	struct tegra_usb *usb = platform_get_drvdata(pdev);
369
370	ci_hdrc_remove_device(usb->dev);
371	usb_phy_shutdown(usb->phy);
372
373	pm_runtime_put_sync_suspend(&pdev->dev);
374	pm_runtime_force_suspend(&pdev->dev);
375}
376
377static int __maybe_unused tegra_usb_runtime_resume(struct device *dev)
378{
379	struct tegra_usb *usb = dev_get_drvdata(dev);
380	int err;
381
382	err = clk_prepare_enable(usb->clk);
383	if (err < 0) {
384		dev_err(dev, "failed to enable clock: %d\n", err);
385		return err;
386	}
387
388	return 0;
389}
390
391static int __maybe_unused tegra_usb_runtime_suspend(struct device *dev)
392{
393	struct tegra_usb *usb = dev_get_drvdata(dev);
394
395	clk_disable_unprepare(usb->clk);
396
397	return 0;
398}
399
400static const struct dev_pm_ops tegra_usb_pm = {
401	SET_RUNTIME_PM_OPS(tegra_usb_runtime_suspend, tegra_usb_runtime_resume,
402			   NULL)
403};
404
405static struct platform_driver tegra_usb_driver = {
406	.driver = {
407		.name = "tegra-usb",
408		.of_match_table = tegra_usb_of_match,
409		.pm = &tegra_usb_pm,
410	},
411	.probe = tegra_usb_probe,
412	.remove_new = tegra_usb_remove,
413};
414module_platform_driver(tegra_usb_driver);
415
416MODULE_DESCRIPTION("NVIDIA Tegra USB driver");
417MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
418MODULE_LICENSE("GPL v2");
419