162306a36Sopenharmony_ci/* SPDX-License-Identifier: GPL-2.0-only */ 262306a36Sopenharmony_ci/* 362306a36Sopenharmony_ci * UFS Host driver for Synopsys Designware Core 462306a36Sopenharmony_ci * 562306a36Sopenharmony_ci * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com) 662306a36Sopenharmony_ci * 762306a36Sopenharmony_ci * Authors: Joao Pinto <jpinto@synopsys.com> 862306a36Sopenharmony_ci */ 962306a36Sopenharmony_ci 1062306a36Sopenharmony_ci#ifndef _UFSHCI_DWC_H 1162306a36Sopenharmony_ci#define _UFSHCI_DWC_H 1262306a36Sopenharmony_ci 1362306a36Sopenharmony_ci/* DWC HC UFSHCI specific Registers */ 1462306a36Sopenharmony_cienum dwc_specific_registers { 1562306a36Sopenharmony_ci DWC_UFS_REG_HCLKDIV = 0xFC, 1662306a36Sopenharmony_ci}; 1762306a36Sopenharmony_ci 1862306a36Sopenharmony_ci/* Clock Divider Values: Hex equivalent of frequency in MHz */ 1962306a36Sopenharmony_cienum clk_div_values { 2062306a36Sopenharmony_ci DWC_UFS_REG_HCLKDIV_DIV_62_5 = 0x3e, 2162306a36Sopenharmony_ci DWC_UFS_REG_HCLKDIV_DIV_125 = 0x7d, 2262306a36Sopenharmony_ci DWC_UFS_REG_HCLKDIV_DIV_200 = 0xc8, 2362306a36Sopenharmony_ci}; 2462306a36Sopenharmony_ci 2562306a36Sopenharmony_ci/* Selector Index */ 2662306a36Sopenharmony_cienum selector_index { 2762306a36Sopenharmony_ci SELIND_LN0_TX = 0x00, 2862306a36Sopenharmony_ci SELIND_LN1_TX = 0x01, 2962306a36Sopenharmony_ci SELIND_LN0_RX = 0x04, 3062306a36Sopenharmony_ci SELIND_LN1_RX = 0x05, 3162306a36Sopenharmony_ci}; 3262306a36Sopenharmony_ci 3362306a36Sopenharmony_ci#endif /* End of Header */ 34