1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2019 MediaTek Inc.
4 */
5
6#ifndef _UFS_MEDIATEK_H
7#define _UFS_MEDIATEK_H
8
9#include <linux/bitops.h>
10#include <linux/pm_qos.h>
11#include <linux/soc/mediatek/mtk_sip_svc.h>
12
13/*
14 * MCQ define and struct
15 */
16#define UFSHCD_MAX_Q_NR 8
17#define MTK_MCQ_INVALID_IRQ	0xFFFF
18
19/* REG_UFS_MMIO_OPT_CTRL_0 160h */
20#define EHS_EN                  BIT(0)
21#define PFM_IMPV                BIT(1)
22#define MCQ_MULTI_INTR_EN       BIT(2)
23#define MCQ_CMB_INTR_EN         BIT(3)
24#define MCQ_AH8                 BIT(4)
25
26#define MCQ_INTR_EN_MSK         (MCQ_MULTI_INTR_EN | MCQ_CMB_INTR_EN)
27
28/*
29 * Vendor specific UFSHCI Registers
30 */
31#define REG_UFS_XOUFS_CTRL          0x140
32#define REG_UFS_REFCLK_CTRL         0x144
33#define REG_UFS_MMIO_OPT_CTRL_0     0x160
34#define REG_UFS_EXTREG              0x2100
35#define REG_UFS_MPHYCTRL            0x2200
36#define REG_UFS_MTK_IP_VER          0x2240
37#define REG_UFS_REJECT_MON          0x22AC
38#define REG_UFS_DEBUG_SEL           0x22C0
39#define REG_UFS_PROBE               0x22C8
40#define REG_UFS_DEBUG_SEL_B0        0x22D0
41#define REG_UFS_DEBUG_SEL_B1        0x22D4
42#define REG_UFS_DEBUG_SEL_B2        0x22D8
43#define REG_UFS_DEBUG_SEL_B3        0x22DC
44
45#define REG_UFS_MTK_SQD             0x2800
46#define REG_UFS_MTK_SQIS            0x2814
47#define REG_UFS_MTK_CQD             0x281C
48#define REG_UFS_MTK_CQIS            0x2824
49
50#define REG_UFS_MCQ_STRIDE          0x30
51
52/*
53 * Ref-clk control
54 *
55 * Values for register REG_UFS_REFCLK_CTRL
56 */
57#define REFCLK_RELEASE              0x0
58#define REFCLK_REQUEST              BIT(0)
59#define REFCLK_ACK                  BIT(1)
60
61#define REFCLK_REQ_TIMEOUT_US       3000
62#define REFCLK_DEFAULT_WAIT_US      32
63
64/*
65 * Other attributes
66 */
67#define VS_DEBUGCLOCKENABLE         0xD0A1
68#define VS_SAVEPOWERCONTROL         0xD0A6
69#define VS_UNIPROPOWERDOWNCONTROL   0xD0A8
70
71/*
72 * Vendor specific link state
73 */
74enum {
75	VS_LINK_DISABLED            = 0,
76	VS_LINK_DOWN                = 1,
77	VS_LINK_UP                  = 2,
78	VS_LINK_HIBERN8             = 3,
79	VS_LINK_LOST                = 4,
80	VS_LINK_CFG                 = 5,
81};
82
83/*
84 * Vendor specific host controller state
85 */
86enum {
87	VS_HCE_RESET                = 0,
88	VS_HCE_BASE                 = 1,
89	VS_HCE_OOCPR_WAIT           = 2,
90	VS_HCE_DME_RESET            = 3,
91	VS_HCE_MIDDLE               = 4,
92	VS_HCE_DME_ENABLE           = 5,
93	VS_HCE_DEFAULTS             = 6,
94	VS_HIB_IDLEEN               = 7,
95	VS_HIB_ENTER                = 8,
96	VS_HIB_ENTER_CONF           = 9,
97	VS_HIB_MIDDLE               = 10,
98	VS_HIB_WAITTIMER            = 11,
99	VS_HIB_EXIT_CONF            = 12,
100	VS_HIB_EXIT                 = 13,
101};
102
103/*
104 * SiP commands
105 */
106#define MTK_SIP_UFS_CONTROL               MTK_SIP_SMC_CMD(0x276)
107#define UFS_MTK_SIP_VA09_PWR_CTRL         BIT(0)
108#define UFS_MTK_SIP_DEVICE_RESET          BIT(1)
109#define UFS_MTK_SIP_CRYPTO_CTRL           BIT(2)
110#define UFS_MTK_SIP_REF_CLK_NOTIFICATION  BIT(3)
111#define UFS_MTK_SIP_HOST_PWR_CTRL         BIT(5)
112#define UFS_MTK_SIP_GET_VCC_NUM           BIT(6)
113#define UFS_MTK_SIP_DEVICE_PWR_CTRL       BIT(7)
114
115/*
116 * VS_DEBUGCLOCKENABLE
117 */
118enum {
119	TX_SYMBOL_CLK_REQ_FORCE = 5,
120};
121
122/*
123 * VS_SAVEPOWERCONTROL
124 */
125enum {
126	RX_SYMBOL_CLK_GATE_EN   = 0,
127	SYS_CLK_GATE_EN         = 2,
128	TX_CLK_GATE_EN          = 3,
129};
130
131/*
132 * Host capability
133 */
134enum ufs_mtk_host_caps {
135	UFS_MTK_CAP_BOOST_CRYPT_ENGINE         = 1 << 0,
136	UFS_MTK_CAP_VA09_PWR_CTRL              = 1 << 1,
137	UFS_MTK_CAP_DISABLE_AH8                = 1 << 2,
138	UFS_MTK_CAP_BROKEN_VCC                 = 1 << 3,
139	UFS_MTK_CAP_PMC_VIA_FASTAUTO           = 1 << 6,
140};
141
142struct ufs_mtk_crypt_cfg {
143	struct regulator *reg_vcore;
144	struct clk *clk_crypt_perf;
145	struct clk *clk_crypt_mux;
146	struct clk *clk_crypt_lp;
147	int vcore_volt;
148};
149
150struct ufs_mtk_clk {
151	struct ufs_clk_info *ufs_sel_clki; /* Mux */
152	struct ufs_clk_info *ufs_sel_max_clki; /* Max src */
153	struct ufs_clk_info *ufs_sel_min_clki; /* Min src */
154};
155
156struct ufs_mtk_hw_ver {
157	u8 step;
158	u8 minor;
159	u8 major;
160};
161
162struct ufs_mtk_mcq_intr_info {
163	struct ufs_hba *hba;
164	u32 irq;
165	u8 qid;
166};
167
168struct ufs_mtk_host {
169	struct phy *mphy;
170	struct pm_qos_request pm_qos_req;
171	struct regulator *reg_va09;
172	struct reset_control *hci_reset;
173	struct reset_control *unipro_reset;
174	struct reset_control *crypto_reset;
175	struct ufs_hba *hba;
176	struct ufs_mtk_crypt_cfg *crypt;
177	struct ufs_mtk_clk mclk;
178	struct ufs_mtk_hw_ver hw_ver;
179	enum ufs_mtk_host_caps caps;
180	bool mphy_powered_on;
181	bool pm_qos_init;
182	bool unipro_lpm;
183	bool ref_clk_enabled;
184	u16 ref_clk_ungating_wait_us;
185	u16 ref_clk_gating_wait_us;
186	u32 ip_ver;
187
188	bool mcq_set_intr;
189	int mcq_nr_intr;
190	struct ufs_mtk_mcq_intr_info mcq_intr_info[UFSHCD_MAX_Q_NR];
191};
192
193/*
194 * Multi-VCC by Numbering
195 */
196enum ufs_mtk_vcc_num {
197	UFS_VCC_NONE = 0,
198	UFS_VCC_1,
199	UFS_VCC_2,
200	UFS_VCC_MAX
201};
202
203/*
204 * Host Power Control options
205 */
206enum {
207	HOST_PWR_HCI = 0,
208	HOST_PWR_MPHY
209};
210
211/*
212 * SMC call wrapper function
213 */
214struct ufs_mtk_smc_arg {
215	unsigned long cmd;
216	struct arm_smccc_res *res;
217	unsigned long v1;
218	unsigned long v2;
219	unsigned long v3;
220	unsigned long v4;
221	unsigned long v5;
222	unsigned long v6;
223	unsigned long v7;
224};
225
226static void _ufs_mtk_smc(struct ufs_mtk_smc_arg s)
227{
228	arm_smccc_smc(MTK_SIP_UFS_CONTROL,
229		      s.cmd, s.v1, s.v2, s.v3, s.v4, s.v5, s.v6, s.res);
230}
231
232#define ufs_mtk_smc(...) \
233	_ufs_mtk_smc((struct ufs_mtk_smc_arg) {__VA_ARGS__})
234
235/*
236 * SMC call interface
237 */
238#define ufs_mtk_va09_pwr_ctrl(res, on) \
239	ufs_mtk_smc(UFS_MTK_SIP_VA09_PWR_CTRL, &(res), on)
240
241#define ufs_mtk_crypto_ctrl(res, enable) \
242	ufs_mtk_smc(UFS_MTK_SIP_CRYPTO_CTRL, &(res), enable)
243
244#define ufs_mtk_ref_clk_notify(on, stage, res) \
245	ufs_mtk_smc(UFS_MTK_SIP_REF_CLK_NOTIFICATION, &(res), on, stage)
246
247#define ufs_mtk_device_reset_ctrl(high, res) \
248	ufs_mtk_smc(UFS_MTK_SIP_DEVICE_RESET, &(res), high)
249
250#define ufs_mtk_host_pwr_ctrl(opt, on, res) \
251	ufs_mtk_smc(UFS_MTK_SIP_HOST_PWR_CTRL, &(res), opt, on)
252
253#define ufs_mtk_get_vcc_num(res) \
254	ufs_mtk_smc(UFS_MTK_SIP_GET_VCC_NUM, &(res))
255
256#define ufs_mtk_device_pwr_ctrl(on, ufs_ver, res) \
257	ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_ver)
258
259#endif /* !_UFS_MEDIATEK_H */
260