1// SPDX-License-Identifier: GPL-2.0 2/* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC. 3 * 4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be) 5 * Copyright (C) 2002, 2006 David S. Miller (davem@davemloft.net) 6 * 7 * Rewrote buffer handling to use CIRC(Circular Buffer) macros. 8 * Maxim Krasnyanskiy <maxk@qualcomm.com> 9 * 10 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud 11 * rates to be programmed into the UART. Also eliminated a lot of 12 * duplicated code in the console setup. 13 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12 14 * 15 * Ported to new 2.5.x UART layer. 16 * David S. Miller <davem@davemloft.net> 17 */ 18 19#include <linux/module.h> 20#include <linux/kernel.h> 21#include <linux/errno.h> 22#include <linux/tty.h> 23#include <linux/tty_flip.h> 24#include <linux/major.h> 25#include <linux/string.h> 26#include <linux/ptrace.h> 27#include <linux/ioport.h> 28#include <linux/circ_buf.h> 29#include <linux/serial.h> 30#include <linux/sysrq.h> 31#include <linux/console.h> 32#include <linux/spinlock.h> 33#include <linux/slab.h> 34#include <linux/delay.h> 35#include <linux/init.h> 36#include <linux/of.h> 37#include <linux/platform_device.h> 38 39#include <linux/io.h> 40#include <asm/irq.h> 41#include <asm/prom.h> 42#include <asm/setup.h> 43 44#include <linux/serial_core.h> 45#include <linux/sunserialcore.h> 46 47#include "sunsab.h" 48 49struct uart_sunsab_port { 50 struct uart_port port; /* Generic UART port */ 51 union sab82532_async_regs __iomem *regs; /* Chip registers */ 52 unsigned long irqflags; /* IRQ state flags */ 53 int dsr; /* Current DSR state */ 54 unsigned int cec_timeout; /* Chip poll timeout... */ 55 unsigned int tec_timeout; /* likewise */ 56 unsigned char interrupt_mask0;/* ISR0 masking */ 57 unsigned char interrupt_mask1;/* ISR1 masking */ 58 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */ 59 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */ 60 unsigned int gis_shift; 61 int type; /* SAB82532 version */ 62 63 /* Setting configuration bits while the transmitter is active 64 * can cause garbage characters to get emitted by the chip. 65 * Therefore, we cache such writes here and do the real register 66 * write the next time the transmitter becomes idle. 67 */ 68 unsigned int cached_ebrg; 69 unsigned char cached_mode; 70 unsigned char cached_pvr; 71 unsigned char cached_dafo; 72}; 73 74/* 75 * This assumes you have a 29.4912 MHz clock for your UART. 76 */ 77#define SAB_BASE_BAUD ( 29491200 / 16 ) 78 79static char *sab82532_version[16] = { 80 "V1.0", "V2.0", "V3.2", "V(0x03)", 81 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)", 82 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)", 83 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)" 84}; 85 86#define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */ 87#define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */ 88 89#define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */ 90#define SAB82532_XMIT_FIFO_SIZE 32 91 92static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up) 93{ 94 int timeout = up->tec_timeout; 95 96 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout) 97 udelay(1); 98} 99 100static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up) 101{ 102 int timeout = up->cec_timeout; 103 104 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout) 105 udelay(1); 106} 107 108static struct tty_port * 109receive_chars(struct uart_sunsab_port *up, 110 union sab82532_irq_status *stat) 111{ 112 struct tty_port *port = NULL; 113 unsigned char buf[32]; 114 int saw_console_brk = 0; 115 int free_fifo = 0; 116 int count = 0; 117 int i; 118 119 if (up->port.state != NULL) /* Unopened serial console */ 120 port = &up->port.state->port; 121 122 /* Read number of BYTES (Character + Status) available. */ 123 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) { 124 count = SAB82532_RECV_FIFO_SIZE; 125 free_fifo++; 126 } 127 128 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) { 129 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1); 130 free_fifo++; 131 } 132 133 /* Issue a FIFO read command in case we where idle. */ 134 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) { 135 sunsab_cec_wait(up); 136 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr); 137 return port; 138 } 139 140 if (stat->sreg.isr0 & SAB82532_ISR0_RFO) 141 free_fifo++; 142 143 /* Read the FIFO. */ 144 for (i = 0; i < count; i++) 145 buf[i] = readb(&up->regs->r.rfifo[i]); 146 147 /* Issue Receive Message Complete command. */ 148 if (free_fifo) { 149 sunsab_cec_wait(up); 150 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr); 151 } 152 153 /* Count may be zero for BRK, so we check for it here */ 154 if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) && 155 (up->port.line == up->port.cons->index)) 156 saw_console_brk = 1; 157 158 if (count == 0) { 159 if (unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) { 160 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR | 161 SAB82532_ISR0_FERR); 162 up->port.icount.brk++; 163 uart_handle_break(&up->port); 164 } 165 } 166 167 for (i = 0; i < count; i++) { 168 unsigned char ch = buf[i], flag; 169 170 flag = TTY_NORMAL; 171 up->port.icount.rx++; 172 173 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR | 174 SAB82532_ISR0_FERR | 175 SAB82532_ISR0_RFO)) || 176 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) { 177 /* 178 * For statistics only 179 */ 180 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) { 181 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR | 182 SAB82532_ISR0_FERR); 183 up->port.icount.brk++; 184 /* 185 * We do the SysRQ and SAK checking 186 * here because otherwise the break 187 * may get masked by ignore_status_mask 188 * or read_status_mask. 189 */ 190 if (uart_handle_break(&up->port)) 191 continue; 192 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR) 193 up->port.icount.parity++; 194 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR) 195 up->port.icount.frame++; 196 if (stat->sreg.isr0 & SAB82532_ISR0_RFO) 197 up->port.icount.overrun++; 198 199 /* 200 * Mask off conditions which should be ingored. 201 */ 202 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff); 203 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff); 204 205 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) { 206 flag = TTY_BREAK; 207 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR) 208 flag = TTY_PARITY; 209 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR) 210 flag = TTY_FRAME; 211 } 212 213 if (uart_handle_sysrq_char(&up->port, ch) || !port) 214 continue; 215 216 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 && 217 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0) 218 tty_insert_flip_char(port, ch, flag); 219 if (stat->sreg.isr0 & SAB82532_ISR0_RFO) 220 tty_insert_flip_char(port, 0, TTY_OVERRUN); 221 } 222 223 if (saw_console_brk) 224 sun_do_break(); 225 226 return port; 227} 228 229static void sunsab_stop_tx(struct uart_port *); 230static void sunsab_tx_idle(struct uart_sunsab_port *); 231 232static void transmit_chars(struct uart_sunsab_port *up, 233 union sab82532_irq_status *stat) 234{ 235 struct circ_buf *xmit = &up->port.state->xmit; 236 int i; 237 238 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) { 239 up->interrupt_mask1 |= SAB82532_IMR1_ALLS; 240 writeb(up->interrupt_mask1, &up->regs->w.imr1); 241 set_bit(SAB82532_ALLS, &up->irqflags); 242 } 243 244#if 0 /* bde@nwlink.com says this check causes problems */ 245 if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR)) 246 return; 247#endif 248 249 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW)) 250 return; 251 252 set_bit(SAB82532_XPR, &up->irqflags); 253 sunsab_tx_idle(up); 254 255 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 256 up->interrupt_mask1 |= SAB82532_IMR1_XPR; 257 writeb(up->interrupt_mask1, &up->regs->w.imr1); 258 return; 259 } 260 261 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR); 262 writeb(up->interrupt_mask1, &up->regs->w.imr1); 263 clear_bit(SAB82532_ALLS, &up->irqflags); 264 265 /* Stuff 32 bytes into Transmit FIFO. */ 266 clear_bit(SAB82532_XPR, &up->irqflags); 267 for (i = 0; i < up->port.fifosize; i++) { 268 writeb(xmit->buf[xmit->tail], 269 &up->regs->w.xfifo[i]); 270 uart_xmit_advance(&up->port, 1); 271 if (uart_circ_empty(xmit)) 272 break; 273 } 274 275 /* Issue a Transmit Frame command. */ 276 sunsab_cec_wait(up); 277 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr); 278 279 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 280 uart_write_wakeup(&up->port); 281 282 if (uart_circ_empty(xmit)) 283 sunsab_stop_tx(&up->port); 284} 285 286static void check_status(struct uart_sunsab_port *up, 287 union sab82532_irq_status *stat) 288{ 289 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC) 290 uart_handle_dcd_change(&up->port, 291 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD)); 292 293 if (stat->sreg.isr1 & SAB82532_ISR1_CSC) 294 uart_handle_cts_change(&up->port, 295 (readb(&up->regs->r.star) & SAB82532_STAR_CTS)); 296 297 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) { 298 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1; 299 up->port.icount.dsr++; 300 } 301 302 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 303} 304 305static irqreturn_t sunsab_interrupt(int irq, void *dev_id) 306{ 307 struct uart_sunsab_port *up = dev_id; 308 struct tty_port *port = NULL; 309 union sab82532_irq_status status; 310 unsigned long flags; 311 unsigned char gis; 312 313 spin_lock_irqsave(&up->port.lock, flags); 314 315 status.stat = 0; 316 gis = readb(&up->regs->r.gis) >> up->gis_shift; 317 if (gis & 1) 318 status.sreg.isr0 = readb(&up->regs->r.isr0); 319 if (gis & 2) 320 status.sreg.isr1 = readb(&up->regs->r.isr1); 321 322 if (status.stat) { 323 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME | 324 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) || 325 (status.sreg.isr1 & SAB82532_ISR1_BRK)) 326 port = receive_chars(up, &status); 327 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) || 328 (status.sreg.isr1 & SAB82532_ISR1_CSC)) 329 check_status(up, &status); 330 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR)) 331 transmit_chars(up, &status); 332 } 333 334 spin_unlock_irqrestore(&up->port.lock, flags); 335 336 if (port) 337 tty_flip_buffer_push(port); 338 339 return IRQ_HANDLED; 340} 341 342/* port->lock is not held. */ 343static unsigned int sunsab_tx_empty(struct uart_port *port) 344{ 345 struct uart_sunsab_port *up = 346 container_of(port, struct uart_sunsab_port, port); 347 int ret; 348 349 /* Do not need a lock for a state test like this. */ 350 if (test_bit(SAB82532_ALLS, &up->irqflags)) 351 ret = TIOCSER_TEMT; 352 else 353 ret = 0; 354 355 return ret; 356} 357 358/* port->lock held by caller. */ 359static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl) 360{ 361 struct uart_sunsab_port *up = 362 container_of(port, struct uart_sunsab_port, port); 363 364 if (mctrl & TIOCM_RTS) { 365 up->cached_mode &= ~SAB82532_MODE_FRTS; 366 up->cached_mode |= SAB82532_MODE_RTS; 367 } else { 368 up->cached_mode |= (SAB82532_MODE_FRTS | 369 SAB82532_MODE_RTS); 370 } 371 if (mctrl & TIOCM_DTR) { 372 up->cached_pvr &= ~(up->pvr_dtr_bit); 373 } else { 374 up->cached_pvr |= up->pvr_dtr_bit; 375 } 376 377 set_bit(SAB82532_REGS_PENDING, &up->irqflags); 378 if (test_bit(SAB82532_XPR, &up->irqflags)) 379 sunsab_tx_idle(up); 380} 381 382/* port->lock is held by caller and interrupts are disabled. */ 383static unsigned int sunsab_get_mctrl(struct uart_port *port) 384{ 385 struct uart_sunsab_port *up = 386 container_of(port, struct uart_sunsab_port, port); 387 unsigned char val; 388 unsigned int result; 389 390 result = 0; 391 392 val = readb(&up->regs->r.pvr); 393 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR; 394 395 val = readb(&up->regs->r.vstr); 396 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR; 397 398 val = readb(&up->regs->r.star); 399 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0; 400 401 return result; 402} 403 404/* port->lock held by caller. */ 405static void sunsab_stop_tx(struct uart_port *port) 406{ 407 struct uart_sunsab_port *up = 408 container_of(port, struct uart_sunsab_port, port); 409 410 up->interrupt_mask1 |= SAB82532_IMR1_XPR; 411 writeb(up->interrupt_mask1, &up->regs->w.imr1); 412} 413 414/* port->lock held by caller. */ 415static void sunsab_tx_idle(struct uart_sunsab_port *up) 416{ 417 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) { 418 u8 tmp; 419 420 clear_bit(SAB82532_REGS_PENDING, &up->irqflags); 421 writeb(up->cached_mode, &up->regs->rw.mode); 422 writeb(up->cached_pvr, &up->regs->rw.pvr); 423 writeb(up->cached_dafo, &up->regs->w.dafo); 424 425 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr); 426 tmp = readb(&up->regs->rw.ccr2); 427 tmp &= ~0xc0; 428 tmp |= (up->cached_ebrg >> 2) & 0xc0; 429 writeb(tmp, &up->regs->rw.ccr2); 430 } 431} 432 433/* port->lock held by caller. */ 434static void sunsab_start_tx(struct uart_port *port) 435{ 436 struct uart_sunsab_port *up = 437 container_of(port, struct uart_sunsab_port, port); 438 struct circ_buf *xmit = &up->port.state->xmit; 439 int i; 440 441 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 442 return; 443 444 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR); 445 writeb(up->interrupt_mask1, &up->regs->w.imr1); 446 447 if (!test_bit(SAB82532_XPR, &up->irqflags)) 448 return; 449 450 clear_bit(SAB82532_ALLS, &up->irqflags); 451 clear_bit(SAB82532_XPR, &up->irqflags); 452 453 for (i = 0; i < up->port.fifosize; i++) { 454 writeb(xmit->buf[xmit->tail], 455 &up->regs->w.xfifo[i]); 456 uart_xmit_advance(&up->port, 1); 457 if (uart_circ_empty(xmit)) 458 break; 459 } 460 461 /* Issue a Transmit Frame command. */ 462 sunsab_cec_wait(up); 463 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr); 464} 465 466/* port->lock is not held. */ 467static void sunsab_send_xchar(struct uart_port *port, char ch) 468{ 469 struct uart_sunsab_port *up = 470 container_of(port, struct uart_sunsab_port, port); 471 unsigned long flags; 472 473 if (ch == __DISABLED_CHAR) 474 return; 475 476 spin_lock_irqsave(&up->port.lock, flags); 477 478 sunsab_tec_wait(up); 479 writeb(ch, &up->regs->w.tic); 480 481 spin_unlock_irqrestore(&up->port.lock, flags); 482} 483 484/* port->lock held by caller. */ 485static void sunsab_stop_rx(struct uart_port *port) 486{ 487 struct uart_sunsab_port *up = 488 container_of(port, struct uart_sunsab_port, port); 489 490 up->interrupt_mask0 |= SAB82532_IMR0_TCD; 491 writeb(up->interrupt_mask1, &up->regs->w.imr0); 492} 493 494/* port->lock is not held. */ 495static void sunsab_break_ctl(struct uart_port *port, int break_state) 496{ 497 struct uart_sunsab_port *up = 498 container_of(port, struct uart_sunsab_port, port); 499 unsigned long flags; 500 unsigned char val; 501 502 spin_lock_irqsave(&up->port.lock, flags); 503 504 val = up->cached_dafo; 505 if (break_state) 506 val |= SAB82532_DAFO_XBRK; 507 else 508 val &= ~SAB82532_DAFO_XBRK; 509 up->cached_dafo = val; 510 511 set_bit(SAB82532_REGS_PENDING, &up->irqflags); 512 if (test_bit(SAB82532_XPR, &up->irqflags)) 513 sunsab_tx_idle(up); 514 515 spin_unlock_irqrestore(&up->port.lock, flags); 516} 517 518/* port->lock is not held. */ 519static int sunsab_startup(struct uart_port *port) 520{ 521 struct uart_sunsab_port *up = 522 container_of(port, struct uart_sunsab_port, port); 523 unsigned long flags; 524 unsigned char tmp; 525 int err = request_irq(up->port.irq, sunsab_interrupt, 526 IRQF_SHARED, "sab", up); 527 if (err) 528 return err; 529 530 spin_lock_irqsave(&up->port.lock, flags); 531 532 /* 533 * Wait for any commands or immediate characters 534 */ 535 sunsab_cec_wait(up); 536 sunsab_tec_wait(up); 537 538 /* 539 * Clear the FIFO buffers. 540 */ 541 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr); 542 sunsab_cec_wait(up); 543 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr); 544 545 /* 546 * Clear the interrupt registers. 547 */ 548 (void) readb(&up->regs->r.isr0); 549 (void) readb(&up->regs->r.isr1); 550 551 /* 552 * Now, initialize the UART 553 */ 554 writeb(0, &up->regs->w.ccr0); /* power-down */ 555 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ | 556 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0); 557 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1); 558 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL | 559 SAB82532_CCR2_TOE, &up->regs->w.ccr2); 560 writeb(0, &up->regs->w.ccr3); 561 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4); 562 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS | 563 SAB82532_MODE_RAC); 564 writeb(up->cached_mode, &up->regs->w.mode); 565 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc); 566 567 tmp = readb(&up->regs->rw.ccr0); 568 tmp |= SAB82532_CCR0_PU; /* power-up */ 569 writeb(tmp, &up->regs->rw.ccr0); 570 571 /* 572 * Finally, enable interrupts 573 */ 574 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR | 575 SAB82532_IMR0_PLLA); 576 writeb(up->interrupt_mask0, &up->regs->w.imr0); 577 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS | 578 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN | 579 SAB82532_IMR1_CSC | SAB82532_IMR1_XON | 580 SAB82532_IMR1_XPR); 581 writeb(up->interrupt_mask1, &up->regs->w.imr1); 582 set_bit(SAB82532_ALLS, &up->irqflags); 583 set_bit(SAB82532_XPR, &up->irqflags); 584 585 spin_unlock_irqrestore(&up->port.lock, flags); 586 587 return 0; 588} 589 590/* port->lock is not held. */ 591static void sunsab_shutdown(struct uart_port *port) 592{ 593 struct uart_sunsab_port *up = 594 container_of(port, struct uart_sunsab_port, port); 595 unsigned long flags; 596 597 spin_lock_irqsave(&up->port.lock, flags); 598 599 /* Disable Interrupts */ 600 up->interrupt_mask0 = 0xff; 601 writeb(up->interrupt_mask0, &up->regs->w.imr0); 602 up->interrupt_mask1 = 0xff; 603 writeb(up->interrupt_mask1, &up->regs->w.imr1); 604 605 /* Disable break condition */ 606 up->cached_dafo = readb(&up->regs->rw.dafo); 607 up->cached_dafo &= ~SAB82532_DAFO_XBRK; 608 writeb(up->cached_dafo, &up->regs->rw.dafo); 609 610 /* Disable Receiver */ 611 up->cached_mode &= ~SAB82532_MODE_RAC; 612 writeb(up->cached_mode, &up->regs->rw.mode); 613 614 /* 615 * XXX FIXME 616 * 617 * If the chip is powered down here the system hangs/crashes during 618 * reboot or shutdown. This needs to be investigated further, 619 * similar behaviour occurs in 2.4 when the driver is configured 620 * as a module only. One hint may be that data is sometimes 621 * transmitted at 9600 baud during shutdown (regardless of the 622 * speed the chip was configured for when the port was open). 623 */ 624#if 0 625 /* Power Down */ 626 tmp = readb(&up->regs->rw.ccr0); 627 tmp &= ~SAB82532_CCR0_PU; 628 writeb(tmp, &up->regs->rw.ccr0); 629#endif 630 631 spin_unlock_irqrestore(&up->port.lock, flags); 632 free_irq(up->port.irq, up); 633} 634 635/* 636 * This is used to figure out the divisor speeds. 637 * 638 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)), 639 * 640 * with 0 <= N < 64 and 0 <= M < 16 641 */ 642 643static void calc_ebrg(int baud, int *n_ret, int *m_ret) 644{ 645 int n, m; 646 647 if (baud == 0) { 648 *n_ret = 0; 649 *m_ret = 0; 650 return; 651 } 652 653 /* 654 * We scale numbers by 10 so that we get better accuracy 655 * without having to use floating point. Here we increment m 656 * until n is within the valid range. 657 */ 658 n = (SAB_BASE_BAUD * 10) / baud; 659 m = 0; 660 while (n >= 640) { 661 n = n / 2; 662 m++; 663 } 664 n = (n+5) / 10; 665 /* 666 * We try very hard to avoid speeds with M == 0 since they may 667 * not work correctly for XTAL frequences above 10 MHz. 668 */ 669 if ((m == 0) && ((n & 1) == 0)) { 670 n = n / 2; 671 m++; 672 } 673 *n_ret = n - 1; 674 *m_ret = m; 675} 676 677/* Internal routine, port->lock is held and local interrupts are disabled. */ 678static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag, 679 unsigned int iflag, unsigned int baud, 680 unsigned int quot) 681{ 682 unsigned char dafo; 683 int n, m; 684 685 /* Byte size and parity */ 686 switch (cflag & CSIZE) { 687 case CS5: dafo = SAB82532_DAFO_CHL5; break; 688 case CS6: dafo = SAB82532_DAFO_CHL6; break; 689 case CS7: dafo = SAB82532_DAFO_CHL7; break; 690 case CS8: dafo = SAB82532_DAFO_CHL8; break; 691 /* Never happens, but GCC is too dumb to figure it out */ 692 default: dafo = SAB82532_DAFO_CHL5; break; 693 } 694 695 if (cflag & CSTOPB) 696 dafo |= SAB82532_DAFO_STOP; 697 698 if (cflag & PARENB) 699 dafo |= SAB82532_DAFO_PARE; 700 701 if (cflag & PARODD) { 702 dafo |= SAB82532_DAFO_PAR_ODD; 703 } else { 704 dafo |= SAB82532_DAFO_PAR_EVEN; 705 } 706 up->cached_dafo = dafo; 707 708 calc_ebrg(baud, &n, &m); 709 710 up->cached_ebrg = n | (m << 6); 711 712 up->tec_timeout = (10 * 1000000) / baud; 713 up->cec_timeout = up->tec_timeout >> 2; 714 715 /* CTS flow control flags */ 716 /* We encode read_status_mask and ignore_status_mask like so: 717 * 718 * --------------------- 719 * | ... | ISR1 | ISR0 | 720 * --------------------- 721 * .. 15 8 7 0 722 */ 723 724 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME | 725 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF | 726 SAB82532_ISR0_CDSC); 727 up->port.read_status_mask |= (SAB82532_ISR1_CSC | 728 SAB82532_ISR1_ALLS | 729 SAB82532_ISR1_XPR) << 8; 730 if (iflag & INPCK) 731 up->port.read_status_mask |= (SAB82532_ISR0_PERR | 732 SAB82532_ISR0_FERR); 733 if (iflag & (IGNBRK | BRKINT | PARMRK)) 734 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8); 735 736 /* 737 * Characteres to ignore 738 */ 739 up->port.ignore_status_mask = 0; 740 if (iflag & IGNPAR) 741 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR | 742 SAB82532_ISR0_FERR); 743 if (iflag & IGNBRK) { 744 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8); 745 /* 746 * If we're ignoring parity and break indicators, 747 * ignore overruns too (for real raw support). 748 */ 749 if (iflag & IGNPAR) 750 up->port.ignore_status_mask |= SAB82532_ISR0_RFO; 751 } 752 753 /* 754 * ignore all characters if CREAD is not set 755 */ 756 if ((cflag & CREAD) == 0) 757 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF | 758 SAB82532_ISR0_TCD); 759 760 uart_update_timeout(&up->port, cflag, 761 (up->port.uartclk / (16 * quot))); 762 763 /* Now schedule a register update when the chip's 764 * transmitter is idle. 765 */ 766 up->cached_mode |= SAB82532_MODE_RAC; 767 set_bit(SAB82532_REGS_PENDING, &up->irqflags); 768 if (test_bit(SAB82532_XPR, &up->irqflags)) 769 sunsab_tx_idle(up); 770} 771 772/* port->lock is not held. */ 773static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios, 774 const struct ktermios *old) 775{ 776 struct uart_sunsab_port *up = 777 container_of(port, struct uart_sunsab_port, port); 778 unsigned long flags; 779 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000); 780 unsigned int quot = uart_get_divisor(port, baud); 781 782 spin_lock_irqsave(&up->port.lock, flags); 783 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot); 784 spin_unlock_irqrestore(&up->port.lock, flags); 785} 786 787static const char *sunsab_type(struct uart_port *port) 788{ 789 struct uart_sunsab_port *up = (void *)port; 790 static char buf[36]; 791 792 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]); 793 return buf; 794} 795 796static void sunsab_release_port(struct uart_port *port) 797{ 798} 799 800static int sunsab_request_port(struct uart_port *port) 801{ 802 return 0; 803} 804 805static void sunsab_config_port(struct uart_port *port, int flags) 806{ 807} 808 809static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser) 810{ 811 return -EINVAL; 812} 813 814static const struct uart_ops sunsab_pops = { 815 .tx_empty = sunsab_tx_empty, 816 .set_mctrl = sunsab_set_mctrl, 817 .get_mctrl = sunsab_get_mctrl, 818 .stop_tx = sunsab_stop_tx, 819 .start_tx = sunsab_start_tx, 820 .send_xchar = sunsab_send_xchar, 821 .stop_rx = sunsab_stop_rx, 822 .break_ctl = sunsab_break_ctl, 823 .startup = sunsab_startup, 824 .shutdown = sunsab_shutdown, 825 .set_termios = sunsab_set_termios, 826 .type = sunsab_type, 827 .release_port = sunsab_release_port, 828 .request_port = sunsab_request_port, 829 .config_port = sunsab_config_port, 830 .verify_port = sunsab_verify_port, 831}; 832 833static struct uart_driver sunsab_reg = { 834 .owner = THIS_MODULE, 835 .driver_name = "sunsab", 836 .dev_name = "ttyS", 837 .major = TTY_MAJOR, 838}; 839 840static struct uart_sunsab_port *sunsab_ports; 841 842#ifdef CONFIG_SERIAL_SUNSAB_CONSOLE 843 844static void sunsab_console_putchar(struct uart_port *port, unsigned char c) 845{ 846 struct uart_sunsab_port *up = 847 container_of(port, struct uart_sunsab_port, port); 848 849 sunsab_tec_wait(up); 850 writeb(c, &up->regs->w.tic); 851} 852 853static void sunsab_console_write(struct console *con, const char *s, unsigned n) 854{ 855 struct uart_sunsab_port *up = &sunsab_ports[con->index]; 856 unsigned long flags; 857 int locked = 1; 858 859 if (up->port.sysrq || oops_in_progress) 860 locked = spin_trylock_irqsave(&up->port.lock, flags); 861 else 862 spin_lock_irqsave(&up->port.lock, flags); 863 864 uart_console_write(&up->port, s, n, sunsab_console_putchar); 865 sunsab_tec_wait(up); 866 867 if (locked) 868 spin_unlock_irqrestore(&up->port.lock, flags); 869} 870 871static int sunsab_console_setup(struct console *con, char *options) 872{ 873 struct uart_sunsab_port *up = &sunsab_ports[con->index]; 874 unsigned long flags; 875 unsigned int baud, quot; 876 877 /* 878 * The console framework calls us for each and every port 879 * registered. Defer the console setup until the requested 880 * port has been properly discovered. A bit of a hack, 881 * though... 882 */ 883 if (up->port.type != PORT_SUNSAB) 884 return -EINVAL; 885 886 printk("Console: ttyS%d (SAB82532)\n", 887 (sunsab_reg.minor - 64) + con->index); 888 889 sunserial_console_termios(con, up->port.dev->of_node); 890 891 switch (con->cflag & CBAUD) { 892 case B150: baud = 150; break; 893 case B300: baud = 300; break; 894 case B600: baud = 600; break; 895 case B1200: baud = 1200; break; 896 case B2400: baud = 2400; break; 897 case B4800: baud = 4800; break; 898 default: case B9600: baud = 9600; break; 899 case B19200: baud = 19200; break; 900 case B38400: baud = 38400; break; 901 case B57600: baud = 57600; break; 902 case B115200: baud = 115200; break; 903 case B230400: baud = 230400; break; 904 case B460800: baud = 460800; break; 905 } 906 907 /* 908 * Temporary fix. 909 */ 910 spin_lock_init(&up->port.lock); 911 912 /* 913 * Initialize the hardware 914 */ 915 sunsab_startup(&up->port); 916 917 spin_lock_irqsave(&up->port.lock, flags); 918 919 /* 920 * Finally, enable interrupts 921 */ 922 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR | 923 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC; 924 writeb(up->interrupt_mask0, &up->regs->w.imr0); 925 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS | 926 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN | 927 SAB82532_IMR1_CSC | SAB82532_IMR1_XON | 928 SAB82532_IMR1_XPR; 929 writeb(up->interrupt_mask1, &up->regs->w.imr1); 930 931 quot = uart_get_divisor(&up->port, baud); 932 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot); 933 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS); 934 935 spin_unlock_irqrestore(&up->port.lock, flags); 936 937 return 0; 938} 939 940static struct console sunsab_console = { 941 .name = "ttyS", 942 .write = sunsab_console_write, 943 .device = uart_console_device, 944 .setup = sunsab_console_setup, 945 .flags = CON_PRINTBUFFER, 946 .index = -1, 947 .data = &sunsab_reg, 948}; 949 950static inline struct console *SUNSAB_CONSOLE(void) 951{ 952 return &sunsab_console; 953} 954#else 955#define SUNSAB_CONSOLE() (NULL) 956#define sunsab_console_init() do { } while (0) 957#endif 958 959static int sunsab_init_one(struct uart_sunsab_port *up, 960 struct platform_device *op, 961 unsigned long offset, 962 int line) 963{ 964 up->port.line = line; 965 up->port.dev = &op->dev; 966 967 up->port.mapbase = op->resource[0].start + offset; 968 up->port.membase = of_ioremap(&op->resource[0], offset, 969 sizeof(union sab82532_async_regs), 970 "sab"); 971 if (!up->port.membase) 972 return -ENOMEM; 973 up->regs = (union sab82532_async_regs __iomem *) up->port.membase; 974 975 up->port.irq = op->archdata.irqs[0]; 976 977 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE; 978 up->port.iotype = UPIO_MEM; 979 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SUNSAB_CONSOLE); 980 981 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc); 982 983 up->port.ops = &sunsab_pops; 984 up->port.type = PORT_SUNSAB; 985 up->port.uartclk = SAB_BASE_BAUD; 986 987 up->type = readb(&up->regs->r.vstr) & 0x0f; 988 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr); 989 writeb(0xff, &up->regs->w.pim); 990 if ((up->port.line & 0x1) == 0) { 991 up->pvr_dsr_bit = (1 << 0); 992 up->pvr_dtr_bit = (1 << 1); 993 up->gis_shift = 2; 994 } else { 995 up->pvr_dsr_bit = (1 << 3); 996 up->pvr_dtr_bit = (1 << 2); 997 up->gis_shift = 0; 998 } 999 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4); 1000 writeb(up->cached_pvr, &up->regs->w.pvr); 1001 up->cached_mode = readb(&up->regs->rw.mode); 1002 up->cached_mode |= SAB82532_MODE_FRTS; 1003 writeb(up->cached_mode, &up->regs->rw.mode); 1004 up->cached_mode |= SAB82532_MODE_RTS; 1005 writeb(up->cached_mode, &up->regs->rw.mode); 1006 1007 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT; 1008 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT; 1009 1010 return 0; 1011} 1012 1013static int sab_probe(struct platform_device *op) 1014{ 1015 static int inst; 1016 struct uart_sunsab_port *up; 1017 int err; 1018 1019 up = &sunsab_ports[inst * 2]; 1020 1021 err = sunsab_init_one(&up[0], op, 1022 0, 1023 (inst * 2) + 0); 1024 if (err) 1025 goto out; 1026 1027 err = sunsab_init_one(&up[1], op, 1028 sizeof(union sab82532_async_regs), 1029 (inst * 2) + 1); 1030 if (err) 1031 goto out1; 1032 1033 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node, 1034 &sunsab_reg, up[0].port.line, 1035 false); 1036 1037 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node, 1038 &sunsab_reg, up[1].port.line, 1039 false); 1040 1041 err = uart_add_one_port(&sunsab_reg, &up[0].port); 1042 if (err) 1043 goto out2; 1044 1045 err = uart_add_one_port(&sunsab_reg, &up[1].port); 1046 if (err) 1047 goto out3; 1048 1049 platform_set_drvdata(op, &up[0]); 1050 1051 inst++; 1052 1053 return 0; 1054 1055out3: 1056 uart_remove_one_port(&sunsab_reg, &up[0].port); 1057out2: 1058 of_iounmap(&op->resource[0], 1059 up[1].port.membase, 1060 sizeof(union sab82532_async_regs)); 1061out1: 1062 of_iounmap(&op->resource[0], 1063 up[0].port.membase, 1064 sizeof(union sab82532_async_regs)); 1065out: 1066 return err; 1067} 1068 1069static int sab_remove(struct platform_device *op) 1070{ 1071 struct uart_sunsab_port *up = platform_get_drvdata(op); 1072 1073 uart_remove_one_port(&sunsab_reg, &up[1].port); 1074 uart_remove_one_port(&sunsab_reg, &up[0].port); 1075 of_iounmap(&op->resource[0], 1076 up[1].port.membase, 1077 sizeof(union sab82532_async_regs)); 1078 of_iounmap(&op->resource[0], 1079 up[0].port.membase, 1080 sizeof(union sab82532_async_regs)); 1081 1082 return 0; 1083} 1084 1085static const struct of_device_id sab_match[] = { 1086 { 1087 .name = "se", 1088 }, 1089 { 1090 .name = "serial", 1091 .compatible = "sab82532", 1092 }, 1093 {}, 1094}; 1095MODULE_DEVICE_TABLE(of, sab_match); 1096 1097static struct platform_driver sab_driver = { 1098 .driver = { 1099 .name = "sab", 1100 .of_match_table = sab_match, 1101 }, 1102 .probe = sab_probe, 1103 .remove = sab_remove, 1104}; 1105 1106static int __init sunsab_init(void) 1107{ 1108 struct device_node *dp; 1109 int err; 1110 int num_channels = 0; 1111 1112 for_each_node_by_name(dp, "se") 1113 num_channels += 2; 1114 for_each_node_by_name(dp, "serial") { 1115 if (of_device_is_compatible(dp, "sab82532")) 1116 num_channels += 2; 1117 } 1118 1119 if (num_channels) { 1120 sunsab_ports = kcalloc(num_channels, 1121 sizeof(struct uart_sunsab_port), 1122 GFP_KERNEL); 1123 if (!sunsab_ports) 1124 return -ENOMEM; 1125 1126 err = sunserial_register_minors(&sunsab_reg, num_channels); 1127 if (err) { 1128 kfree(sunsab_ports); 1129 sunsab_ports = NULL; 1130 1131 return err; 1132 } 1133 } 1134 1135 err = platform_driver_register(&sab_driver); 1136 if (err) { 1137 kfree(sunsab_ports); 1138 sunsab_ports = NULL; 1139 } 1140 1141 return err; 1142} 1143 1144static void __exit sunsab_exit(void) 1145{ 1146 platform_driver_unregister(&sab_driver); 1147 if (sunsab_reg.nr) { 1148 sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr); 1149 } 1150 1151 kfree(sunsab_ports); 1152 sunsab_ports = NULL; 1153} 1154 1155module_init(sunsab_init); 1156module_exit(sunsab_exit); 1157 1158MODULE_AUTHOR("Eddie C. Dost and David S. Miller"); 1159MODULE_DESCRIPTION("Sun SAB82532 serial port driver"); 1160MODULE_LICENSE("GPL"); 1161