1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) 4 * 5 * Copyright (C) 2002 - 2011 Paul Mundt 6 * Copyright (C) 2015 Glider bvba 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). 8 * 9 * based off of the old drivers/char/sh-sci.c by: 10 * 11 * Copyright (C) 1999, 2000 Niibe Yutaka 12 * Copyright (C) 2000 Sugioka Toshinobu 13 * Modified to support multiple serial ports. Stuart Menefy (May 2000). 14 * Modified to support SecureEdge. David McCullough (2002) 15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). 16 * Removed SH7300 support (Jul 2007). 17 */ 18#undef DEBUG 19 20#include <linux/clk.h> 21#include <linux/console.h> 22#include <linux/ctype.h> 23#include <linux/cpufreq.h> 24#include <linux/delay.h> 25#include <linux/dmaengine.h> 26#include <linux/dma-mapping.h> 27#include <linux/err.h> 28#include <linux/errno.h> 29#include <linux/init.h> 30#include <linux/interrupt.h> 31#include <linux/ioport.h> 32#include <linux/ktime.h> 33#include <linux/major.h> 34#include <linux/minmax.h> 35#include <linux/module.h> 36#include <linux/mm.h> 37#include <linux/of.h> 38#include <linux/platform_device.h> 39#include <linux/pm_runtime.h> 40#include <linux/reset.h> 41#include <linux/scatterlist.h> 42#include <linux/serial.h> 43#include <linux/serial_sci.h> 44#include <linux/sh_dma.h> 45#include <linux/slab.h> 46#include <linux/string.h> 47#include <linux/sysrq.h> 48#include <linux/timer.h> 49#include <linux/tty.h> 50#include <linux/tty_flip.h> 51 52#ifdef CONFIG_SUPERH 53#include <asm/sh_bios.h> 54#include <asm/platform_early.h> 55#endif 56 57#include "serial_mctrl_gpio.h" 58#include "sh-sci.h" 59 60/* Offsets into the sci_port->irqs array */ 61enum { 62 SCIx_ERI_IRQ, 63 SCIx_RXI_IRQ, 64 SCIx_TXI_IRQ, 65 SCIx_BRI_IRQ, 66 SCIx_DRI_IRQ, 67 SCIx_TEI_IRQ, 68 SCIx_NR_IRQS, 69 70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ 71}; 72 73#define SCIx_IRQ_IS_MUXED(port) \ 74 ((port)->irqs[SCIx_ERI_IRQ] == \ 75 (port)->irqs[SCIx_RXI_IRQ]) || \ 76 ((port)->irqs[SCIx_ERI_IRQ] && \ 77 ((port)->irqs[SCIx_RXI_IRQ] < 0)) 78 79enum SCI_CLKS { 80 SCI_FCK, /* Functional Clock */ 81 SCI_SCK, /* Optional External Clock */ 82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */ 83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */ 84 SCI_NUM_CLKS 85}; 86 87/* Bit x set means sampling rate x + 1 is supported */ 88#define SCI_SR(x) BIT((x) - 1) 89#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1) 90 91#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \ 92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \ 93 SCI_SR(19) | SCI_SR(27) 94 95#define min_sr(_port) ffs((_port)->sampling_rate_mask) 96#define max_sr(_port) fls((_port)->sampling_rate_mask) 97 98/* Iterate over all supported sampling rates, from high to low */ 99#define for_each_sr(_sr, _port) \ 100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \ 101 if ((_port)->sampling_rate_mask & SCI_SR((_sr))) 102 103struct plat_sci_reg { 104 u8 offset, size; 105}; 106 107struct sci_port_params { 108 const struct plat_sci_reg regs[SCIx_NR_REGS]; 109 unsigned int fifosize; 110 unsigned int overrun_reg; 111 unsigned int overrun_mask; 112 unsigned int sampling_rate_mask; 113 unsigned int error_mask; 114 unsigned int error_clear; 115}; 116 117struct sci_port { 118 struct uart_port port; 119 120 /* Platform configuration */ 121 const struct sci_port_params *params; 122 const struct plat_sci_port *cfg; 123 unsigned int sampling_rate_mask; 124 resource_size_t reg_size; 125 struct mctrl_gpios *gpios; 126 127 /* Clocks */ 128 struct clk *clks[SCI_NUM_CLKS]; 129 unsigned long clk_rates[SCI_NUM_CLKS]; 130 131 int irqs[SCIx_NR_IRQS]; 132 char *irqstr[SCIx_NR_IRQS]; 133 134 struct dma_chan *chan_tx; 135 struct dma_chan *chan_rx; 136 137#ifdef CONFIG_SERIAL_SH_SCI_DMA 138 struct dma_chan *chan_tx_saved; 139 struct dma_chan *chan_rx_saved; 140 dma_cookie_t cookie_tx; 141 dma_cookie_t cookie_rx[2]; 142 dma_cookie_t active_rx; 143 dma_addr_t tx_dma_addr; 144 unsigned int tx_dma_len; 145 struct scatterlist sg_rx[2]; 146 void *rx_buf[2]; 147 size_t buf_len_rx; 148 struct work_struct work_tx; 149 struct hrtimer rx_timer; 150 unsigned int rx_timeout; /* microseconds */ 151#endif 152 unsigned int rx_frame; 153 int rx_trigger; 154 struct timer_list rx_fifo_timer; 155 int rx_fifo_timeout; 156 u16 hscif_tot; 157 158 bool has_rtscts; 159 bool autorts; 160}; 161 162#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS 163 164static struct sci_port sci_ports[SCI_NPORTS]; 165static unsigned long sci_ports_in_use; 166static struct uart_driver sci_uart_driver; 167 168static inline struct sci_port * 169to_sci_port(struct uart_port *uart) 170{ 171 return container_of(uart, struct sci_port, port); 172} 173 174static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = { 175 /* 176 * Common SCI definitions, dependent on the port's regshift 177 * value. 178 */ 179 [SCIx_SCI_REGTYPE] = { 180 .regs = { 181 [SCSMR] = { 0x00, 8 }, 182 [SCBRR] = { 0x01, 8 }, 183 [SCSCR] = { 0x02, 8 }, 184 [SCxTDR] = { 0x03, 8 }, 185 [SCxSR] = { 0x04, 8 }, 186 [SCxRDR] = { 0x05, 8 }, 187 }, 188 .fifosize = 1, 189 .overrun_reg = SCxSR, 190 .overrun_mask = SCI_ORER, 191 .sampling_rate_mask = SCI_SR(32), 192 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 193 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 194 }, 195 196 /* 197 * Common definitions for legacy IrDA ports. 198 */ 199 [SCIx_IRDA_REGTYPE] = { 200 .regs = { 201 [SCSMR] = { 0x00, 8 }, 202 [SCBRR] = { 0x02, 8 }, 203 [SCSCR] = { 0x04, 8 }, 204 [SCxTDR] = { 0x06, 8 }, 205 [SCxSR] = { 0x08, 16 }, 206 [SCxRDR] = { 0x0a, 8 }, 207 [SCFCR] = { 0x0c, 8 }, 208 [SCFDR] = { 0x0e, 16 }, 209 }, 210 .fifosize = 1, 211 .overrun_reg = SCxSR, 212 .overrun_mask = SCI_ORER, 213 .sampling_rate_mask = SCI_SR(32), 214 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER, 215 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER, 216 }, 217 218 /* 219 * Common SCIFA definitions. 220 */ 221 [SCIx_SCIFA_REGTYPE] = { 222 .regs = { 223 [SCSMR] = { 0x00, 16 }, 224 [SCBRR] = { 0x04, 8 }, 225 [SCSCR] = { 0x08, 16 }, 226 [SCxTDR] = { 0x20, 8 }, 227 [SCxSR] = { 0x14, 16 }, 228 [SCxRDR] = { 0x24, 8 }, 229 [SCFCR] = { 0x18, 16 }, 230 [SCFDR] = { 0x1c, 16 }, 231 [SCPCR] = { 0x30, 16 }, 232 [SCPDR] = { 0x34, 16 }, 233 }, 234 .fifosize = 64, 235 .overrun_reg = SCxSR, 236 .overrun_mask = SCIFA_ORER, 237 .sampling_rate_mask = SCI_SR_SCIFAB, 238 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 239 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 240 }, 241 242 /* 243 * Common SCIFB definitions. 244 */ 245 [SCIx_SCIFB_REGTYPE] = { 246 .regs = { 247 [SCSMR] = { 0x00, 16 }, 248 [SCBRR] = { 0x04, 8 }, 249 [SCSCR] = { 0x08, 16 }, 250 [SCxTDR] = { 0x40, 8 }, 251 [SCxSR] = { 0x14, 16 }, 252 [SCxRDR] = { 0x60, 8 }, 253 [SCFCR] = { 0x18, 16 }, 254 [SCTFDR] = { 0x38, 16 }, 255 [SCRFDR] = { 0x3c, 16 }, 256 [SCPCR] = { 0x30, 16 }, 257 [SCPDR] = { 0x34, 16 }, 258 }, 259 .fifosize = 256, 260 .overrun_reg = SCxSR, 261 .overrun_mask = SCIFA_ORER, 262 .sampling_rate_mask = SCI_SR_SCIFAB, 263 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 264 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 265 }, 266 267 /* 268 * Common SH-2(A) SCIF definitions for ports with FIFO data 269 * count registers. 270 */ 271 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { 272 .regs = { 273 [SCSMR] = { 0x00, 16 }, 274 [SCBRR] = { 0x04, 8 }, 275 [SCSCR] = { 0x08, 16 }, 276 [SCxTDR] = { 0x0c, 8 }, 277 [SCxSR] = { 0x10, 16 }, 278 [SCxRDR] = { 0x14, 8 }, 279 [SCFCR] = { 0x18, 16 }, 280 [SCFDR] = { 0x1c, 16 }, 281 [SCSPTR] = { 0x20, 16 }, 282 [SCLSR] = { 0x24, 16 }, 283 }, 284 .fifosize = 16, 285 .overrun_reg = SCLSR, 286 .overrun_mask = SCLSR_ORER, 287 .sampling_rate_mask = SCI_SR(32), 288 .error_mask = SCIF_DEFAULT_ERROR_MASK, 289 .error_clear = SCIF_ERROR_CLEAR, 290 }, 291 292 /* 293 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T. 294 * It looks like a normal SCIF with FIFO data, but with a 295 * compressed address space. Also, the break out of interrupts 296 * are different: ERI/BRI, RXI, TXI, TEI, DRI. 297 */ 298 [SCIx_RZ_SCIFA_REGTYPE] = { 299 .regs = { 300 [SCSMR] = { 0x00, 16 }, 301 [SCBRR] = { 0x02, 8 }, 302 [SCSCR] = { 0x04, 16 }, 303 [SCxTDR] = { 0x06, 8 }, 304 [SCxSR] = { 0x08, 16 }, 305 [SCxRDR] = { 0x0A, 8 }, 306 [SCFCR] = { 0x0C, 16 }, 307 [SCFDR] = { 0x0E, 16 }, 308 [SCSPTR] = { 0x10, 16 }, 309 [SCLSR] = { 0x12, 16 }, 310 [SEMR] = { 0x14, 8 }, 311 }, 312 .fifosize = 16, 313 .overrun_reg = SCLSR, 314 .overrun_mask = SCLSR_ORER, 315 .sampling_rate_mask = SCI_SR(32), 316 .error_mask = SCIF_DEFAULT_ERROR_MASK, 317 .error_clear = SCIF_ERROR_CLEAR, 318 }, 319 320 /* 321 * Common SH-3 SCIF definitions. 322 */ 323 [SCIx_SH3_SCIF_REGTYPE] = { 324 .regs = { 325 [SCSMR] = { 0x00, 8 }, 326 [SCBRR] = { 0x02, 8 }, 327 [SCSCR] = { 0x04, 8 }, 328 [SCxTDR] = { 0x06, 8 }, 329 [SCxSR] = { 0x08, 16 }, 330 [SCxRDR] = { 0x0a, 8 }, 331 [SCFCR] = { 0x0c, 8 }, 332 [SCFDR] = { 0x0e, 16 }, 333 }, 334 .fifosize = 16, 335 .overrun_reg = SCLSR, 336 .overrun_mask = SCLSR_ORER, 337 .sampling_rate_mask = SCI_SR(32), 338 .error_mask = SCIF_DEFAULT_ERROR_MASK, 339 .error_clear = SCIF_ERROR_CLEAR, 340 }, 341 342 /* 343 * Common SH-4(A) SCIF(B) definitions. 344 */ 345 [SCIx_SH4_SCIF_REGTYPE] = { 346 .regs = { 347 [SCSMR] = { 0x00, 16 }, 348 [SCBRR] = { 0x04, 8 }, 349 [SCSCR] = { 0x08, 16 }, 350 [SCxTDR] = { 0x0c, 8 }, 351 [SCxSR] = { 0x10, 16 }, 352 [SCxRDR] = { 0x14, 8 }, 353 [SCFCR] = { 0x18, 16 }, 354 [SCFDR] = { 0x1c, 16 }, 355 [SCSPTR] = { 0x20, 16 }, 356 [SCLSR] = { 0x24, 16 }, 357 }, 358 .fifosize = 16, 359 .overrun_reg = SCLSR, 360 .overrun_mask = SCLSR_ORER, 361 .sampling_rate_mask = SCI_SR(32), 362 .error_mask = SCIF_DEFAULT_ERROR_MASK, 363 .error_clear = SCIF_ERROR_CLEAR, 364 }, 365 366 /* 367 * Common SCIF definitions for ports with a Baud Rate Generator for 368 * External Clock (BRG). 369 */ 370 [SCIx_SH4_SCIF_BRG_REGTYPE] = { 371 .regs = { 372 [SCSMR] = { 0x00, 16 }, 373 [SCBRR] = { 0x04, 8 }, 374 [SCSCR] = { 0x08, 16 }, 375 [SCxTDR] = { 0x0c, 8 }, 376 [SCxSR] = { 0x10, 16 }, 377 [SCxRDR] = { 0x14, 8 }, 378 [SCFCR] = { 0x18, 16 }, 379 [SCFDR] = { 0x1c, 16 }, 380 [SCSPTR] = { 0x20, 16 }, 381 [SCLSR] = { 0x24, 16 }, 382 [SCDL] = { 0x30, 16 }, 383 [SCCKS] = { 0x34, 16 }, 384 }, 385 .fifosize = 16, 386 .overrun_reg = SCLSR, 387 .overrun_mask = SCLSR_ORER, 388 .sampling_rate_mask = SCI_SR(32), 389 .error_mask = SCIF_DEFAULT_ERROR_MASK, 390 .error_clear = SCIF_ERROR_CLEAR, 391 }, 392 393 /* 394 * Common HSCIF definitions. 395 */ 396 [SCIx_HSCIF_REGTYPE] = { 397 .regs = { 398 [SCSMR] = { 0x00, 16 }, 399 [SCBRR] = { 0x04, 8 }, 400 [SCSCR] = { 0x08, 16 }, 401 [SCxTDR] = { 0x0c, 8 }, 402 [SCxSR] = { 0x10, 16 }, 403 [SCxRDR] = { 0x14, 8 }, 404 [SCFCR] = { 0x18, 16 }, 405 [SCFDR] = { 0x1c, 16 }, 406 [SCSPTR] = { 0x20, 16 }, 407 [SCLSR] = { 0x24, 16 }, 408 [HSSRR] = { 0x40, 16 }, 409 [SCDL] = { 0x30, 16 }, 410 [SCCKS] = { 0x34, 16 }, 411 [HSRTRGR] = { 0x54, 16 }, 412 [HSTTRGR] = { 0x58, 16 }, 413 }, 414 .fifosize = 128, 415 .overrun_reg = SCLSR, 416 .overrun_mask = SCLSR_ORER, 417 .sampling_rate_mask = SCI_SR_RANGE(8, 32), 418 .error_mask = SCIF_DEFAULT_ERROR_MASK, 419 .error_clear = SCIF_ERROR_CLEAR, 420 }, 421 422 /* 423 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR 424 * register. 425 */ 426 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { 427 .regs = { 428 [SCSMR] = { 0x00, 16 }, 429 [SCBRR] = { 0x04, 8 }, 430 [SCSCR] = { 0x08, 16 }, 431 [SCxTDR] = { 0x0c, 8 }, 432 [SCxSR] = { 0x10, 16 }, 433 [SCxRDR] = { 0x14, 8 }, 434 [SCFCR] = { 0x18, 16 }, 435 [SCFDR] = { 0x1c, 16 }, 436 [SCLSR] = { 0x24, 16 }, 437 }, 438 .fifosize = 16, 439 .overrun_reg = SCLSR, 440 .overrun_mask = SCLSR_ORER, 441 .sampling_rate_mask = SCI_SR(32), 442 .error_mask = SCIF_DEFAULT_ERROR_MASK, 443 .error_clear = SCIF_ERROR_CLEAR, 444 }, 445 446 /* 447 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data 448 * count registers. 449 */ 450 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { 451 .regs = { 452 [SCSMR] = { 0x00, 16 }, 453 [SCBRR] = { 0x04, 8 }, 454 [SCSCR] = { 0x08, 16 }, 455 [SCxTDR] = { 0x0c, 8 }, 456 [SCxSR] = { 0x10, 16 }, 457 [SCxRDR] = { 0x14, 8 }, 458 [SCFCR] = { 0x18, 16 }, 459 [SCFDR] = { 0x1c, 16 }, 460 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ 461 [SCRFDR] = { 0x20, 16 }, 462 [SCSPTR] = { 0x24, 16 }, 463 [SCLSR] = { 0x28, 16 }, 464 }, 465 .fifosize = 16, 466 .overrun_reg = SCLSR, 467 .overrun_mask = SCLSR_ORER, 468 .sampling_rate_mask = SCI_SR(32), 469 .error_mask = SCIF_DEFAULT_ERROR_MASK, 470 .error_clear = SCIF_ERROR_CLEAR, 471 }, 472 473 /* 474 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR 475 * registers. 476 */ 477 [SCIx_SH7705_SCIF_REGTYPE] = { 478 .regs = { 479 [SCSMR] = { 0x00, 16 }, 480 [SCBRR] = { 0x04, 8 }, 481 [SCSCR] = { 0x08, 16 }, 482 [SCxTDR] = { 0x20, 8 }, 483 [SCxSR] = { 0x14, 16 }, 484 [SCxRDR] = { 0x24, 8 }, 485 [SCFCR] = { 0x18, 16 }, 486 [SCFDR] = { 0x1c, 16 }, 487 }, 488 .fifosize = 64, 489 .overrun_reg = SCxSR, 490 .overrun_mask = SCIFA_ORER, 491 .sampling_rate_mask = SCI_SR(16), 492 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER, 493 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER, 494 }, 495}; 496 497#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset]) 498 499/* 500 * The "offset" here is rather misleading, in that it refers to an enum 501 * value relative to the port mapping rather than the fixed offset 502 * itself, which needs to be manually retrieved from the platform's 503 * register map for the given port. 504 */ 505static unsigned int sci_serial_in(struct uart_port *p, int offset) 506{ 507 const struct plat_sci_reg *reg = sci_getreg(p, offset); 508 509 if (reg->size == 8) 510 return ioread8(p->membase + (reg->offset << p->regshift)); 511 else if (reg->size == 16) 512 return ioread16(p->membase + (reg->offset << p->regshift)); 513 else 514 WARN(1, "Invalid register access\n"); 515 516 return 0; 517} 518 519static void sci_serial_out(struct uart_port *p, int offset, int value) 520{ 521 const struct plat_sci_reg *reg = sci_getreg(p, offset); 522 523 if (reg->size == 8) 524 iowrite8(value, p->membase + (reg->offset << p->regshift)); 525 else if (reg->size == 16) 526 iowrite16(value, p->membase + (reg->offset << p->regshift)); 527 else 528 WARN(1, "Invalid register access\n"); 529} 530 531static void sci_port_enable(struct sci_port *sci_port) 532{ 533 unsigned int i; 534 535 if (!sci_port->port.dev) 536 return; 537 538 pm_runtime_get_sync(sci_port->port.dev); 539 540 for (i = 0; i < SCI_NUM_CLKS; i++) { 541 clk_prepare_enable(sci_port->clks[i]); 542 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); 543 } 544 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; 545} 546 547static void sci_port_disable(struct sci_port *sci_port) 548{ 549 unsigned int i; 550 551 if (!sci_port->port.dev) 552 return; 553 554 for (i = SCI_NUM_CLKS; i-- > 0; ) 555 clk_disable_unprepare(sci_port->clks[i]); 556 557 pm_runtime_put_sync(sci_port->port.dev); 558} 559 560static inline unsigned long port_rx_irq_mask(struct uart_port *port) 561{ 562 /* 563 * Not all ports (such as SCIFA) will support REIE. Rather than 564 * special-casing the port type, we check the port initialization 565 * IRQ enable mask to see whether the IRQ is desired at all. If 566 * it's unset, it's logically inferred that there's no point in 567 * testing for it. 568 */ 569 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); 570} 571 572static void sci_start_tx(struct uart_port *port) 573{ 574 struct sci_port *s = to_sci_port(port); 575 unsigned short ctrl; 576 577#ifdef CONFIG_SERIAL_SH_SCI_DMA 578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 579 u16 new, scr = serial_port_in(port, SCSCR); 580 if (s->chan_tx) 581 new = scr | SCSCR_TDRQE; 582 else 583 new = scr & ~SCSCR_TDRQE; 584 if (new != scr) 585 serial_port_out(port, SCSCR, new); 586 } 587 588 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && 589 dma_submit_error(s->cookie_tx)) { 590 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 591 /* Switch irq from SCIF to DMA */ 592 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]); 593 594 s->cookie_tx = 0; 595 schedule_work(&s->work_tx); 596 } 597#endif 598 599 if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE || 600 port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 601 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ 602 ctrl = serial_port_in(port, SCSCR); 603 604 /* 605 * For SCI, TE (transmit enable) must be set after setting TIE 606 * (transmit interrupt enable) or in the same instruction to start 607 * the transmit process. 608 */ 609 if (port->type == PORT_SCI) 610 ctrl |= SCSCR_TE; 611 612 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); 613 } 614} 615 616static void sci_stop_tx(struct uart_port *port) 617{ 618 unsigned short ctrl; 619 620 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ 621 ctrl = serial_port_in(port, SCSCR); 622 623 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 624 ctrl &= ~SCSCR_TDRQE; 625 626 ctrl &= ~SCSCR_TIE; 627 628 serial_port_out(port, SCSCR, ctrl); 629 630#ifdef CONFIG_SERIAL_SH_SCI_DMA 631 if (to_sci_port(port)->chan_tx && 632 !dma_submit_error(to_sci_port(port)->cookie_tx)) { 633 dmaengine_terminate_async(to_sci_port(port)->chan_tx); 634 to_sci_port(port)->cookie_tx = -EINVAL; 635 } 636#endif 637} 638 639static void sci_start_rx(struct uart_port *port) 640{ 641 unsigned short ctrl; 642 643 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); 644 645 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 646 ctrl &= ~SCSCR_RDRQE; 647 648 serial_port_out(port, SCSCR, ctrl); 649} 650 651static void sci_stop_rx(struct uart_port *port) 652{ 653 unsigned short ctrl; 654 655 ctrl = serial_port_in(port, SCSCR); 656 657 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 658 ctrl &= ~SCSCR_RDRQE; 659 660 ctrl &= ~port_rx_irq_mask(port); 661 662 serial_port_out(port, SCSCR, ctrl); 663} 664 665static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) 666{ 667 if (port->type == PORT_SCI) { 668 /* Just store the mask */ 669 serial_port_out(port, SCxSR, mask); 670 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) { 671 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ 672 /* Only clear the status bits we want to clear */ 673 serial_port_out(port, SCxSR, 674 serial_port_in(port, SCxSR) & mask); 675 } else { 676 /* Store the mask, clear parity/framing errors */ 677 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); 678 } 679} 680 681#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 682 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 683 684#ifdef CONFIG_CONSOLE_POLL 685static int sci_poll_get_char(struct uart_port *port) 686{ 687 unsigned short status; 688 int c; 689 690 do { 691 status = serial_port_in(port, SCxSR); 692 if (status & SCxSR_ERRORS(port)) { 693 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 694 continue; 695 } 696 break; 697 } while (1); 698 699 if (!(status & SCxSR_RDxF(port))) 700 return NO_POLL_CHAR; 701 702 c = serial_port_in(port, SCxRDR); 703 704 /* Dummy read */ 705 serial_port_in(port, SCxSR); 706 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 707 708 return c; 709} 710#endif 711 712static void sci_poll_put_char(struct uart_port *port, unsigned char c) 713{ 714 unsigned short status; 715 716 do { 717 status = serial_port_in(port, SCxSR); 718 } while (!(status & SCxSR_TDxE(port))); 719 720 serial_port_out(port, SCxTDR, c); 721 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); 722} 723#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || 724 CONFIG_SERIAL_SH_SCI_EARLYCON */ 725 726static void sci_init_pins(struct uart_port *port, unsigned int cflag) 727{ 728 struct sci_port *s = to_sci_port(port); 729 730 /* 731 * Use port-specific handler if provided. 732 */ 733 if (s->cfg->ops && s->cfg->ops->init_pins) { 734 s->cfg->ops->init_pins(port, cflag); 735 return; 736 } 737 738 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 739 u16 data = serial_port_in(port, SCPDR); 740 u16 ctrl = serial_port_in(port, SCPCR); 741 742 /* Enable RXD and TXD pin functions */ 743 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC); 744 if (to_sci_port(port)->has_rtscts) { 745 /* RTS# is output, active low, unless autorts */ 746 if (!(port->mctrl & TIOCM_RTS)) { 747 ctrl |= SCPCR_RTSC; 748 data |= SCPDR_RTSD; 749 } else if (!s->autorts) { 750 ctrl |= SCPCR_RTSC; 751 data &= ~SCPDR_RTSD; 752 } else { 753 /* Enable RTS# pin function */ 754 ctrl &= ~SCPCR_RTSC; 755 } 756 /* Enable CTS# pin function */ 757 ctrl &= ~SCPCR_CTSC; 758 } 759 serial_port_out(port, SCPDR, data); 760 serial_port_out(port, SCPCR, ctrl); 761 } else if (sci_getreg(port, SCSPTR)->size) { 762 u16 status = serial_port_in(port, SCSPTR); 763 764 /* RTS# is always output; and active low, unless autorts */ 765 status |= SCSPTR_RTSIO; 766 if (!(port->mctrl & TIOCM_RTS)) 767 status |= SCSPTR_RTSDT; 768 else if (!s->autorts) 769 status &= ~SCSPTR_RTSDT; 770 /* CTS# and SCK are inputs */ 771 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO); 772 serial_port_out(port, SCSPTR, status); 773 } 774} 775 776static int sci_txfill(struct uart_port *port) 777{ 778 struct sci_port *s = to_sci_port(port); 779 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 780 const struct plat_sci_reg *reg; 781 782 reg = sci_getreg(port, SCTFDR); 783 if (reg->size) 784 return serial_port_in(port, SCTFDR) & fifo_mask; 785 786 reg = sci_getreg(port, SCFDR); 787 if (reg->size) 788 return serial_port_in(port, SCFDR) >> 8; 789 790 return !(serial_port_in(port, SCxSR) & SCI_TDRE); 791} 792 793static int sci_txroom(struct uart_port *port) 794{ 795 return port->fifosize - sci_txfill(port); 796} 797 798static int sci_rxfill(struct uart_port *port) 799{ 800 struct sci_port *s = to_sci_port(port); 801 unsigned int fifo_mask = (s->params->fifosize << 1) - 1; 802 const struct plat_sci_reg *reg; 803 804 reg = sci_getreg(port, SCRFDR); 805 if (reg->size) 806 return serial_port_in(port, SCRFDR) & fifo_mask; 807 808 reg = sci_getreg(port, SCFDR); 809 if (reg->size) 810 return serial_port_in(port, SCFDR) & fifo_mask; 811 812 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; 813} 814 815/* ********************************************************************** * 816 * the interrupt related routines * 817 * ********************************************************************** */ 818 819static void sci_transmit_chars(struct uart_port *port) 820{ 821 struct circ_buf *xmit = &port->state->xmit; 822 unsigned int stopped = uart_tx_stopped(port); 823 unsigned short status; 824 unsigned short ctrl; 825 int count; 826 827 status = serial_port_in(port, SCxSR); 828 if (!(status & SCxSR_TDxE(port))) { 829 ctrl = serial_port_in(port, SCSCR); 830 if (uart_circ_empty(xmit)) 831 ctrl &= ~SCSCR_TIE; 832 else 833 ctrl |= SCSCR_TIE; 834 serial_port_out(port, SCSCR, ctrl); 835 return; 836 } 837 838 count = sci_txroom(port); 839 840 do { 841 unsigned char c; 842 843 if (port->x_char) { 844 c = port->x_char; 845 port->x_char = 0; 846 } else if (!uart_circ_empty(xmit) && !stopped) { 847 c = xmit->buf[xmit->tail]; 848 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 849 } else if (port->type == PORT_SCI && uart_circ_empty(xmit)) { 850 ctrl = serial_port_in(port, SCSCR); 851 ctrl &= ~SCSCR_TE; 852 serial_port_out(port, SCSCR, ctrl); 853 return; 854 } else { 855 break; 856 } 857 858 serial_port_out(port, SCxTDR, c); 859 860 port->icount.tx++; 861 } while (--count > 0); 862 863 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); 864 865 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 866 uart_write_wakeup(port); 867 if (uart_circ_empty(xmit)) { 868 if (port->type == PORT_SCI) { 869 ctrl = serial_port_in(port, SCSCR); 870 ctrl &= ~SCSCR_TIE; 871 ctrl |= SCSCR_TEIE; 872 serial_port_out(port, SCSCR, ctrl); 873 } 874 875 sci_stop_tx(port); 876 } 877} 878 879static void sci_receive_chars(struct uart_port *port) 880{ 881 struct tty_port *tport = &port->state->port; 882 int i, count, copied = 0; 883 unsigned short status; 884 unsigned char flag; 885 886 status = serial_port_in(port, SCxSR); 887 if (!(status & SCxSR_RDxF(port))) 888 return; 889 890 while (1) { 891 /* Don't copy more bytes than there is room for in the buffer */ 892 count = tty_buffer_request_room(tport, sci_rxfill(port)); 893 894 /* If for any reason we can't copy more data, we're done! */ 895 if (count == 0) 896 break; 897 898 if (port->type == PORT_SCI) { 899 char c = serial_port_in(port, SCxRDR); 900 if (uart_handle_sysrq_char(port, c)) 901 count = 0; 902 else 903 tty_insert_flip_char(tport, c, TTY_NORMAL); 904 } else { 905 for (i = 0; i < count; i++) { 906 char c; 907 908 if (port->type == PORT_SCIF || 909 port->type == PORT_HSCIF) { 910 status = serial_port_in(port, SCxSR); 911 c = serial_port_in(port, SCxRDR); 912 } else { 913 c = serial_port_in(port, SCxRDR); 914 status = serial_port_in(port, SCxSR); 915 } 916 if (uart_handle_sysrq_char(port, c)) { 917 count--; i--; 918 continue; 919 } 920 921 /* Store data and status */ 922 if (status & SCxSR_FER(port)) { 923 flag = TTY_FRAME; 924 port->icount.frame++; 925 } else if (status & SCxSR_PER(port)) { 926 flag = TTY_PARITY; 927 port->icount.parity++; 928 } else 929 flag = TTY_NORMAL; 930 931 tty_insert_flip_char(tport, c, flag); 932 } 933 } 934 935 serial_port_in(port, SCxSR); /* dummy read */ 936 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 937 938 copied += count; 939 port->icount.rx += count; 940 } 941 942 if (copied) { 943 /* Tell the rest of the system the news. New characters! */ 944 tty_flip_buffer_push(tport); 945 } else { 946 /* TTY buffers full; read from RX reg to prevent lockup */ 947 serial_port_in(port, SCxRDR); 948 serial_port_in(port, SCxSR); /* dummy read */ 949 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 950 } 951} 952 953static int sci_handle_errors(struct uart_port *port) 954{ 955 int copied = 0; 956 unsigned short status = serial_port_in(port, SCxSR); 957 struct tty_port *tport = &port->state->port; 958 struct sci_port *s = to_sci_port(port); 959 960 /* Handle overruns */ 961 if (status & s->params->overrun_mask) { 962 port->icount.overrun++; 963 964 /* overrun error */ 965 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) 966 copied++; 967 } 968 969 if (status & SCxSR_FER(port)) { 970 /* frame error */ 971 port->icount.frame++; 972 973 if (tty_insert_flip_char(tport, 0, TTY_FRAME)) 974 copied++; 975 } 976 977 if (status & SCxSR_PER(port)) { 978 /* parity error */ 979 port->icount.parity++; 980 981 if (tty_insert_flip_char(tport, 0, TTY_PARITY)) 982 copied++; 983 } 984 985 if (copied) 986 tty_flip_buffer_push(tport); 987 988 return copied; 989} 990 991static int sci_handle_fifo_overrun(struct uart_port *port) 992{ 993 struct tty_port *tport = &port->state->port; 994 struct sci_port *s = to_sci_port(port); 995 const struct plat_sci_reg *reg; 996 int copied = 0; 997 u16 status; 998 999 reg = sci_getreg(port, s->params->overrun_reg); 1000 if (!reg->size) 1001 return 0; 1002 1003 status = serial_port_in(port, s->params->overrun_reg); 1004 if (status & s->params->overrun_mask) { 1005 status &= ~s->params->overrun_mask; 1006 serial_port_out(port, s->params->overrun_reg, status); 1007 1008 port->icount.overrun++; 1009 1010 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 1011 tty_flip_buffer_push(tport); 1012 copied++; 1013 } 1014 1015 return copied; 1016} 1017 1018static int sci_handle_breaks(struct uart_port *port) 1019{ 1020 int copied = 0; 1021 unsigned short status = serial_port_in(port, SCxSR); 1022 struct tty_port *tport = &port->state->port; 1023 1024 if (uart_handle_break(port)) 1025 return 0; 1026 1027 if (status & SCxSR_BRK(port)) { 1028 port->icount.brk++; 1029 1030 /* Notify of BREAK */ 1031 if (tty_insert_flip_char(tport, 0, TTY_BREAK)) 1032 copied++; 1033 } 1034 1035 if (copied) 1036 tty_flip_buffer_push(tport); 1037 1038 copied += sci_handle_fifo_overrun(port); 1039 1040 return copied; 1041} 1042 1043static int scif_set_rtrg(struct uart_port *port, int rx_trig) 1044{ 1045 unsigned int bits; 1046 1047 if (rx_trig >= port->fifosize) 1048 rx_trig = port->fifosize - 1; 1049 if (rx_trig < 1) 1050 rx_trig = 1; 1051 1052 /* HSCIF can be set to an arbitrary level. */ 1053 if (sci_getreg(port, HSRTRGR)->size) { 1054 serial_port_out(port, HSRTRGR, rx_trig); 1055 return rx_trig; 1056 } 1057 1058 switch (port->type) { 1059 case PORT_SCIF: 1060 if (rx_trig < 4) { 1061 bits = 0; 1062 rx_trig = 1; 1063 } else if (rx_trig < 8) { 1064 bits = SCFCR_RTRG0; 1065 rx_trig = 4; 1066 } else if (rx_trig < 14) { 1067 bits = SCFCR_RTRG1; 1068 rx_trig = 8; 1069 } else { 1070 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1071 rx_trig = 14; 1072 } 1073 break; 1074 case PORT_SCIFA: 1075 case PORT_SCIFB: 1076 if (rx_trig < 16) { 1077 bits = 0; 1078 rx_trig = 1; 1079 } else if (rx_trig < 32) { 1080 bits = SCFCR_RTRG0; 1081 rx_trig = 16; 1082 } else if (rx_trig < 48) { 1083 bits = SCFCR_RTRG1; 1084 rx_trig = 32; 1085 } else { 1086 bits = SCFCR_RTRG0 | SCFCR_RTRG1; 1087 rx_trig = 48; 1088 } 1089 break; 1090 default: 1091 WARN(1, "unknown FIFO configuration"); 1092 return 1; 1093 } 1094 1095 serial_port_out(port, SCFCR, 1096 (serial_port_in(port, SCFCR) & 1097 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits); 1098 1099 return rx_trig; 1100} 1101 1102static int scif_rtrg_enabled(struct uart_port *port) 1103{ 1104 if (sci_getreg(port, HSRTRGR)->size) 1105 return serial_port_in(port, HSRTRGR) != 0; 1106 else 1107 return (serial_port_in(port, SCFCR) & 1108 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0; 1109} 1110 1111static void rx_fifo_timer_fn(struct timer_list *t) 1112{ 1113 struct sci_port *s = from_timer(s, t, rx_fifo_timer); 1114 struct uart_port *port = &s->port; 1115 1116 dev_dbg(port->dev, "Rx timed out\n"); 1117 scif_set_rtrg(port, 1); 1118} 1119 1120static ssize_t rx_fifo_trigger_show(struct device *dev, 1121 struct device_attribute *attr, char *buf) 1122{ 1123 struct uart_port *port = dev_get_drvdata(dev); 1124 struct sci_port *sci = to_sci_port(port); 1125 1126 return sprintf(buf, "%d\n", sci->rx_trigger); 1127} 1128 1129static ssize_t rx_fifo_trigger_store(struct device *dev, 1130 struct device_attribute *attr, 1131 const char *buf, size_t count) 1132{ 1133 struct uart_port *port = dev_get_drvdata(dev); 1134 struct sci_port *sci = to_sci_port(port); 1135 int ret; 1136 long r; 1137 1138 ret = kstrtol(buf, 0, &r); 1139 if (ret) 1140 return ret; 1141 1142 sci->rx_trigger = scif_set_rtrg(port, r); 1143 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 1144 scif_set_rtrg(port, 1); 1145 1146 return count; 1147} 1148 1149static DEVICE_ATTR_RW(rx_fifo_trigger); 1150 1151static ssize_t rx_fifo_timeout_show(struct device *dev, 1152 struct device_attribute *attr, 1153 char *buf) 1154{ 1155 struct uart_port *port = dev_get_drvdata(dev); 1156 struct sci_port *sci = to_sci_port(port); 1157 int v; 1158 1159 if (port->type == PORT_HSCIF) 1160 v = sci->hscif_tot >> HSSCR_TOT_SHIFT; 1161 else 1162 v = sci->rx_fifo_timeout; 1163 1164 return sprintf(buf, "%d\n", v); 1165} 1166 1167static ssize_t rx_fifo_timeout_store(struct device *dev, 1168 struct device_attribute *attr, 1169 const char *buf, 1170 size_t count) 1171{ 1172 struct uart_port *port = dev_get_drvdata(dev); 1173 struct sci_port *sci = to_sci_port(port); 1174 int ret; 1175 long r; 1176 1177 ret = kstrtol(buf, 0, &r); 1178 if (ret) 1179 return ret; 1180 1181 if (port->type == PORT_HSCIF) { 1182 if (r < 0 || r > 3) 1183 return -EINVAL; 1184 sci->hscif_tot = r << HSSCR_TOT_SHIFT; 1185 } else { 1186 sci->rx_fifo_timeout = r; 1187 scif_set_rtrg(port, 1); 1188 if (r > 0) 1189 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0); 1190 } 1191 1192 return count; 1193} 1194 1195static DEVICE_ATTR_RW(rx_fifo_timeout); 1196 1197 1198#ifdef CONFIG_SERIAL_SH_SCI_DMA 1199static void sci_dma_tx_complete(void *arg) 1200{ 1201 struct sci_port *s = arg; 1202 struct uart_port *port = &s->port; 1203 struct circ_buf *xmit = &port->state->xmit; 1204 unsigned long flags; 1205 1206 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1207 1208 spin_lock_irqsave(&port->lock, flags); 1209 1210 uart_xmit_advance(port, s->tx_dma_len); 1211 1212 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1213 uart_write_wakeup(port); 1214 1215 if (!uart_circ_empty(xmit)) { 1216 s->cookie_tx = 0; 1217 schedule_work(&s->work_tx); 1218 } else { 1219 s->cookie_tx = -EINVAL; 1220 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1221 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1222 u16 ctrl = serial_port_in(port, SCSCR); 1223 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); 1224 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1225 /* Switch irq from DMA to SCIF */ 1226 dmaengine_pause(s->chan_tx_saved); 1227 enable_irq(s->irqs[SCIx_TXI_IRQ]); 1228 } 1229 } 1230 } 1231 1232 spin_unlock_irqrestore(&port->lock, flags); 1233} 1234 1235/* Locking: called with port lock held */ 1236static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) 1237{ 1238 struct uart_port *port = &s->port; 1239 struct tty_port *tport = &port->state->port; 1240 int copied; 1241 1242 copied = tty_insert_flip_string(tport, buf, count); 1243 if (copied < count) 1244 port->icount.buf_overrun++; 1245 1246 port->icount.rx += copied; 1247 1248 return copied; 1249} 1250 1251static int sci_dma_rx_find_active(struct sci_port *s) 1252{ 1253 unsigned int i; 1254 1255 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1256 if (s->active_rx == s->cookie_rx[i]) 1257 return i; 1258 1259 return -1; 1260} 1261 1262static void sci_dma_rx_chan_invalidate(struct sci_port *s) 1263{ 1264 unsigned int i; 1265 1266 s->chan_rx = NULL; 1267 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) 1268 s->cookie_rx[i] = -EINVAL; 1269 s->active_rx = 0; 1270} 1271 1272static void sci_dma_rx_release(struct sci_port *s) 1273{ 1274 struct dma_chan *chan = s->chan_rx_saved; 1275 1276 s->chan_rx_saved = NULL; 1277 sci_dma_rx_chan_invalidate(s); 1278 dmaengine_terminate_sync(chan); 1279 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], 1280 sg_dma_address(&s->sg_rx[0])); 1281 dma_release_channel(chan); 1282} 1283 1284static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec) 1285{ 1286 long sec = usec / 1000000; 1287 long nsec = (usec % 1000000) * 1000; 1288 ktime_t t = ktime_set(sec, nsec); 1289 1290 hrtimer_start(hrt, t, HRTIMER_MODE_REL); 1291} 1292 1293static void sci_dma_rx_reenable_irq(struct sci_port *s) 1294{ 1295 struct uart_port *port = &s->port; 1296 u16 scr; 1297 1298 /* Direct new serial port interrupts back to CPU */ 1299 scr = serial_port_in(port, SCSCR); 1300 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1301 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1302 enable_irq(s->irqs[SCIx_RXI_IRQ]); 1303 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1304 scif_set_rtrg(port, s->rx_trigger); 1305 else 1306 scr &= ~SCSCR_RDRQE; 1307 } 1308 serial_port_out(port, SCSCR, scr | SCSCR_RIE); 1309} 1310 1311static void sci_dma_rx_complete(void *arg) 1312{ 1313 struct sci_port *s = arg; 1314 struct dma_chan *chan = s->chan_rx; 1315 struct uart_port *port = &s->port; 1316 struct dma_async_tx_descriptor *desc; 1317 unsigned long flags; 1318 int active, count = 0; 1319 1320 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1321 s->active_rx); 1322 1323 spin_lock_irqsave(&port->lock, flags); 1324 1325 active = sci_dma_rx_find_active(s); 1326 if (active >= 0) 1327 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); 1328 1329 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1330 1331 if (count) 1332 tty_flip_buffer_push(&port->state->port); 1333 1334 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, 1335 DMA_DEV_TO_MEM, 1336 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1337 if (!desc) 1338 goto fail; 1339 1340 desc->callback = sci_dma_rx_complete; 1341 desc->callback_param = s; 1342 s->cookie_rx[active] = dmaengine_submit(desc); 1343 if (dma_submit_error(s->cookie_rx[active])) 1344 goto fail; 1345 1346 s->active_rx = s->cookie_rx[!active]; 1347 1348 dma_async_issue_pending(chan); 1349 1350 spin_unlock_irqrestore(&port->lock, flags); 1351 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1352 __func__, s->cookie_rx[active], active, s->active_rx); 1353 return; 1354 1355fail: 1356 spin_unlock_irqrestore(&port->lock, flags); 1357 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1358 /* Switch to PIO */ 1359 spin_lock_irqsave(&port->lock, flags); 1360 dmaengine_terminate_async(chan); 1361 sci_dma_rx_chan_invalidate(s); 1362 sci_dma_rx_reenable_irq(s); 1363 spin_unlock_irqrestore(&port->lock, flags); 1364} 1365 1366static void sci_dma_tx_release(struct sci_port *s) 1367{ 1368 struct dma_chan *chan = s->chan_tx_saved; 1369 1370 cancel_work_sync(&s->work_tx); 1371 s->chan_tx_saved = s->chan_tx = NULL; 1372 s->cookie_tx = -EINVAL; 1373 dmaengine_terminate_sync(chan); 1374 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, 1375 DMA_TO_DEVICE); 1376 dma_release_channel(chan); 1377} 1378 1379static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held) 1380{ 1381 struct dma_chan *chan = s->chan_rx; 1382 struct uart_port *port = &s->port; 1383 unsigned long flags; 1384 int i; 1385 1386 for (i = 0; i < 2; i++) { 1387 struct scatterlist *sg = &s->sg_rx[i]; 1388 struct dma_async_tx_descriptor *desc; 1389 1390 desc = dmaengine_prep_slave_sg(chan, 1391 sg, 1, DMA_DEV_TO_MEM, 1392 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1393 if (!desc) 1394 goto fail; 1395 1396 desc->callback = sci_dma_rx_complete; 1397 desc->callback_param = s; 1398 s->cookie_rx[i] = dmaengine_submit(desc); 1399 if (dma_submit_error(s->cookie_rx[i])) 1400 goto fail; 1401 1402 } 1403 1404 s->active_rx = s->cookie_rx[0]; 1405 1406 dma_async_issue_pending(chan); 1407 return 0; 1408 1409fail: 1410 /* Switch to PIO */ 1411 if (!port_lock_held) 1412 spin_lock_irqsave(&port->lock, flags); 1413 if (i) 1414 dmaengine_terminate_async(chan); 1415 sci_dma_rx_chan_invalidate(s); 1416 sci_start_rx(port); 1417 if (!port_lock_held) 1418 spin_unlock_irqrestore(&port->lock, flags); 1419 return -EAGAIN; 1420} 1421 1422static void sci_dma_tx_work_fn(struct work_struct *work) 1423{ 1424 struct sci_port *s = container_of(work, struct sci_port, work_tx); 1425 struct dma_async_tx_descriptor *desc; 1426 struct dma_chan *chan = s->chan_tx; 1427 struct uart_port *port = &s->port; 1428 struct circ_buf *xmit = &port->state->xmit; 1429 unsigned long flags; 1430 dma_addr_t buf; 1431 int head, tail; 1432 1433 /* 1434 * DMA is idle now. 1435 * Port xmit buffer is already mapped, and it is one page... Just adjust 1436 * offsets and lengths. Since it is a circular buffer, we have to 1437 * transmit till the end, and then the rest. Take the port lock to get a 1438 * consistent xmit buffer state. 1439 */ 1440 spin_lock_irq(&port->lock); 1441 head = xmit->head; 1442 tail = xmit->tail; 1443 buf = s->tx_dma_addr + tail; 1444 s->tx_dma_len = CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE); 1445 if (!s->tx_dma_len) { 1446 /* Transmit buffer has been flushed */ 1447 spin_unlock_irq(&port->lock); 1448 return; 1449 } 1450 1451 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, 1452 DMA_MEM_TO_DEV, 1453 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1454 if (!desc) { 1455 spin_unlock_irq(&port->lock); 1456 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1457 goto switch_to_pio; 1458 } 1459 1460 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, 1461 DMA_TO_DEVICE); 1462 1463 desc->callback = sci_dma_tx_complete; 1464 desc->callback_param = s; 1465 s->cookie_tx = dmaengine_submit(desc); 1466 if (dma_submit_error(s->cookie_tx)) { 1467 spin_unlock_irq(&port->lock); 1468 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1469 goto switch_to_pio; 1470 } 1471 1472 spin_unlock_irq(&port->lock); 1473 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1474 __func__, xmit->buf, tail, head, s->cookie_tx); 1475 1476 dma_async_issue_pending(chan); 1477 return; 1478 1479switch_to_pio: 1480 spin_lock_irqsave(&port->lock, flags); 1481 s->chan_tx = NULL; 1482 sci_start_tx(port); 1483 spin_unlock_irqrestore(&port->lock, flags); 1484 return; 1485} 1486 1487static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t) 1488{ 1489 struct sci_port *s = container_of(t, struct sci_port, rx_timer); 1490 struct dma_chan *chan = s->chan_rx; 1491 struct uart_port *port = &s->port; 1492 struct dma_tx_state state; 1493 enum dma_status status; 1494 unsigned long flags; 1495 unsigned int read; 1496 int active, count; 1497 1498 dev_dbg(port->dev, "DMA Rx timed out\n"); 1499 1500 spin_lock_irqsave(&port->lock, flags); 1501 1502 active = sci_dma_rx_find_active(s); 1503 if (active < 0) { 1504 spin_unlock_irqrestore(&port->lock, flags); 1505 return HRTIMER_NORESTART; 1506 } 1507 1508 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1509 if (status == DMA_COMPLETE) { 1510 spin_unlock_irqrestore(&port->lock, flags); 1511 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1512 s->active_rx, active); 1513 1514 /* Let packet complete handler take care of the packet */ 1515 return HRTIMER_NORESTART; 1516 } 1517 1518 dmaengine_pause(chan); 1519 1520 /* 1521 * sometimes DMA transfer doesn't stop even if it is stopped and 1522 * data keeps on coming until transaction is complete so check 1523 * for DMA_COMPLETE again 1524 * Let packet complete handler take care of the packet 1525 */ 1526 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1527 if (status == DMA_COMPLETE) { 1528 spin_unlock_irqrestore(&port->lock, flags); 1529 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1530 return HRTIMER_NORESTART; 1531 } 1532 1533 /* Handle incomplete DMA receive */ 1534 dmaengine_terminate_async(s->chan_rx); 1535 read = sg_dma_len(&s->sg_rx[active]) - state.residue; 1536 1537 if (read) { 1538 count = sci_dma_rx_push(s, s->rx_buf[active], read); 1539 if (count) 1540 tty_flip_buffer_push(&port->state->port); 1541 } 1542 1543 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1544 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1545 sci_dma_rx_submit(s, true); 1546 1547 sci_dma_rx_reenable_irq(s); 1548 1549 spin_unlock_irqrestore(&port->lock, flags); 1550 1551 return HRTIMER_NORESTART; 1552} 1553 1554static struct dma_chan *sci_request_dma_chan(struct uart_port *port, 1555 enum dma_transfer_direction dir) 1556{ 1557 struct dma_chan *chan; 1558 struct dma_slave_config cfg; 1559 int ret; 1560 1561 chan = dma_request_slave_channel(port->dev, 1562 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1563 if (!chan) { 1564 dev_dbg(port->dev, "dma_request_slave_channel failed\n"); 1565 return NULL; 1566 } 1567 1568 memset(&cfg, 0, sizeof(cfg)); 1569 cfg.direction = dir; 1570 cfg.dst_addr = port->mapbase + 1571 (sci_getreg(port, SCxTDR)->offset << port->regshift); 1572 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1573 cfg.src_addr = port->mapbase + 1574 (sci_getreg(port, SCxRDR)->offset << port->regshift); 1575 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1576 1577 ret = dmaengine_slave_config(chan, &cfg); 1578 if (ret) { 1579 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); 1580 dma_release_channel(chan); 1581 return NULL; 1582 } 1583 1584 return chan; 1585} 1586 1587static void sci_request_dma(struct uart_port *port) 1588{ 1589 struct sci_port *s = to_sci_port(port); 1590 struct dma_chan *chan; 1591 1592 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); 1593 1594 /* 1595 * DMA on console may interfere with Kernel log messages which use 1596 * plain putchar(). So, simply don't use it with a console. 1597 */ 1598 if (uart_console(port)) 1599 return; 1600 1601 if (!port->dev->of_node) 1602 return; 1603 1604 s->cookie_tx = -EINVAL; 1605 1606 /* 1607 * Don't request a dma channel if no channel was specified 1608 * in the device tree. 1609 */ 1610 if (!of_property_present(port->dev->of_node, "dmas")) 1611 return; 1612 1613 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV); 1614 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); 1615 if (chan) { 1616 /* UART circular tx buffer is an aligned page. */ 1617 s->tx_dma_addr = dma_map_single(chan->device->dev, 1618 port->state->xmit.buf, 1619 UART_XMIT_SIZE, 1620 DMA_TO_DEVICE); 1621 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { 1622 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); 1623 dma_release_channel(chan); 1624 } else { 1625 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", 1626 __func__, UART_XMIT_SIZE, 1627 port->state->xmit.buf, &s->tx_dma_addr); 1628 1629 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn); 1630 s->chan_tx_saved = s->chan_tx = chan; 1631 } 1632 } 1633 1634 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM); 1635 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); 1636 if (chan) { 1637 unsigned int i; 1638 dma_addr_t dma; 1639 void *buf; 1640 1641 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); 1642 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, 1643 &dma, GFP_KERNEL); 1644 if (!buf) { 1645 dev_warn(port->dev, 1646 "Failed to allocate Rx dma buffer, using PIO\n"); 1647 dma_release_channel(chan); 1648 return; 1649 } 1650 1651 for (i = 0; i < 2; i++) { 1652 struct scatterlist *sg = &s->sg_rx[i]; 1653 1654 sg_init_table(sg, 1); 1655 s->rx_buf[i] = buf; 1656 sg_dma_address(sg) = dma; 1657 sg_dma_len(sg) = s->buf_len_rx; 1658 1659 buf += s->buf_len_rx; 1660 dma += s->buf_len_rx; 1661 } 1662 1663 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 1664 s->rx_timer.function = sci_dma_rx_timer_fn; 1665 1666 s->chan_rx_saved = s->chan_rx = chan; 1667 1668 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1669 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) 1670 sci_dma_rx_submit(s, false); 1671 } 1672} 1673 1674static void sci_free_dma(struct uart_port *port) 1675{ 1676 struct sci_port *s = to_sci_port(port); 1677 1678 if (s->chan_tx_saved) 1679 sci_dma_tx_release(s); 1680 if (s->chan_rx_saved) 1681 sci_dma_rx_release(s); 1682} 1683 1684static void sci_flush_buffer(struct uart_port *port) 1685{ 1686 struct sci_port *s = to_sci_port(port); 1687 1688 /* 1689 * In uart_flush_buffer(), the xmit circular buffer has just been 1690 * cleared, so we have to reset tx_dma_len accordingly, and stop any 1691 * pending transfers 1692 */ 1693 s->tx_dma_len = 0; 1694 if (s->chan_tx) { 1695 dmaengine_terminate_async(s->chan_tx); 1696 s->cookie_tx = -EINVAL; 1697 } 1698} 1699#else /* !CONFIG_SERIAL_SH_SCI_DMA */ 1700static inline void sci_request_dma(struct uart_port *port) 1701{ 1702} 1703 1704static inline void sci_free_dma(struct uart_port *port) 1705{ 1706} 1707 1708#define sci_flush_buffer NULL 1709#endif /* !CONFIG_SERIAL_SH_SCI_DMA */ 1710 1711static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 1712{ 1713 struct uart_port *port = ptr; 1714 struct sci_port *s = to_sci_port(port); 1715 1716#ifdef CONFIG_SERIAL_SH_SCI_DMA 1717 if (s->chan_rx) { 1718 u16 scr = serial_port_in(port, SCSCR); 1719 u16 ssr = serial_port_in(port, SCxSR); 1720 1721 /* Disable future Rx interrupts */ 1722 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB || 1723 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1724 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]); 1725 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) { 1726 scif_set_rtrg(port, 1); 1727 scr |= SCSCR_RIE; 1728 } else { 1729 scr |= SCSCR_RDRQE; 1730 } 1731 } else { 1732 if (sci_dma_rx_submit(s, false) < 0) 1733 goto handle_pio; 1734 1735 scr &= ~SCSCR_RIE; 1736 } 1737 serial_port_out(port, SCSCR, scr); 1738 /* Clear current interrupt */ 1739 serial_port_out(port, SCxSR, 1740 ssr & ~(SCIF_DR | SCxSR_RDxF(port))); 1741 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n", 1742 jiffies, s->rx_timeout); 1743 start_hrtimer_us(&s->rx_timer, s->rx_timeout); 1744 1745 return IRQ_HANDLED; 1746 } 1747 1748handle_pio: 1749#endif 1750 1751 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) { 1752 if (!scif_rtrg_enabled(port)) 1753 scif_set_rtrg(port, s->rx_trigger); 1754 1755 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP( 1756 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000)); 1757 } 1758 1759 /* I think sci_receive_chars has to be called irrespective 1760 * of whether the I_IXOFF is set, otherwise, how is the interrupt 1761 * to be disabled? 1762 */ 1763 sci_receive_chars(port); 1764 1765 return IRQ_HANDLED; 1766} 1767 1768static irqreturn_t sci_tx_interrupt(int irq, void *ptr) 1769{ 1770 struct uart_port *port = ptr; 1771 unsigned long flags; 1772 1773 spin_lock_irqsave(&port->lock, flags); 1774 sci_transmit_chars(port); 1775 spin_unlock_irqrestore(&port->lock, flags); 1776 1777 return IRQ_HANDLED; 1778} 1779 1780static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr) 1781{ 1782 struct uart_port *port = ptr; 1783 unsigned long flags; 1784 unsigned short ctrl; 1785 1786 if (port->type != PORT_SCI) 1787 return sci_tx_interrupt(irq, ptr); 1788 1789 spin_lock_irqsave(&port->lock, flags); 1790 ctrl = serial_port_in(port, SCSCR); 1791 ctrl &= ~(SCSCR_TE | SCSCR_TEIE); 1792 serial_port_out(port, SCSCR, ctrl); 1793 spin_unlock_irqrestore(&port->lock, flags); 1794 1795 return IRQ_HANDLED; 1796} 1797 1798static irqreturn_t sci_br_interrupt(int irq, void *ptr) 1799{ 1800 struct uart_port *port = ptr; 1801 1802 /* Handle BREAKs */ 1803 sci_handle_breaks(port); 1804 1805 /* drop invalid character received before break was detected */ 1806 serial_port_in(port, SCxRDR); 1807 1808 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); 1809 1810 return IRQ_HANDLED; 1811} 1812 1813static irqreturn_t sci_er_interrupt(int irq, void *ptr) 1814{ 1815 struct uart_port *port = ptr; 1816 struct sci_port *s = to_sci_port(port); 1817 1818 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) { 1819 /* Break and Error interrupts are muxed */ 1820 unsigned short ssr_status = serial_port_in(port, SCxSR); 1821 1822 /* Break Interrupt */ 1823 if (ssr_status & SCxSR_BRK(port)) 1824 sci_br_interrupt(irq, ptr); 1825 1826 /* Break only? */ 1827 if (!(ssr_status & SCxSR_ERRORS(port))) 1828 return IRQ_HANDLED; 1829 } 1830 1831 /* Handle errors */ 1832 if (port->type == PORT_SCI) { 1833 if (sci_handle_errors(port)) { 1834 /* discard character in rx buffer */ 1835 serial_port_in(port, SCxSR); 1836 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); 1837 } 1838 } else { 1839 sci_handle_fifo_overrun(port); 1840 if (!s->chan_rx) 1841 sci_receive_chars(port); 1842 } 1843 1844 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); 1845 1846 /* Kick the transmission */ 1847 if (!s->chan_tx) 1848 sci_tx_interrupt(irq, ptr); 1849 1850 return IRQ_HANDLED; 1851} 1852 1853static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) 1854{ 1855 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; 1856 struct uart_port *port = ptr; 1857 struct sci_port *s = to_sci_port(port); 1858 irqreturn_t ret = IRQ_NONE; 1859 1860 ssr_status = serial_port_in(port, SCxSR); 1861 scr_status = serial_port_in(port, SCSCR); 1862 if (s->params->overrun_reg == SCxSR) 1863 orer_status = ssr_status; 1864 else if (sci_getreg(port, s->params->overrun_reg)->size) 1865 orer_status = serial_port_in(port, s->params->overrun_reg); 1866 1867 err_enabled = scr_status & port_rx_irq_mask(port); 1868 1869 /* Tx Interrupt */ 1870 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && 1871 !s->chan_tx) 1872 ret = sci_tx_interrupt(irq, ptr); 1873 1874 /* 1875 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / 1876 * DR flags 1877 */ 1878 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && 1879 (scr_status & SCSCR_RIE)) 1880 ret = sci_rx_interrupt(irq, ptr); 1881 1882 /* Error Interrupt */ 1883 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) 1884 ret = sci_er_interrupt(irq, ptr); 1885 1886 /* Break Interrupt */ 1887 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] && 1888 (ssr_status & SCxSR_BRK(port)) && err_enabled) 1889 ret = sci_br_interrupt(irq, ptr); 1890 1891 /* Overrun Interrupt */ 1892 if (orer_status & s->params->overrun_mask) { 1893 sci_handle_fifo_overrun(port); 1894 ret = IRQ_HANDLED; 1895 } 1896 1897 return ret; 1898} 1899 1900static const struct sci_irq_desc { 1901 const char *desc; 1902 irq_handler_t handler; 1903} sci_irq_desc[] = { 1904 /* 1905 * Split out handlers, the default case. 1906 */ 1907 [SCIx_ERI_IRQ] = { 1908 .desc = "rx err", 1909 .handler = sci_er_interrupt, 1910 }, 1911 1912 [SCIx_RXI_IRQ] = { 1913 .desc = "rx full", 1914 .handler = sci_rx_interrupt, 1915 }, 1916 1917 [SCIx_TXI_IRQ] = { 1918 .desc = "tx empty", 1919 .handler = sci_tx_interrupt, 1920 }, 1921 1922 [SCIx_BRI_IRQ] = { 1923 .desc = "break", 1924 .handler = sci_br_interrupt, 1925 }, 1926 1927 [SCIx_DRI_IRQ] = { 1928 .desc = "rx ready", 1929 .handler = sci_rx_interrupt, 1930 }, 1931 1932 [SCIx_TEI_IRQ] = { 1933 .desc = "tx end", 1934 .handler = sci_tx_end_interrupt, 1935 }, 1936 1937 /* 1938 * Special muxed handler. 1939 */ 1940 [SCIx_MUX_IRQ] = { 1941 .desc = "mux", 1942 .handler = sci_mpxed_interrupt, 1943 }, 1944}; 1945 1946static int sci_request_irq(struct sci_port *port) 1947{ 1948 struct uart_port *up = &port->port; 1949 int i, j, w, ret = 0; 1950 1951 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { 1952 const struct sci_irq_desc *desc; 1953 int irq; 1954 1955 /* Check if already registered (muxed) */ 1956 for (w = 0; w < i; w++) 1957 if (port->irqs[w] == port->irqs[i]) 1958 w = i + 1; 1959 if (w > i) 1960 continue; 1961 1962 if (SCIx_IRQ_IS_MUXED(port)) { 1963 i = SCIx_MUX_IRQ; 1964 irq = up->irq; 1965 } else { 1966 irq = port->irqs[i]; 1967 1968 /* 1969 * Certain port types won't support all of the 1970 * available interrupt sources. 1971 */ 1972 if (unlikely(irq < 0)) 1973 continue; 1974 } 1975 1976 desc = sci_irq_desc + i; 1977 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", 1978 dev_name(up->dev), desc->desc); 1979 if (!port->irqstr[j]) { 1980 ret = -ENOMEM; 1981 goto out_nomem; 1982 } 1983 1984 ret = request_irq(irq, desc->handler, up->irqflags, 1985 port->irqstr[j], port); 1986 if (unlikely(ret)) { 1987 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); 1988 goto out_noirq; 1989 } 1990 } 1991 1992 return 0; 1993 1994out_noirq: 1995 while (--i >= 0) 1996 free_irq(port->irqs[i], port); 1997 1998out_nomem: 1999 while (--j >= 0) 2000 kfree(port->irqstr[j]); 2001 2002 return ret; 2003} 2004 2005static void sci_free_irq(struct sci_port *port) 2006{ 2007 int i, j; 2008 2009 /* 2010 * Intentionally in reverse order so we iterate over the muxed 2011 * IRQ first. 2012 */ 2013 for (i = 0; i < SCIx_NR_IRQS; i++) { 2014 int irq = port->irqs[i]; 2015 2016 /* 2017 * Certain port types won't support all of the available 2018 * interrupt sources. 2019 */ 2020 if (unlikely(irq < 0)) 2021 continue; 2022 2023 /* Check if already freed (irq was muxed) */ 2024 for (j = 0; j < i; j++) 2025 if (port->irqs[j] == irq) 2026 j = i + 1; 2027 if (j > i) 2028 continue; 2029 2030 free_irq(port->irqs[i], port); 2031 kfree(port->irqstr[i]); 2032 2033 if (SCIx_IRQ_IS_MUXED(port)) { 2034 /* If there's only one IRQ, we're done. */ 2035 return; 2036 } 2037 } 2038} 2039 2040static unsigned int sci_tx_empty(struct uart_port *port) 2041{ 2042 unsigned short status = serial_port_in(port, SCxSR); 2043 unsigned short in_tx_fifo = sci_txfill(port); 2044 2045 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 2046} 2047 2048static void sci_set_rts(struct uart_port *port, bool state) 2049{ 2050 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2051 u16 data = serial_port_in(port, SCPDR); 2052 2053 /* Active low */ 2054 if (state) 2055 data &= ~SCPDR_RTSD; 2056 else 2057 data |= SCPDR_RTSD; 2058 serial_port_out(port, SCPDR, data); 2059 2060 /* RTS# is output */ 2061 serial_port_out(port, SCPCR, 2062 serial_port_in(port, SCPCR) | SCPCR_RTSC); 2063 } else if (sci_getreg(port, SCSPTR)->size) { 2064 u16 ctrl = serial_port_in(port, SCSPTR); 2065 2066 /* Active low */ 2067 if (state) 2068 ctrl &= ~SCSPTR_RTSDT; 2069 else 2070 ctrl |= SCSPTR_RTSDT; 2071 serial_port_out(port, SCSPTR, ctrl); 2072 } 2073} 2074 2075static bool sci_get_cts(struct uart_port *port) 2076{ 2077 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2078 /* Active low */ 2079 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD); 2080 } else if (sci_getreg(port, SCSPTR)->size) { 2081 /* Active low */ 2082 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT); 2083 } 2084 2085 return true; 2086} 2087 2088/* 2089 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally 2090 * CTS/RTS is supported in hardware by at least one port and controlled 2091 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently 2092 * handled via the ->init_pins() op, which is a bit of a one-way street, 2093 * lacking any ability to defer pin control -- this will later be 2094 * converted over to the GPIO framework). 2095 * 2096 * Other modes (such as loopback) are supported generically on certain 2097 * port types, but not others. For these it's sufficient to test for the 2098 * existence of the support register and simply ignore the port type. 2099 */ 2100static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 2101{ 2102 struct sci_port *s = to_sci_port(port); 2103 2104 if (mctrl & TIOCM_LOOP) { 2105 const struct plat_sci_reg *reg; 2106 2107 /* 2108 * Standard loopback mode for SCFCR ports. 2109 */ 2110 reg = sci_getreg(port, SCFCR); 2111 if (reg->size) 2112 serial_port_out(port, SCFCR, 2113 serial_port_in(port, SCFCR) | 2114 SCFCR_LOOP); 2115 } 2116 2117 mctrl_gpio_set(s->gpios, mctrl); 2118 2119 if (!s->has_rtscts) 2120 return; 2121 2122 if (!(mctrl & TIOCM_RTS)) { 2123 /* Disable Auto RTS */ 2124 serial_port_out(port, SCFCR, 2125 serial_port_in(port, SCFCR) & ~SCFCR_MCE); 2126 2127 /* Clear RTS */ 2128 sci_set_rts(port, 0); 2129 } else if (s->autorts) { 2130 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { 2131 /* Enable RTS# pin function */ 2132 serial_port_out(port, SCPCR, 2133 serial_port_in(port, SCPCR) & ~SCPCR_RTSC); 2134 } 2135 2136 /* Enable Auto RTS */ 2137 serial_port_out(port, SCFCR, 2138 serial_port_in(port, SCFCR) | SCFCR_MCE); 2139 } else { 2140 /* Set RTS */ 2141 sci_set_rts(port, 1); 2142 } 2143} 2144 2145static unsigned int sci_get_mctrl(struct uart_port *port) 2146{ 2147 struct sci_port *s = to_sci_port(port); 2148 struct mctrl_gpios *gpios = s->gpios; 2149 unsigned int mctrl = 0; 2150 2151 mctrl_gpio_get(gpios, &mctrl); 2152 2153 /* 2154 * CTS/RTS is handled in hardware when supported, while nothing 2155 * else is wired up. 2156 */ 2157 if (s->autorts) { 2158 if (sci_get_cts(port)) 2159 mctrl |= TIOCM_CTS; 2160 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) { 2161 mctrl |= TIOCM_CTS; 2162 } 2163 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)) 2164 mctrl |= TIOCM_DSR; 2165 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)) 2166 mctrl |= TIOCM_CAR; 2167 2168 return mctrl; 2169} 2170 2171static void sci_enable_ms(struct uart_port *port) 2172{ 2173 mctrl_gpio_enable_ms(to_sci_port(port)->gpios); 2174} 2175 2176static void sci_break_ctl(struct uart_port *port, int break_state) 2177{ 2178 unsigned short scscr, scsptr; 2179 unsigned long flags; 2180 2181 /* check whether the port has SCSPTR */ 2182 if (!sci_getreg(port, SCSPTR)->size) { 2183 /* 2184 * Not supported by hardware. Most parts couple break and rx 2185 * interrupts together, with break detection always enabled. 2186 */ 2187 return; 2188 } 2189 2190 spin_lock_irqsave(&port->lock, flags); 2191 scsptr = serial_port_in(port, SCSPTR); 2192 scscr = serial_port_in(port, SCSCR); 2193 2194 if (break_state == -1) { 2195 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; 2196 scscr &= ~SCSCR_TE; 2197 } else { 2198 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; 2199 scscr |= SCSCR_TE; 2200 } 2201 2202 serial_port_out(port, SCSPTR, scsptr); 2203 serial_port_out(port, SCSCR, scscr); 2204 spin_unlock_irqrestore(&port->lock, flags); 2205} 2206 2207static int sci_startup(struct uart_port *port) 2208{ 2209 struct sci_port *s = to_sci_port(port); 2210 int ret; 2211 2212 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2213 2214 sci_request_dma(port); 2215 2216 ret = sci_request_irq(s); 2217 if (unlikely(ret < 0)) { 2218 sci_free_dma(port); 2219 return ret; 2220 } 2221 2222 return 0; 2223} 2224 2225static void sci_shutdown(struct uart_port *port) 2226{ 2227 struct sci_port *s = to_sci_port(port); 2228 unsigned long flags; 2229 u16 scr; 2230 2231 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 2232 2233 s->autorts = false; 2234 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2235 2236 spin_lock_irqsave(&port->lock, flags); 2237 sci_stop_rx(port); 2238 sci_stop_tx(port); 2239 /* 2240 * Stop RX and TX, disable related interrupts, keep clock source 2241 * and HSCIF TOT bits 2242 */ 2243 scr = serial_port_in(port, SCSCR); 2244 serial_port_out(port, SCSCR, scr & 2245 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2246 spin_unlock_irqrestore(&port->lock, flags); 2247 2248#ifdef CONFIG_SERIAL_SH_SCI_DMA 2249 if (s->chan_rx_saved) { 2250 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, 2251 port->line); 2252 hrtimer_cancel(&s->rx_timer); 2253 } 2254#endif 2255 2256 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) 2257 del_timer_sync(&s->rx_fifo_timer); 2258 sci_free_irq(s); 2259 sci_free_dma(port); 2260} 2261 2262static int sci_sck_calc(struct sci_port *s, unsigned int bps, 2263 unsigned int *srr) 2264{ 2265 unsigned long freq = s->clk_rates[SCI_SCK]; 2266 int err, min_err = INT_MAX; 2267 unsigned int sr; 2268 2269 if (s->port.type != PORT_HSCIF) 2270 freq *= 2; 2271 2272 for_each_sr(sr, s) { 2273 err = DIV_ROUND_CLOSEST(freq, sr) - bps; 2274 if (abs(err) >= abs(min_err)) 2275 continue; 2276 2277 min_err = err; 2278 *srr = sr - 1; 2279 2280 if (!err) 2281 break; 2282 } 2283 2284 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, 2285 *srr + 1); 2286 return min_err; 2287} 2288 2289static int sci_brg_calc(struct sci_port *s, unsigned int bps, 2290 unsigned long freq, unsigned int *dlr, 2291 unsigned int *srr) 2292{ 2293 int err, min_err = INT_MAX; 2294 unsigned int sr, dl; 2295 2296 if (s->port.type != PORT_HSCIF) 2297 freq *= 2; 2298 2299 for_each_sr(sr, s) { 2300 dl = DIV_ROUND_CLOSEST(freq, sr * bps); 2301 dl = clamp(dl, 1U, 65535U); 2302 2303 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; 2304 if (abs(err) >= abs(min_err)) 2305 continue; 2306 2307 min_err = err; 2308 *dlr = dl; 2309 *srr = sr - 1; 2310 2311 if (!err) 2312 break; 2313 } 2314 2315 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, 2316 min_err, *dlr, *srr + 1); 2317 return min_err; 2318} 2319 2320/* calculate sample rate, BRR, and clock select */ 2321static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, 2322 unsigned int *brr, unsigned int *srr, 2323 unsigned int *cks) 2324{ 2325 unsigned long freq = s->clk_rates[SCI_FCK]; 2326 unsigned int sr, br, prediv, scrate, c; 2327 int err, min_err = INT_MAX; 2328 2329 if (s->port.type != PORT_HSCIF) 2330 freq *= 2; 2331 2332 /* 2333 * Find the combination of sample rate and clock select with the 2334 * smallest deviation from the desired baud rate. 2335 * Prefer high sample rates to maximise the receive margin. 2336 * 2337 * M: Receive margin (%) 2338 * N: Ratio of bit rate to clock (N = sampling rate) 2339 * D: Clock duty (D = 0 to 1.0) 2340 * L: Frame length (L = 9 to 12) 2341 * F: Absolute value of clock frequency deviation 2342 * 2343 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - 2344 * (|D - 0.5| / N * (1 + F))| 2345 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. 2346 */ 2347 for_each_sr(sr, s) { 2348 for (c = 0; c <= 3; c++) { 2349 /* integerized formulas from HSCIF documentation */ 2350 prediv = sr << (2 * c + 1); 2351 2352 /* 2353 * We need to calculate: 2354 * 2355 * br = freq / (prediv * bps) clamped to [1..256] 2356 * err = freq / (br * prediv) - bps 2357 * 2358 * Watch out for overflow when calculating the desired 2359 * sampling clock rate! 2360 */ 2361 if (bps > UINT_MAX / prediv) 2362 break; 2363 2364 scrate = prediv * bps; 2365 br = DIV_ROUND_CLOSEST(freq, scrate); 2366 br = clamp(br, 1U, 256U); 2367 2368 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; 2369 if (abs(err) >= abs(min_err)) 2370 continue; 2371 2372 min_err = err; 2373 *brr = br - 1; 2374 *srr = sr - 1; 2375 *cks = c; 2376 2377 if (!err) 2378 goto found; 2379 } 2380 } 2381 2382found: 2383 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, 2384 min_err, *brr, *srr + 1, *cks); 2385 return min_err; 2386} 2387 2388static void sci_reset(struct uart_port *port) 2389{ 2390 const struct plat_sci_reg *reg; 2391 unsigned int status; 2392 struct sci_port *s = to_sci_port(port); 2393 2394 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */ 2395 2396 reg = sci_getreg(port, SCFCR); 2397 if (reg->size) 2398 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); 2399 2400 sci_clear_SCxSR(port, 2401 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) & 2402 SCxSR_BREAK_CLEAR(port)); 2403 if (sci_getreg(port, SCLSR)->size) { 2404 status = serial_port_in(port, SCLSR); 2405 status &= ~(SCLSR_TO | SCLSR_ORER); 2406 serial_port_out(port, SCLSR, status); 2407 } 2408 2409 if (s->rx_trigger > 1) { 2410 if (s->rx_fifo_timeout) { 2411 scif_set_rtrg(port, 1); 2412 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0); 2413 } else { 2414 if (port->type == PORT_SCIFA || 2415 port->type == PORT_SCIFB) 2416 scif_set_rtrg(port, 1); 2417 else 2418 scif_set_rtrg(port, s->rx_trigger); 2419 } 2420 } 2421} 2422 2423static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 2424 const struct ktermios *old) 2425{ 2426 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits; 2427 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; 2428 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; 2429 struct sci_port *s = to_sci_port(port); 2430 const struct plat_sci_reg *reg; 2431 int min_err = INT_MAX, err; 2432 unsigned long max_freq = 0; 2433 int best_clk = -1; 2434 unsigned long flags; 2435 2436 if ((termios->c_cflag & CSIZE) == CS7) { 2437 smr_val |= SCSMR_CHR; 2438 } else { 2439 termios->c_cflag &= ~CSIZE; 2440 termios->c_cflag |= CS8; 2441 } 2442 if (termios->c_cflag & PARENB) 2443 smr_val |= SCSMR_PE; 2444 if (termios->c_cflag & PARODD) 2445 smr_val |= SCSMR_PE | SCSMR_ODD; 2446 if (termios->c_cflag & CSTOPB) 2447 smr_val |= SCSMR_STOP; 2448 2449 /* 2450 * earlyprintk comes here early on with port->uartclk set to zero. 2451 * the clock framework is not up and running at this point so here 2452 * we assume that 115200 is the maximum baud rate. please note that 2453 * the baud rate is not programmed during earlyprintk - it is assumed 2454 * that the previous boot loader has enabled required clocks and 2455 * setup the baud rate generator hardware for us already. 2456 */ 2457 if (!port->uartclk) { 2458 baud = uart_get_baud_rate(port, termios, old, 0, 115200); 2459 goto done; 2460 } 2461 2462 for (i = 0; i < SCI_NUM_CLKS; i++) 2463 max_freq = max(max_freq, s->clk_rates[i]); 2464 2465 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s)); 2466 if (!baud) 2467 goto done; 2468 2469 /* 2470 * There can be multiple sources for the sampling clock. Find the one 2471 * that gives us the smallest deviation from the desired baud rate. 2472 */ 2473 2474 /* Optional Undivided External Clock */ 2475 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && 2476 port->type != PORT_SCIFB) { 2477 err = sci_sck_calc(s, baud, &srr1); 2478 if (abs(err) < abs(min_err)) { 2479 best_clk = SCI_SCK; 2480 scr_val = SCSCR_CKE1; 2481 sccks = SCCKS_CKS; 2482 min_err = err; 2483 srr = srr1; 2484 if (!err) 2485 goto done; 2486 } 2487 } 2488 2489 /* Optional BRG Frequency Divided External Clock */ 2490 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { 2491 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, 2492 &srr1); 2493 if (abs(err) < abs(min_err)) { 2494 best_clk = SCI_SCIF_CLK; 2495 scr_val = SCSCR_CKE1; 2496 sccks = 0; 2497 min_err = err; 2498 dl = dl1; 2499 srr = srr1; 2500 if (!err) 2501 goto done; 2502 } 2503 } 2504 2505 /* Optional BRG Frequency Divided Internal Clock */ 2506 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { 2507 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, 2508 &srr1); 2509 if (abs(err) < abs(min_err)) { 2510 best_clk = SCI_BRG_INT; 2511 scr_val = SCSCR_CKE1; 2512 sccks = SCCKS_XIN; 2513 min_err = err; 2514 dl = dl1; 2515 srr = srr1; 2516 if (!min_err) 2517 goto done; 2518 } 2519 } 2520 2521 /* Divided Functional Clock using standard Bit Rate Register */ 2522 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); 2523 if (abs(err) < abs(min_err)) { 2524 best_clk = SCI_FCK; 2525 scr_val = 0; 2526 min_err = err; 2527 brr = brr1; 2528 srr = srr1; 2529 cks = cks1; 2530 } 2531 2532done: 2533 if (best_clk >= 0) 2534 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", 2535 s->clks[best_clk], baud, min_err); 2536 2537 sci_port_enable(s); 2538 2539 /* 2540 * Program the optional External Baud Rate Generator (BRG) first. 2541 * It controls the mux to select (H)SCK or frequency divided clock. 2542 */ 2543 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { 2544 serial_port_out(port, SCDL, dl); 2545 serial_port_out(port, SCCKS, sccks); 2546 } 2547 2548 spin_lock_irqsave(&port->lock, flags); 2549 2550 sci_reset(port); 2551 2552 uart_update_timeout(port, termios->c_cflag, baud); 2553 2554 /* byte size and parity */ 2555 bits = tty_get_frame_size(termios->c_cflag); 2556 2557 if (sci_getreg(port, SEMR)->size) 2558 serial_port_out(port, SEMR, 0); 2559 2560 if (best_clk >= 0) { 2561 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) 2562 switch (srr + 1) { 2563 case 5: smr_val |= SCSMR_SRC_5; break; 2564 case 7: smr_val |= SCSMR_SRC_7; break; 2565 case 11: smr_val |= SCSMR_SRC_11; break; 2566 case 13: smr_val |= SCSMR_SRC_13; break; 2567 case 16: smr_val |= SCSMR_SRC_16; break; 2568 case 17: smr_val |= SCSMR_SRC_17; break; 2569 case 19: smr_val |= SCSMR_SRC_19; break; 2570 case 27: smr_val |= SCSMR_SRC_27; break; 2571 } 2572 smr_val |= cks; 2573 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2574 serial_port_out(port, SCSMR, smr_val); 2575 serial_port_out(port, SCBRR, brr); 2576 if (sci_getreg(port, HSSRR)->size) { 2577 unsigned int hssrr = srr | HSCIF_SRE; 2578 /* Calculate deviation from intended rate at the 2579 * center of the last stop bit in sampling clocks. 2580 */ 2581 int last_stop = bits * 2 - 1; 2582 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop * 2583 (int)(srr + 1), 2584 2 * (int)baud); 2585 2586 if (abs(deviation) >= 2) { 2587 /* At least two sampling clocks off at the 2588 * last stop bit; we can increase the error 2589 * margin by shifting the sampling point. 2590 */ 2591 int shift = clamp(deviation / 2, -8, 7); 2592 2593 hssrr |= (shift << HSCIF_SRHP_SHIFT) & 2594 HSCIF_SRHP_MASK; 2595 hssrr |= HSCIF_SRDE; 2596 } 2597 serial_port_out(port, HSSRR, hssrr); 2598 } 2599 2600 /* Wait one bit interval */ 2601 udelay((1000000 + (baud - 1)) / baud); 2602 } else { 2603 /* Don't touch the bit rate configuration */ 2604 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); 2605 smr_val |= serial_port_in(port, SCSMR) & 2606 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); 2607 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2608 serial_port_out(port, SCSMR, smr_val); 2609 } 2610 2611 sci_init_pins(port, termios->c_cflag); 2612 2613 port->status &= ~UPSTAT_AUTOCTS; 2614 s->autorts = false; 2615 reg = sci_getreg(port, SCFCR); 2616 if (reg->size) { 2617 unsigned short ctrl = serial_port_in(port, SCFCR); 2618 2619 if ((port->flags & UPF_HARD_FLOW) && 2620 (termios->c_cflag & CRTSCTS)) { 2621 /* There is no CTS interrupt to restart the hardware */ 2622 port->status |= UPSTAT_AUTOCTS; 2623 /* MCE is enabled when RTS is raised */ 2624 s->autorts = true; 2625 } 2626 2627 /* 2628 * As we've done a sci_reset() above, ensure we don't 2629 * interfere with the FIFOs while toggling MCE. As the 2630 * reset values could still be set, simply mask them out. 2631 */ 2632 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); 2633 2634 serial_port_out(port, SCFCR, ctrl); 2635 } 2636 if (port->flags & UPF_HARD_FLOW) { 2637 /* Refresh (Auto) RTS */ 2638 sci_set_mctrl(port, port->mctrl); 2639 } 2640 2641 /* 2642 * For SCI, TE (transmit enable) must be set after setting TIE 2643 * (transmit interrupt enable) or in the same instruction to 2644 * start the transmitting process. So skip setting TE here for SCI. 2645 */ 2646 if (port->type != PORT_SCI) 2647 scr_val |= SCSCR_TE; 2648 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)); 2649 serial_port_out(port, SCSCR, scr_val | s->hscif_tot); 2650 if ((srr + 1 == 5) && 2651 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) { 2652 /* 2653 * In asynchronous mode, when the sampling rate is 1/5, first 2654 * received data may become invalid on some SCIFA and SCIFB. 2655 * To avoid this problem wait more than 1 serial data time (1 2656 * bit time x serial data number) after setting SCSCR.RE = 1. 2657 */ 2658 udelay(DIV_ROUND_UP(10 * 1000000, baud)); 2659 } 2660 2661 /* Calculate delay for 2 DMA buffers (4 FIFO). */ 2662 s->rx_frame = (10000 * bits) / (baud / 100); 2663#ifdef CONFIG_SERIAL_SH_SCI_DMA 2664 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame; 2665#endif 2666 2667 if ((termios->c_cflag & CREAD) != 0) 2668 sci_start_rx(port); 2669 2670 spin_unlock_irqrestore(&port->lock, flags); 2671 2672 sci_port_disable(s); 2673 2674 if (UART_ENABLE_MS(port, termios->c_cflag)) 2675 sci_enable_ms(port); 2676} 2677 2678static void sci_pm(struct uart_port *port, unsigned int state, 2679 unsigned int oldstate) 2680{ 2681 struct sci_port *sci_port = to_sci_port(port); 2682 2683 switch (state) { 2684 case UART_PM_STATE_OFF: 2685 sci_port_disable(sci_port); 2686 break; 2687 default: 2688 sci_port_enable(sci_port); 2689 break; 2690 } 2691} 2692 2693static const char *sci_type(struct uart_port *port) 2694{ 2695 switch (port->type) { 2696 case PORT_IRDA: 2697 return "irda"; 2698 case PORT_SCI: 2699 return "sci"; 2700 case PORT_SCIF: 2701 return "scif"; 2702 case PORT_SCIFA: 2703 return "scifa"; 2704 case PORT_SCIFB: 2705 return "scifb"; 2706 case PORT_HSCIF: 2707 return "hscif"; 2708 } 2709 2710 return NULL; 2711} 2712 2713static int sci_remap_port(struct uart_port *port) 2714{ 2715 struct sci_port *sport = to_sci_port(port); 2716 2717 /* 2718 * Nothing to do if there's already an established membase. 2719 */ 2720 if (port->membase) 2721 return 0; 2722 2723 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2724 port->membase = ioremap(port->mapbase, sport->reg_size); 2725 if (unlikely(!port->membase)) { 2726 dev_err(port->dev, "can't remap port#%d\n", port->line); 2727 return -ENXIO; 2728 } 2729 } else { 2730 /* 2731 * For the simple (and majority of) cases where we don't 2732 * need to do any remapping, just cast the cookie 2733 * directly. 2734 */ 2735 port->membase = (void __iomem *)(uintptr_t)port->mapbase; 2736 } 2737 2738 return 0; 2739} 2740 2741static void sci_release_port(struct uart_port *port) 2742{ 2743 struct sci_port *sport = to_sci_port(port); 2744 2745 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) { 2746 iounmap(port->membase); 2747 port->membase = NULL; 2748 } 2749 2750 release_mem_region(port->mapbase, sport->reg_size); 2751} 2752 2753static int sci_request_port(struct uart_port *port) 2754{ 2755 struct resource *res; 2756 struct sci_port *sport = to_sci_port(port); 2757 int ret; 2758 2759 res = request_mem_region(port->mapbase, sport->reg_size, 2760 dev_name(port->dev)); 2761 if (unlikely(res == NULL)) { 2762 dev_err(port->dev, "request_mem_region failed."); 2763 return -EBUSY; 2764 } 2765 2766 ret = sci_remap_port(port); 2767 if (unlikely(ret != 0)) { 2768 release_resource(res); 2769 return ret; 2770 } 2771 2772 return 0; 2773} 2774 2775static void sci_config_port(struct uart_port *port, int flags) 2776{ 2777 if (flags & UART_CONFIG_TYPE) { 2778 struct sci_port *sport = to_sci_port(port); 2779 2780 port->type = sport->cfg->type; 2781 sci_request_port(port); 2782 } 2783} 2784 2785static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 2786{ 2787 if (ser->baud_base < 2400) 2788 /* No paper tape reader for Mitch.. */ 2789 return -EINVAL; 2790 2791 return 0; 2792} 2793 2794static const struct uart_ops sci_uart_ops = { 2795 .tx_empty = sci_tx_empty, 2796 .set_mctrl = sci_set_mctrl, 2797 .get_mctrl = sci_get_mctrl, 2798 .start_tx = sci_start_tx, 2799 .stop_tx = sci_stop_tx, 2800 .stop_rx = sci_stop_rx, 2801 .enable_ms = sci_enable_ms, 2802 .break_ctl = sci_break_ctl, 2803 .startup = sci_startup, 2804 .shutdown = sci_shutdown, 2805 .flush_buffer = sci_flush_buffer, 2806 .set_termios = sci_set_termios, 2807 .pm = sci_pm, 2808 .type = sci_type, 2809 .release_port = sci_release_port, 2810 .request_port = sci_request_port, 2811 .config_port = sci_config_port, 2812 .verify_port = sci_verify_port, 2813#ifdef CONFIG_CONSOLE_POLL 2814 .poll_get_char = sci_poll_get_char, 2815 .poll_put_char = sci_poll_put_char, 2816#endif 2817}; 2818 2819static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) 2820{ 2821 const char *clk_names[] = { 2822 [SCI_FCK] = "fck", 2823 [SCI_SCK] = "sck", 2824 [SCI_BRG_INT] = "brg_int", 2825 [SCI_SCIF_CLK] = "scif_clk", 2826 }; 2827 struct clk *clk; 2828 unsigned int i; 2829 2830 if (sci_port->cfg->type == PORT_HSCIF) 2831 clk_names[SCI_SCK] = "hsck"; 2832 2833 for (i = 0; i < SCI_NUM_CLKS; i++) { 2834 clk = devm_clk_get_optional(dev, clk_names[i]); 2835 if (IS_ERR(clk)) 2836 return PTR_ERR(clk); 2837 2838 if (!clk && i == SCI_FCK) { 2839 /* 2840 * Not all SH platforms declare a clock lookup entry 2841 * for SCI devices, in which case we need to get the 2842 * global "peripheral_clk" clock. 2843 */ 2844 clk = devm_clk_get(dev, "peripheral_clk"); 2845 if (IS_ERR(clk)) 2846 return dev_err_probe(dev, PTR_ERR(clk), 2847 "failed to get %s\n", 2848 clk_names[i]); 2849 } 2850 2851 if (!clk) 2852 dev_dbg(dev, "failed to get %s\n", clk_names[i]); 2853 else 2854 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i], 2855 clk, clk_get_rate(clk)); 2856 sci_port->clks[i] = clk; 2857 } 2858 return 0; 2859} 2860 2861static const struct sci_port_params * 2862sci_probe_regmap(const struct plat_sci_port *cfg) 2863{ 2864 unsigned int regtype; 2865 2866 if (cfg->regtype != SCIx_PROBE_REGTYPE) 2867 return &sci_port_params[cfg->regtype]; 2868 2869 switch (cfg->type) { 2870 case PORT_SCI: 2871 regtype = SCIx_SCI_REGTYPE; 2872 break; 2873 case PORT_IRDA: 2874 regtype = SCIx_IRDA_REGTYPE; 2875 break; 2876 case PORT_SCIFA: 2877 regtype = SCIx_SCIFA_REGTYPE; 2878 break; 2879 case PORT_SCIFB: 2880 regtype = SCIx_SCIFB_REGTYPE; 2881 break; 2882 case PORT_SCIF: 2883 /* 2884 * The SH-4 is a bit of a misnomer here, although that's 2885 * where this particular port layout originated. This 2886 * configuration (or some slight variation thereof) 2887 * remains the dominant model for all SCIFs. 2888 */ 2889 regtype = SCIx_SH4_SCIF_REGTYPE; 2890 break; 2891 case PORT_HSCIF: 2892 regtype = SCIx_HSCIF_REGTYPE; 2893 break; 2894 default: 2895 pr_err("Can't probe register map for given port\n"); 2896 return NULL; 2897 } 2898 2899 return &sci_port_params[regtype]; 2900} 2901 2902static int sci_init_single(struct platform_device *dev, 2903 struct sci_port *sci_port, unsigned int index, 2904 const struct plat_sci_port *p, bool early) 2905{ 2906 struct uart_port *port = &sci_port->port; 2907 const struct resource *res; 2908 unsigned int i; 2909 int ret; 2910 2911 sci_port->cfg = p; 2912 2913 port->ops = &sci_uart_ops; 2914 port->iotype = UPIO_MEM; 2915 port->line = index; 2916 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE); 2917 2918 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 2919 if (res == NULL) 2920 return -ENOMEM; 2921 2922 port->mapbase = res->start; 2923 sci_port->reg_size = resource_size(res); 2924 2925 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) { 2926 if (i) 2927 sci_port->irqs[i] = platform_get_irq_optional(dev, i); 2928 else 2929 sci_port->irqs[i] = platform_get_irq(dev, i); 2930 } 2931 2932 /* 2933 * The fourth interrupt on SCI port is transmit end interrupt, so 2934 * shuffle the interrupts. 2935 */ 2936 if (p->type == PORT_SCI) 2937 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); 2938 2939 /* The SCI generates several interrupts. They can be muxed together or 2940 * connected to different interrupt lines. In the muxed case only one 2941 * interrupt resource is specified as there is only one interrupt ID. 2942 * In the non-muxed case, up to 6 interrupt signals might be generated 2943 * from the SCI, however those signals might have their own individual 2944 * interrupt ID numbers, or muxed together with another interrupt. 2945 */ 2946 if (sci_port->irqs[0] < 0) 2947 return -ENXIO; 2948 2949 if (sci_port->irqs[1] < 0) 2950 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++) 2951 sci_port->irqs[i] = sci_port->irqs[0]; 2952 2953 sci_port->params = sci_probe_regmap(p); 2954 if (unlikely(sci_port->params == NULL)) 2955 return -EINVAL; 2956 2957 switch (p->type) { 2958 case PORT_SCIFB: 2959 sci_port->rx_trigger = 48; 2960 break; 2961 case PORT_HSCIF: 2962 sci_port->rx_trigger = 64; 2963 break; 2964 case PORT_SCIFA: 2965 sci_port->rx_trigger = 32; 2966 break; 2967 case PORT_SCIF: 2968 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) 2969 /* RX triggering not implemented for this IP */ 2970 sci_port->rx_trigger = 1; 2971 else 2972 sci_port->rx_trigger = 8; 2973 break; 2974 default: 2975 sci_port->rx_trigger = 1; 2976 break; 2977 } 2978 2979 sci_port->rx_fifo_timeout = 0; 2980 sci_port->hscif_tot = 0; 2981 2982 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't 2983 * match the SoC datasheet, this should be investigated. Let platform 2984 * data override the sampling rate for now. 2985 */ 2986 sci_port->sampling_rate_mask = p->sampling_rate 2987 ? SCI_SR(p->sampling_rate) 2988 : sci_port->params->sampling_rate_mask; 2989 2990 if (!early) { 2991 ret = sci_init_clocks(sci_port, &dev->dev); 2992 if (ret < 0) 2993 return ret; 2994 2995 port->dev = &dev->dev; 2996 2997 pm_runtime_enable(&dev->dev); 2998 } 2999 3000 port->type = p->type; 3001 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; 3002 port->fifosize = sci_port->params->fifosize; 3003 3004 if (port->type == PORT_SCI && !dev->dev.of_node) { 3005 if (sci_port->reg_size >= 0x20) 3006 port->regshift = 2; 3007 else 3008 port->regshift = 1; 3009 } 3010 3011 /* 3012 * The UART port needs an IRQ value, so we peg this to the RX IRQ 3013 * for the multi-IRQ ports, which is where we are primarily 3014 * concerned with the shutdown path synchronization. 3015 * 3016 * For the muxed case there's nothing more to do. 3017 */ 3018 port->irq = sci_port->irqs[SCIx_RXI_IRQ]; 3019 port->irqflags = 0; 3020 3021 port->serial_in = sci_serial_in; 3022 port->serial_out = sci_serial_out; 3023 3024 return 0; 3025} 3026 3027static void sci_cleanup_single(struct sci_port *port) 3028{ 3029 pm_runtime_disable(port->port.dev); 3030} 3031 3032#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ 3033 defined(CONFIG_SERIAL_SH_SCI_EARLYCON) 3034static void serial_console_putchar(struct uart_port *port, unsigned char ch) 3035{ 3036 sci_poll_put_char(port, ch); 3037} 3038 3039/* 3040 * Print a string to the serial port trying not to disturb 3041 * any possible real use of the port... 3042 */ 3043static void serial_console_write(struct console *co, const char *s, 3044 unsigned count) 3045{ 3046 struct sci_port *sci_port = &sci_ports[co->index]; 3047 struct uart_port *port = &sci_port->port; 3048 unsigned short bits, ctrl, ctrl_temp; 3049 unsigned long flags; 3050 int locked = 1; 3051 3052 if (port->sysrq) 3053 locked = 0; 3054 else if (oops_in_progress) 3055 locked = spin_trylock_irqsave(&port->lock, flags); 3056 else 3057 spin_lock_irqsave(&port->lock, flags); 3058 3059 /* first save SCSCR then disable interrupts, keep clock source */ 3060 ctrl = serial_port_in(port, SCSCR); 3061 ctrl_temp = SCSCR_RE | SCSCR_TE | 3062 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | 3063 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); 3064 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot); 3065 3066 uart_console_write(port, s, count, serial_console_putchar); 3067 3068 /* wait until fifo is empty and last bit has been transmitted */ 3069 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 3070 while ((serial_port_in(port, SCxSR) & bits) != bits) 3071 cpu_relax(); 3072 3073 /* restore the SCSCR */ 3074 serial_port_out(port, SCSCR, ctrl); 3075 3076 if (locked) 3077 spin_unlock_irqrestore(&port->lock, flags); 3078} 3079 3080static int serial_console_setup(struct console *co, char *options) 3081{ 3082 struct sci_port *sci_port; 3083 struct uart_port *port; 3084 int baud = 115200; 3085 int bits = 8; 3086 int parity = 'n'; 3087 int flow = 'n'; 3088 int ret; 3089 3090 /* 3091 * Refuse to handle any bogus ports. 3092 */ 3093 if (co->index < 0 || co->index >= SCI_NPORTS) 3094 return -ENODEV; 3095 3096 sci_port = &sci_ports[co->index]; 3097 port = &sci_port->port; 3098 3099 /* 3100 * Refuse to handle uninitialized ports. 3101 */ 3102 if (!port->ops) 3103 return -ENODEV; 3104 3105 ret = sci_remap_port(port); 3106 if (unlikely(ret != 0)) 3107 return ret; 3108 3109 if (options) 3110 uart_parse_options(options, &baud, &parity, &bits, &flow); 3111 3112 return uart_set_options(port, co, baud, parity, bits, flow); 3113} 3114 3115static struct console serial_console = { 3116 .name = "ttySC", 3117 .device = uart_console_device, 3118 .write = serial_console_write, 3119 .setup = serial_console_setup, 3120 .flags = CON_PRINTBUFFER, 3121 .index = -1, 3122 .data = &sci_uart_driver, 3123}; 3124 3125#ifdef CONFIG_SUPERH 3126static char early_serial_buf[32]; 3127 3128static int early_serial_console_setup(struct console *co, char *options) 3129{ 3130 /* 3131 * This early console is always registered using the earlyprintk= 3132 * parameter, which does not call add_preferred_console(). Thus 3133 * @options is always NULL and the options for this early console 3134 * are passed using a custom buffer. 3135 */ 3136 WARN_ON(options); 3137 3138 return serial_console_setup(co, early_serial_buf); 3139} 3140 3141static struct console early_serial_console = { 3142 .name = "early_ttySC", 3143 .write = serial_console_write, 3144 .setup = early_serial_console_setup, 3145 .flags = CON_PRINTBUFFER, 3146 .index = -1, 3147}; 3148 3149static int sci_probe_earlyprintk(struct platform_device *pdev) 3150{ 3151 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); 3152 3153 if (early_serial_console.data) 3154 return -EEXIST; 3155 3156 early_serial_console.index = pdev->id; 3157 3158 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); 3159 3160 if (!strstr(early_serial_buf, "keep")) 3161 early_serial_console.flags |= CON_BOOT; 3162 3163 register_console(&early_serial_console); 3164 return 0; 3165} 3166#endif 3167 3168#define SCI_CONSOLE (&serial_console) 3169 3170#else 3171static inline int sci_probe_earlyprintk(struct platform_device *pdev) 3172{ 3173 return -EINVAL; 3174} 3175 3176#define SCI_CONSOLE NULL 3177 3178#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ 3179 3180static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; 3181 3182static DEFINE_MUTEX(sci_uart_registration_lock); 3183static struct uart_driver sci_uart_driver = { 3184 .owner = THIS_MODULE, 3185 .driver_name = "sci", 3186 .dev_name = "ttySC", 3187 .major = SCI_MAJOR, 3188 .minor = SCI_MINOR_START, 3189 .nr = SCI_NPORTS, 3190 .cons = SCI_CONSOLE, 3191}; 3192 3193static int sci_remove(struct platform_device *dev) 3194{ 3195 struct sci_port *port = platform_get_drvdata(dev); 3196 unsigned int type = port->port.type; /* uart_remove_... clears it */ 3197 3198 sci_ports_in_use &= ~BIT(port->port.line); 3199 uart_remove_one_port(&sci_uart_driver, &port->port); 3200 3201 sci_cleanup_single(port); 3202 3203 if (port->port.fifosize > 1) 3204 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3205 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) 3206 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3207 3208 return 0; 3209} 3210 3211 3212#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) 3213#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) 3214#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) 3215 3216static const struct of_device_id of_sci_match[] __maybe_unused = { 3217 /* SoC-specific types */ 3218 { 3219 .compatible = "renesas,scif-r7s72100", 3220 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), 3221 }, 3222 { 3223 .compatible = "renesas,scif-r7s9210", 3224 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3225 }, 3226 { 3227 .compatible = "renesas,scif-r9a07g044", 3228 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE), 3229 }, 3230 /* Family-specific types */ 3231 { 3232 .compatible = "renesas,rcar-gen1-scif", 3233 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3234 }, { 3235 .compatible = "renesas,rcar-gen2-scif", 3236 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3237 }, { 3238 .compatible = "renesas,rcar-gen3-scif", 3239 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3240 }, { 3241 .compatible = "renesas,rcar-gen4-scif", 3242 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), 3243 }, 3244 /* Generic types */ 3245 { 3246 .compatible = "renesas,scif", 3247 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), 3248 }, { 3249 .compatible = "renesas,scifa", 3250 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), 3251 }, { 3252 .compatible = "renesas,scifb", 3253 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), 3254 }, { 3255 .compatible = "renesas,hscif", 3256 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), 3257 }, { 3258 .compatible = "renesas,sci", 3259 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), 3260 }, { 3261 /* Terminator */ 3262 }, 3263}; 3264MODULE_DEVICE_TABLE(of, of_sci_match); 3265 3266static void sci_reset_control_assert(void *data) 3267{ 3268 reset_control_assert(data); 3269} 3270 3271static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev, 3272 unsigned int *dev_id) 3273{ 3274 struct device_node *np = pdev->dev.of_node; 3275 struct reset_control *rstc; 3276 struct plat_sci_port *p; 3277 struct sci_port *sp; 3278 const void *data; 3279 int id, ret; 3280 3281 if (!IS_ENABLED(CONFIG_OF) || !np) 3282 return ERR_PTR(-EINVAL); 3283 3284 data = of_device_get_match_data(&pdev->dev); 3285 3286 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 3287 if (IS_ERR(rstc)) 3288 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc), 3289 "failed to get reset ctrl\n")); 3290 3291 ret = reset_control_deassert(rstc); 3292 if (ret) { 3293 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret); 3294 return ERR_PTR(ret); 3295 } 3296 3297 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc); 3298 if (ret) { 3299 dev_err(&pdev->dev, "failed to register assert devm action, %d\n", 3300 ret); 3301 return ERR_PTR(ret); 3302 } 3303 3304 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); 3305 if (!p) 3306 return ERR_PTR(-ENOMEM); 3307 3308 /* Get the line number from the aliases node. */ 3309 id = of_alias_get_id(np, "serial"); 3310 if (id < 0 && ~sci_ports_in_use) 3311 id = ffz(sci_ports_in_use); 3312 if (id < 0) { 3313 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); 3314 return ERR_PTR(-EINVAL); 3315 } 3316 if (id >= ARRAY_SIZE(sci_ports)) { 3317 dev_err(&pdev->dev, "serial%d out of range\n", id); 3318 return ERR_PTR(-EINVAL); 3319 } 3320 3321 sp = &sci_ports[id]; 3322 *dev_id = id; 3323 3324 p->type = SCI_OF_TYPE(data); 3325 p->regtype = SCI_OF_REGTYPE(data); 3326 3327 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts"); 3328 3329 return p; 3330} 3331 3332static int sci_probe_single(struct platform_device *dev, 3333 unsigned int index, 3334 struct plat_sci_port *p, 3335 struct sci_port *sciport) 3336{ 3337 int ret; 3338 3339 /* Sanity check */ 3340 if (unlikely(index >= SCI_NPORTS)) { 3341 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", 3342 index+1, SCI_NPORTS); 3343 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); 3344 return -EINVAL; 3345 } 3346 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8); 3347 if (sci_ports_in_use & BIT(index)) 3348 return -EBUSY; 3349 3350 mutex_lock(&sci_uart_registration_lock); 3351 if (!sci_uart_driver.state) { 3352 ret = uart_register_driver(&sci_uart_driver); 3353 if (ret) { 3354 mutex_unlock(&sci_uart_registration_lock); 3355 return ret; 3356 } 3357 } 3358 mutex_unlock(&sci_uart_registration_lock); 3359 3360 ret = sci_init_single(dev, sciport, index, p, false); 3361 if (ret) 3362 return ret; 3363 3364 sciport->gpios = mctrl_gpio_init(&sciport->port, 0); 3365 if (IS_ERR(sciport->gpios)) 3366 return PTR_ERR(sciport->gpios); 3367 3368 if (sciport->has_rtscts) { 3369 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) || 3370 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) { 3371 dev_err(&dev->dev, "Conflicting RTS/CTS config\n"); 3372 return -EINVAL; 3373 } 3374 sciport->port.flags |= UPF_HARD_FLOW; 3375 } 3376 3377 ret = uart_add_one_port(&sci_uart_driver, &sciport->port); 3378 if (ret) { 3379 sci_cleanup_single(sciport); 3380 return ret; 3381 } 3382 3383 return 0; 3384} 3385 3386static int sci_probe(struct platform_device *dev) 3387{ 3388 struct plat_sci_port *p; 3389 struct sci_port *sp; 3390 unsigned int dev_id; 3391 int ret; 3392 3393 /* 3394 * If we've come here via earlyprintk initialization, head off to 3395 * the special early probe. We don't have sufficient device state 3396 * to make it beyond this yet. 3397 */ 3398#ifdef CONFIG_SUPERH 3399 if (is_sh_early_platform_device(dev)) 3400 return sci_probe_earlyprintk(dev); 3401#endif 3402 3403 if (dev->dev.of_node) { 3404 p = sci_parse_dt(dev, &dev_id); 3405 if (IS_ERR(p)) 3406 return PTR_ERR(p); 3407 } else { 3408 p = dev->dev.platform_data; 3409 if (p == NULL) { 3410 dev_err(&dev->dev, "no platform data supplied\n"); 3411 return -EINVAL; 3412 } 3413 3414 dev_id = dev->id; 3415 } 3416 3417 sp = &sci_ports[dev_id]; 3418 platform_set_drvdata(dev, sp); 3419 3420 ret = sci_probe_single(dev, dev_id, p, sp); 3421 if (ret) 3422 return ret; 3423 3424 if (sp->port.fifosize > 1) { 3425 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger); 3426 if (ret) 3427 return ret; 3428 } 3429 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB || 3430 sp->port.type == PORT_HSCIF) { 3431 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout); 3432 if (ret) { 3433 if (sp->port.fifosize > 1) { 3434 device_remove_file(&dev->dev, 3435 &dev_attr_rx_fifo_trigger); 3436 } 3437 return ret; 3438 } 3439 } 3440 3441#ifdef CONFIG_SH_STANDARD_BIOS 3442 sh_bios_gdb_detach(); 3443#endif 3444 3445 sci_ports_in_use |= BIT(dev_id); 3446 return 0; 3447} 3448 3449static __maybe_unused int sci_suspend(struct device *dev) 3450{ 3451 struct sci_port *sport = dev_get_drvdata(dev); 3452 3453 if (sport) 3454 uart_suspend_port(&sci_uart_driver, &sport->port); 3455 3456 return 0; 3457} 3458 3459static __maybe_unused int sci_resume(struct device *dev) 3460{ 3461 struct sci_port *sport = dev_get_drvdata(dev); 3462 3463 if (sport) 3464 uart_resume_port(&sci_uart_driver, &sport->port); 3465 3466 return 0; 3467} 3468 3469static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); 3470 3471static struct platform_driver sci_driver = { 3472 .probe = sci_probe, 3473 .remove = sci_remove, 3474 .driver = { 3475 .name = "sh-sci", 3476 .pm = &sci_dev_pm_ops, 3477 .of_match_table = of_match_ptr(of_sci_match), 3478 }, 3479}; 3480 3481static int __init sci_init(void) 3482{ 3483 pr_info("%s\n", banner); 3484 3485 return platform_driver_register(&sci_driver); 3486} 3487 3488static void __exit sci_exit(void) 3489{ 3490 platform_driver_unregister(&sci_driver); 3491 3492 if (sci_uart_driver.state) 3493 uart_unregister_driver(&sci_uart_driver); 3494} 3495 3496#if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 3497sh_early_platform_init_buffer("earlyprintk", &sci_driver, 3498 early_serial_buf, ARRAY_SIZE(early_serial_buf)); 3499#endif 3500#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON 3501static struct plat_sci_port port_cfg __initdata; 3502 3503static int __init early_console_setup(struct earlycon_device *device, 3504 int type) 3505{ 3506 if (!device->port.membase) 3507 return -ENODEV; 3508 3509 device->port.serial_in = sci_serial_in; 3510 device->port.serial_out = sci_serial_out; 3511 device->port.type = type; 3512 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); 3513 port_cfg.type = type; 3514 sci_ports[0].cfg = &port_cfg; 3515 sci_ports[0].params = sci_probe_regmap(&port_cfg); 3516 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR); 3517 sci_serial_out(&sci_ports[0].port, SCSCR, 3518 SCSCR_RE | SCSCR_TE | port_cfg.scscr); 3519 3520 device->con->write = serial_console_write; 3521 return 0; 3522} 3523static int __init sci_early_console_setup(struct earlycon_device *device, 3524 const char *opt) 3525{ 3526 return early_console_setup(device, PORT_SCI); 3527} 3528static int __init scif_early_console_setup(struct earlycon_device *device, 3529 const char *opt) 3530{ 3531 return early_console_setup(device, PORT_SCIF); 3532} 3533static int __init rzscifa_early_console_setup(struct earlycon_device *device, 3534 const char *opt) 3535{ 3536 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE; 3537 return early_console_setup(device, PORT_SCIF); 3538} 3539 3540static int __init scifa_early_console_setup(struct earlycon_device *device, 3541 const char *opt) 3542{ 3543 return early_console_setup(device, PORT_SCIFA); 3544} 3545static int __init scifb_early_console_setup(struct earlycon_device *device, 3546 const char *opt) 3547{ 3548 return early_console_setup(device, PORT_SCIFB); 3549} 3550static int __init hscif_early_console_setup(struct earlycon_device *device, 3551 const char *opt) 3552{ 3553 return early_console_setup(device, PORT_HSCIF); 3554} 3555 3556OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); 3557OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); 3558OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup); 3559OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup); 3560OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); 3561OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); 3562OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); 3563#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ 3564 3565module_init(sci_init); 3566module_exit(sci_exit); 3567 3568MODULE_LICENSE("GPL"); 3569MODULE_ALIAS("platform:sh-sci"); 3570MODULE_AUTHOR("Paul Mundt"); 3571MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); 3572