1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint 4 * Author: Jon Ringle <jringle@gridpoint.com> 5 * 6 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru> 7 */ 8 9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11#include <linux/bitops.h> 12#include <linux/clk.h> 13#include <linux/delay.h> 14#include <linux/device.h> 15#include <linux/gpio/driver.h> 16#include <linux/i2c.h> 17#include <linux/mod_devicetable.h> 18#include <linux/module.h> 19#include <linux/property.h> 20#include <linux/regmap.h> 21#include <linux/serial_core.h> 22#include <linux/serial.h> 23#include <linux/tty.h> 24#include <linux/tty_flip.h> 25#include <linux/spi/spi.h> 26#include <linux/uaccess.h> 27#include <linux/units.h> 28#include <uapi/linux/sched/types.h> 29 30#define SC16IS7XX_NAME "sc16is7xx" 31#define SC16IS7XX_MAX_DEVS 8 32 33/* SC16IS7XX register definitions */ 34#define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */ 35#define SC16IS7XX_THR_REG (0x00) /* TX FIFO */ 36#define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */ 37#define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */ 38#define SC16IS7XX_FCR_REG (0x02) /* FIFO control */ 39#define SC16IS7XX_LCR_REG (0x03) /* Line Control */ 40#define SC16IS7XX_MCR_REG (0x04) /* Modem Control */ 41#define SC16IS7XX_LSR_REG (0x05) /* Line Status */ 42#define SC16IS7XX_MSR_REG (0x06) /* Modem Status */ 43#define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */ 44#define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */ 45#define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */ 46#define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction 47 * - only on 75x/76x 48 */ 49#define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State 50 * - only on 75x/76x 51 */ 52#define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable 53 * - only on 75x/76x 54 */ 55#define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control 56 * - only on 75x/76x 57 */ 58#define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */ 59 60/* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */ 61#define SC16IS7XX_TCR_REG (0x06) /* Transmit control */ 62#define SC16IS7XX_TLR_REG (0x07) /* Trigger level */ 63 64/* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */ 65#define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */ 66#define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */ 67 68/* Enhanced Register set: Only if (LCR == 0xBF) */ 69#define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */ 70#define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */ 71#define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */ 72#define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */ 73#define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */ 74 75/* IER register bits */ 76#define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */ 77#define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register 78 * interrupt */ 79#define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status 80 * interrupt */ 81#define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status 82 * interrupt */ 83 84/* IER register bits - write only if (EFR[4] == 1) */ 85#define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */ 86#define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */ 87#define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */ 88#define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */ 89 90/* FCR register bits */ 91#define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */ 92#define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */ 93#define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */ 94#define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */ 95#define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */ 96 97/* FCR register bits - write only if (EFR[4] == 1) */ 98#define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */ 99#define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */ 100 101/* IIR register bits */ 102#define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */ 103#define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */ 104#define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */ 105#define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */ 106#define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */ 107#define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */ 108#define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt 109 * - only on 75x/76x 110 */ 111#define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state 112 * - only on 75x/76x 113 */ 114#define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */ 115#define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state 116 * from active (LOW) 117 * to inactive (HIGH) 118 */ 119/* LCR register bits */ 120#define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 121#define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 122 * 123 * Word length bits table: 124 * 00 -> 5 bit words 125 * 01 -> 6 bit words 126 * 10 -> 7 bit words 127 * 11 -> 8 bit words 128 */ 129#define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 130 * 131 * STOP length bit table: 132 * 0 -> 1 stop bit 133 * 1 -> 1-1.5 stop bits if 134 * word length is 5, 135 * 2 stop bits otherwise 136 */ 137#define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 138#define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 139#define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 140#define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 141#define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */ 142#define SC16IS7XX_LCR_WORD_LEN_5 (0x00) 143#define SC16IS7XX_LCR_WORD_LEN_6 (0x01) 144#define SC16IS7XX_LCR_WORD_LEN_7 (0x02) 145#define SC16IS7XX_LCR_WORD_LEN_8 (0x03) 146#define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special 147 * reg set */ 148#define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced 149 * reg set */ 150 151/* MCR register bits */ 152#define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement 153 * - only on 75x/76x 154 */ 155#define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */ 156#define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */ 157#define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */ 158#define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any 159 * - write enabled 160 * if (EFR[4] == 1) 161 */ 162#define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode 163 * - write enabled 164 * if (EFR[4] == 1) 165 */ 166#define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4 167 * - write enabled 168 * if (EFR[4] == 1) 169 */ 170 171/* LSR register bits */ 172#define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */ 173#define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */ 174#define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */ 175#define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */ 176#define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */ 177#define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */ 178#define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */ 179#define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */ 180#define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */ 181 182/* MSR register bits */ 183#define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */ 184#define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready 185 * or (IO4) 186 * - only on 75x/76x 187 */ 188#define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator 189 * or (IO7) 190 * - only on 75x/76x 191 */ 192#define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect 193 * or (IO6) 194 * - only on 75x/76x 195 */ 196#define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */ 197#define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4) 198 * - only on 75x/76x 199 */ 200#define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7) 201 * - only on 75x/76x 202 */ 203#define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6) 204 * - only on 75x/76x 205 */ 206#define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */ 207 208/* 209 * TCR register bits 210 * TCR trigger levels are available from 0 to 60 characters with a granularity 211 * of four. 212 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is 213 * no built-in hardware check to make sure this condition is met. Also, the TCR 214 * must be programmed with this condition before auto RTS or software flow 215 * control is enabled to avoid spurious operation of the device. 216 */ 217#define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0) 218#define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4) 219 220/* 221 * TLR register bits 222 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the 223 * FIFO Control Register (FCR) are used for the transmit and receive FIFO 224 * trigger levels. Trigger levels from 4 characters to 60 characters are 225 * available with a granularity of four. 226 * 227 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the 228 * trigger level setting defined in FCR. If TLR has non-zero trigger level value 229 * the trigger level defined in FCR is discarded. This applies to both transmit 230 * FIFO and receive FIFO trigger level setting. 231 * 232 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the 233 * default state, that is, '00'. 234 */ 235#define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0) 236#define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) 237 238/* IOControl register bits (Only 750/760) */ 239#define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ 240#define SC16IS7XX_IOCONTROL_MODEM_A_BIT (1 << 1) /* Enable GPIO[7:4] as modem A pins */ 241#define SC16IS7XX_IOCONTROL_MODEM_B_BIT (1 << 2) /* Enable GPIO[3:0] as modem B pins */ 242#define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */ 243 244/* EFCR register bits */ 245#define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop 246 * mode (RS485) */ 247#define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */ 248#define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */ 249#define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */ 250#define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */ 251#define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode 252 * 0 = rate upto 115.2 kbit/s 253 * - Only 750/760 254 * 1 = rate upto 1.152 Mbit/s 255 * - Only 760 256 */ 257 258/* EFR register bits */ 259#define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */ 260#define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */ 261#define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */ 262#define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions 263 * and writing to IER[7:4], 264 * FCR[5:4], MCR[7:5] 265 */ 266#define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */ 267#define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2 268 * 269 * SWFLOW bits 3 & 2 table: 270 * 00 -> no transmitter flow 271 * control 272 * 01 -> transmitter generates 273 * XON2 and XOFF2 274 * 10 -> transmitter generates 275 * XON1 and XOFF1 276 * 11 -> transmitter generates 277 * XON1, XON2, XOFF1 and 278 * XOFF2 279 */ 280#define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */ 281#define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3 282 * 283 * SWFLOW bits 3 & 2 table: 284 * 00 -> no received flow 285 * control 286 * 01 -> receiver compares 287 * XON2 and XOFF2 288 * 10 -> receiver compares 289 * XON1 and XOFF1 290 * 11 -> receiver compares 291 * XON1, XON2, XOFF1 and 292 * XOFF2 293 */ 294#define SC16IS7XX_EFR_FLOWCTRL_BITS (SC16IS7XX_EFR_AUTORTS_BIT | \ 295 SC16IS7XX_EFR_AUTOCTS_BIT | \ 296 SC16IS7XX_EFR_XOFF2_DETECT_BIT | \ 297 SC16IS7XX_EFR_SWFLOW3_BIT | \ 298 SC16IS7XX_EFR_SWFLOW2_BIT | \ 299 SC16IS7XX_EFR_SWFLOW1_BIT | \ 300 SC16IS7XX_EFR_SWFLOW0_BIT) 301 302 303/* Misc definitions */ 304#define SC16IS7XX_SPI_READ_BIT BIT(7) 305#define SC16IS7XX_FIFO_SIZE (64) 306#define SC16IS7XX_GPIOS_PER_BANK 4 307 308struct sc16is7xx_devtype { 309 char name[10]; 310 int nr_gpio; 311 int nr_uart; 312}; 313 314#define SC16IS7XX_RECONF_MD (1 << 0) 315#define SC16IS7XX_RECONF_IER (1 << 1) 316#define SC16IS7XX_RECONF_RS485 (1 << 2) 317 318struct sc16is7xx_one_config { 319 unsigned int flags; 320 u8 ier_mask; 321 u8 ier_val; 322}; 323 324struct sc16is7xx_one { 325 struct uart_port port; 326 struct regmap *regmap; 327 struct mutex efr_lock; /* EFR registers access */ 328 struct kthread_work tx_work; 329 struct kthread_work reg_work; 330 struct kthread_delayed_work ms_work; 331 struct sc16is7xx_one_config config; 332 bool irda_mode; 333 unsigned int old_mctrl; 334}; 335 336struct sc16is7xx_port { 337 const struct sc16is7xx_devtype *devtype; 338 struct clk *clk; 339#ifdef CONFIG_GPIOLIB 340 struct gpio_chip gpio; 341 unsigned long gpio_valid_mask; 342#endif 343 u8 mctrl_mask; 344 unsigned char buf[SC16IS7XX_FIFO_SIZE]; 345 struct kthread_worker kworker; 346 struct task_struct *kworker_task; 347 struct sc16is7xx_one p[]; 348}; 349 350static unsigned long sc16is7xx_lines; 351 352static struct uart_driver sc16is7xx_uart = { 353 .owner = THIS_MODULE, 354 .dev_name = "ttySC", 355 .nr = SC16IS7XX_MAX_DEVS, 356}; 357 358static void sc16is7xx_ier_set(struct uart_port *port, u8 bit); 359static void sc16is7xx_stop_tx(struct uart_port *port); 360 361#define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e))) 362#define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e))) 363 364static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg) 365{ 366 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 367 unsigned int val = 0; 368 369 regmap_read(one->regmap, reg, &val); 370 371 return val; 372} 373 374static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val) 375{ 376 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 377 378 regmap_write(one->regmap, reg, val); 379} 380 381static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen) 382{ 383 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 384 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 385 386 regmap_noinc_read(one->regmap, SC16IS7XX_RHR_REG, s->buf, rxlen); 387} 388 389static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send) 390{ 391 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 392 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 393 394 /* 395 * Don't send zero-length data, at least on SPI it confuses the chip 396 * delivering wrong TXLVL data. 397 */ 398 if (unlikely(!to_send)) 399 return; 400 401 regmap_noinc_write(one->regmap, SC16IS7XX_THR_REG, s->buf, to_send); 402} 403 404static void sc16is7xx_port_update(struct uart_port *port, u8 reg, 405 u8 mask, u8 val) 406{ 407 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 408 409 regmap_update_bits(one->regmap, reg, mask, val); 410} 411 412static void sc16is7xx_power(struct uart_port *port, int on) 413{ 414 sc16is7xx_port_update(port, SC16IS7XX_IER_REG, 415 SC16IS7XX_IER_SLEEP_BIT, 416 on ? 0 : SC16IS7XX_IER_SLEEP_BIT); 417} 418 419static const struct sc16is7xx_devtype sc16is74x_devtype = { 420 .name = "SC16IS74X", 421 .nr_gpio = 0, 422 .nr_uart = 1, 423}; 424 425static const struct sc16is7xx_devtype sc16is750_devtype = { 426 .name = "SC16IS750", 427 .nr_gpio = 8, 428 .nr_uart = 1, 429}; 430 431static const struct sc16is7xx_devtype sc16is752_devtype = { 432 .name = "SC16IS752", 433 .nr_gpio = 8, 434 .nr_uart = 2, 435}; 436 437static const struct sc16is7xx_devtype sc16is760_devtype = { 438 .name = "SC16IS760", 439 .nr_gpio = 8, 440 .nr_uart = 1, 441}; 442 443static const struct sc16is7xx_devtype sc16is762_devtype = { 444 .name = "SC16IS762", 445 .nr_gpio = 8, 446 .nr_uart = 2, 447}; 448 449static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg) 450{ 451 switch (reg) { 452 case SC16IS7XX_RHR_REG: 453 case SC16IS7XX_IIR_REG: 454 case SC16IS7XX_LSR_REG: 455 case SC16IS7XX_MSR_REG: 456 case SC16IS7XX_TXLVL_REG: 457 case SC16IS7XX_RXLVL_REG: 458 case SC16IS7XX_IOSTATE_REG: 459 case SC16IS7XX_IOCONTROL_REG: 460 return true; 461 default: 462 break; 463 } 464 465 return false; 466} 467 468static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg) 469{ 470 switch (reg) { 471 case SC16IS7XX_RHR_REG: 472 return true; 473 default: 474 break; 475 } 476 477 return false; 478} 479 480static bool sc16is7xx_regmap_noinc(struct device *dev, unsigned int reg) 481{ 482 return reg == SC16IS7XX_RHR_REG; 483} 484 485static int sc16is7xx_set_baud(struct uart_port *port, int baud) 486{ 487 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 488 u8 lcr; 489 u8 prescaler = 0; 490 unsigned long clk = port->uartclk, div = clk / 16 / baud; 491 492 if (div > 0xffff) { 493 prescaler = SC16IS7XX_MCR_CLKSEL_BIT; 494 div /= 4; 495 } 496 497 /* In an amazing feat of design, the Enhanced Features Register shares 498 * the address of the Interrupt Identification Register, and is 499 * switched in by writing a magic value (0xbf) to the Line Control 500 * Register. Any interrupt firing during this time will see the EFR 501 * where it expects the IIR to be, leading to "Unexpected interrupt" 502 * messages. 503 * 504 * Prevent this possibility by claiming a mutex while accessing the 505 * EFR, and claiming the same mutex from within the interrupt handler. 506 * This is similar to disabling the interrupt, but that doesn't work 507 * because the bulk of the interrupt processing is run as a workqueue 508 * job in thread context. 509 */ 510 mutex_lock(&one->efr_lock); 511 512 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG); 513 514 /* Open the LCR divisors for configuration */ 515 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 516 SC16IS7XX_LCR_CONF_MODE_B); 517 518 /* Enable enhanced features */ 519 regcache_cache_bypass(one->regmap, true); 520 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 521 SC16IS7XX_EFR_ENABLE_BIT, 522 SC16IS7XX_EFR_ENABLE_BIT); 523 524 regcache_cache_bypass(one->regmap, false); 525 526 /* Put LCR back to the normal mode */ 527 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 528 529 mutex_unlock(&one->efr_lock); 530 531 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 532 SC16IS7XX_MCR_CLKSEL_BIT, 533 prescaler); 534 535 /* Open the LCR divisors for configuration */ 536 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 537 SC16IS7XX_LCR_CONF_MODE_A); 538 539 /* Write the new divisor */ 540 regcache_cache_bypass(one->regmap, true); 541 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256); 542 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256); 543 regcache_cache_bypass(one->regmap, false); 544 545 /* Put LCR back to the normal mode */ 546 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 547 548 return DIV_ROUND_CLOSEST(clk / 16, div); 549} 550 551static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen, 552 unsigned int iir) 553{ 554 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 555 unsigned int lsr = 0, bytes_read, i; 556 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false; 557 u8 ch, flag; 558 559 if (unlikely(rxlen >= sizeof(s->buf))) { 560 dev_warn_ratelimited(port->dev, 561 "ttySC%i: Possible RX FIFO overrun: %d\n", 562 port->line, rxlen); 563 port->icount.buf_overrun++; 564 /* Ensure sanity of RX level */ 565 rxlen = sizeof(s->buf); 566 } 567 568 while (rxlen) { 569 /* Only read lsr if there are possible errors in FIFO */ 570 if (read_lsr) { 571 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 572 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT)) 573 read_lsr = false; /* No errors left in FIFO */ 574 } else 575 lsr = 0; 576 577 if (read_lsr) { 578 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG); 579 bytes_read = 1; 580 } else { 581 sc16is7xx_fifo_read(port, rxlen); 582 bytes_read = rxlen; 583 } 584 585 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK; 586 587 port->icount.rx++; 588 flag = TTY_NORMAL; 589 590 if (unlikely(lsr)) { 591 if (lsr & SC16IS7XX_LSR_BI_BIT) { 592 port->icount.brk++; 593 if (uart_handle_break(port)) 594 continue; 595 } else if (lsr & SC16IS7XX_LSR_PE_BIT) 596 port->icount.parity++; 597 else if (lsr & SC16IS7XX_LSR_FE_BIT) 598 port->icount.frame++; 599 else if (lsr & SC16IS7XX_LSR_OE_BIT) 600 port->icount.overrun++; 601 602 lsr &= port->read_status_mask; 603 if (lsr & SC16IS7XX_LSR_BI_BIT) 604 flag = TTY_BREAK; 605 else if (lsr & SC16IS7XX_LSR_PE_BIT) 606 flag = TTY_PARITY; 607 else if (lsr & SC16IS7XX_LSR_FE_BIT) 608 flag = TTY_FRAME; 609 else if (lsr & SC16IS7XX_LSR_OE_BIT) 610 flag = TTY_OVERRUN; 611 } 612 613 for (i = 0; i < bytes_read; ++i) { 614 ch = s->buf[i]; 615 if (uart_handle_sysrq_char(port, ch)) 616 continue; 617 618 if (lsr & port->ignore_status_mask) 619 continue; 620 621 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch, 622 flag); 623 } 624 rxlen -= bytes_read; 625 } 626 627 tty_flip_buffer_push(&port->state->port); 628} 629 630static void sc16is7xx_handle_tx(struct uart_port *port) 631{ 632 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 633 struct circ_buf *xmit = &port->state->xmit; 634 unsigned int txlen, to_send, i; 635 unsigned long flags; 636 637 if (unlikely(port->x_char)) { 638 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char); 639 port->icount.tx++; 640 port->x_char = 0; 641 return; 642 } 643 644 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 645 uart_port_lock_irqsave(port, &flags); 646 sc16is7xx_stop_tx(port); 647 uart_port_unlock_irqrestore(port, flags); 648 return; 649 } 650 651 /* Get length of data pending in circular buffer */ 652 to_send = uart_circ_chars_pending(xmit); 653 if (likely(to_send)) { 654 /* Limit to size of TX FIFO */ 655 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG); 656 if (txlen > SC16IS7XX_FIFO_SIZE) { 657 dev_err_ratelimited(port->dev, 658 "chip reports %d free bytes in TX fifo, but it only has %d", 659 txlen, SC16IS7XX_FIFO_SIZE); 660 txlen = 0; 661 } 662 to_send = (to_send > txlen) ? txlen : to_send; 663 664 /* Convert to linear buffer */ 665 for (i = 0; i < to_send; ++i) { 666 s->buf[i] = xmit->buf[xmit->tail]; 667 uart_xmit_advance(port, 1); 668 } 669 670 sc16is7xx_fifo_write(port, to_send); 671 } 672 673 uart_port_lock_irqsave(port, &flags); 674 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 675 uart_write_wakeup(port); 676 677 if (uart_circ_empty(xmit)) 678 sc16is7xx_stop_tx(port); 679 else 680 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT); 681 uart_port_unlock_irqrestore(port, flags); 682} 683 684static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port) 685{ 686 u8 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG); 687 unsigned int mctrl = 0; 688 689 mctrl |= (msr & SC16IS7XX_MSR_CTS_BIT) ? TIOCM_CTS : 0; 690 mctrl |= (msr & SC16IS7XX_MSR_DSR_BIT) ? TIOCM_DSR : 0; 691 mctrl |= (msr & SC16IS7XX_MSR_CD_BIT) ? TIOCM_CAR : 0; 692 mctrl |= (msr & SC16IS7XX_MSR_RI_BIT) ? TIOCM_RNG : 0; 693 return mctrl; 694} 695 696static void sc16is7xx_update_mlines(struct sc16is7xx_one *one) 697{ 698 struct uart_port *port = &one->port; 699 unsigned long flags; 700 unsigned int status, changed; 701 702 lockdep_assert_held_once(&one->efr_lock); 703 704 status = sc16is7xx_get_hwmctrl(port); 705 changed = status ^ one->old_mctrl; 706 707 if (changed == 0) 708 return; 709 710 one->old_mctrl = status; 711 712 uart_port_lock_irqsave(port, &flags); 713 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG)) 714 port->icount.rng++; 715 if (changed & TIOCM_DSR) 716 port->icount.dsr++; 717 if (changed & TIOCM_CAR) 718 uart_handle_dcd_change(port, status & TIOCM_CAR); 719 if (changed & TIOCM_CTS) 720 uart_handle_cts_change(port, status & TIOCM_CTS); 721 722 wake_up_interruptible(&port->state->port.delta_msr_wait); 723 uart_port_unlock_irqrestore(port, flags); 724} 725 726static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno) 727{ 728 bool rc = true; 729 unsigned int iir, rxlen; 730 struct uart_port *port = &s->p[portno].port; 731 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 732 733 mutex_lock(&one->efr_lock); 734 735 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG); 736 if (iir & SC16IS7XX_IIR_NO_INT_BIT) { 737 rc = false; 738 goto out_port_irq; 739 } 740 741 iir &= SC16IS7XX_IIR_ID_MASK; 742 743 switch (iir) { 744 case SC16IS7XX_IIR_RDI_SRC: 745 case SC16IS7XX_IIR_RLSE_SRC: 746 case SC16IS7XX_IIR_RTOI_SRC: 747 case SC16IS7XX_IIR_XOFFI_SRC: 748 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG); 749 750 /* 751 * There is a silicon bug that makes the chip report a 752 * time-out interrupt but no data in the FIFO. This is 753 * described in errata section 18.1.4. 754 * 755 * When this happens, read one byte from the FIFO to 756 * clear the interrupt. 757 */ 758 if (iir == SC16IS7XX_IIR_RTOI_SRC && !rxlen) 759 rxlen = 1; 760 761 if (rxlen) 762 sc16is7xx_handle_rx(port, rxlen, iir); 763 break; 764 /* CTSRTS interrupt comes only when CTS goes inactive */ 765 case SC16IS7XX_IIR_CTSRTS_SRC: 766 case SC16IS7XX_IIR_MSI_SRC: 767 sc16is7xx_update_mlines(one); 768 break; 769 case SC16IS7XX_IIR_THRI_SRC: 770 sc16is7xx_handle_tx(port); 771 break; 772 default: 773 dev_err_ratelimited(port->dev, 774 "ttySC%i: Unexpected interrupt: %x", 775 port->line, iir); 776 break; 777 } 778 779out_port_irq: 780 mutex_unlock(&one->efr_lock); 781 782 return rc; 783} 784 785static irqreturn_t sc16is7xx_irq(int irq, void *dev_id) 786{ 787 bool keep_polling; 788 789 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id; 790 791 do { 792 int i; 793 794 keep_polling = false; 795 796 for (i = 0; i < s->devtype->nr_uart; ++i) 797 keep_polling |= sc16is7xx_port_irq(s, i); 798 } while (keep_polling); 799 800 return IRQ_HANDLED; 801} 802 803static void sc16is7xx_tx_proc(struct kthread_work *ws) 804{ 805 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port); 806 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 807 808 if ((port->rs485.flags & SER_RS485_ENABLED) && 809 (port->rs485.delay_rts_before_send > 0)) 810 msleep(port->rs485.delay_rts_before_send); 811 812 mutex_lock(&one->efr_lock); 813 sc16is7xx_handle_tx(port); 814 mutex_unlock(&one->efr_lock); 815} 816 817static void sc16is7xx_reconf_rs485(struct uart_port *port) 818{ 819 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT | 820 SC16IS7XX_EFCR_RTS_INVERT_BIT; 821 u32 efcr = 0; 822 struct serial_rs485 *rs485 = &port->rs485; 823 unsigned long irqflags; 824 825 uart_port_lock_irqsave(port, &irqflags); 826 if (rs485->flags & SER_RS485_ENABLED) { 827 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT; 828 829 if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 830 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT; 831 } 832 uart_port_unlock_irqrestore(port, irqflags); 833 834 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr); 835} 836 837static void sc16is7xx_reg_proc(struct kthread_work *ws) 838{ 839 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work); 840 struct sc16is7xx_one_config config; 841 unsigned long irqflags; 842 843 uart_port_lock_irqsave(&one->port, &irqflags); 844 config = one->config; 845 memset(&one->config, 0, sizeof(one->config)); 846 uart_port_unlock_irqrestore(&one->port, irqflags); 847 848 if (config.flags & SC16IS7XX_RECONF_MD) { 849 u8 mcr = 0; 850 851 /* Device ignores RTS setting when hardware flow is enabled */ 852 if (one->port.mctrl & TIOCM_RTS) 853 mcr |= SC16IS7XX_MCR_RTS_BIT; 854 855 if (one->port.mctrl & TIOCM_DTR) 856 mcr |= SC16IS7XX_MCR_DTR_BIT; 857 858 if (one->port.mctrl & TIOCM_LOOP) 859 mcr |= SC16IS7XX_MCR_LOOP_BIT; 860 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG, 861 SC16IS7XX_MCR_RTS_BIT | 862 SC16IS7XX_MCR_DTR_BIT | 863 SC16IS7XX_MCR_LOOP_BIT, 864 mcr); 865 } 866 867 if (config.flags & SC16IS7XX_RECONF_IER) 868 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG, 869 config.ier_mask, config.ier_val); 870 871 if (config.flags & SC16IS7XX_RECONF_RS485) 872 sc16is7xx_reconf_rs485(&one->port); 873} 874 875static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit) 876{ 877 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 878 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 879 880 lockdep_assert_held_once(&port->lock); 881 882 one->config.flags |= SC16IS7XX_RECONF_IER; 883 one->config.ier_mask |= bit; 884 one->config.ier_val &= ~bit; 885 kthread_queue_work(&s->kworker, &one->reg_work); 886} 887 888static void sc16is7xx_ier_set(struct uart_port *port, u8 bit) 889{ 890 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 891 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 892 893 lockdep_assert_held_once(&port->lock); 894 895 one->config.flags |= SC16IS7XX_RECONF_IER; 896 one->config.ier_mask |= bit; 897 one->config.ier_val |= bit; 898 kthread_queue_work(&s->kworker, &one->reg_work); 899} 900 901static void sc16is7xx_stop_tx(struct uart_port *port) 902{ 903 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT); 904} 905 906static void sc16is7xx_stop_rx(struct uart_port *port) 907{ 908 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 909} 910 911static void sc16is7xx_ms_proc(struct kthread_work *ws) 912{ 913 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, ms_work.work); 914 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev); 915 916 if (one->port.state) { 917 mutex_lock(&one->efr_lock); 918 sc16is7xx_update_mlines(one); 919 mutex_unlock(&one->efr_lock); 920 921 kthread_queue_delayed_work(&s->kworker, &one->ms_work, HZ); 922 } 923} 924 925static void sc16is7xx_enable_ms(struct uart_port *port) 926{ 927 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 928 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 929 930 lockdep_assert_held_once(&port->lock); 931 932 kthread_queue_delayed_work(&s->kworker, &one->ms_work, 0); 933} 934 935static void sc16is7xx_start_tx(struct uart_port *port) 936{ 937 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 938 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 939 940 kthread_queue_work(&s->kworker, &one->tx_work); 941} 942 943static void sc16is7xx_throttle(struct uart_port *port) 944{ 945 unsigned long flags; 946 947 /* 948 * Hardware flow control is enabled and thus the device ignores RTS 949 * value set in MCR register. Stop reading data from RX FIFO so the 950 * AutoRTS feature will de-activate RTS output. 951 */ 952 uart_port_lock_irqsave(port, &flags); 953 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 954 uart_port_unlock_irqrestore(port, flags); 955} 956 957static void sc16is7xx_unthrottle(struct uart_port *port) 958{ 959 unsigned long flags; 960 961 uart_port_lock_irqsave(port, &flags); 962 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT); 963 uart_port_unlock_irqrestore(port, flags); 964} 965 966static unsigned int sc16is7xx_tx_empty(struct uart_port *port) 967{ 968 unsigned int lsr; 969 970 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG); 971 972 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0; 973} 974 975static unsigned int sc16is7xx_get_mctrl(struct uart_port *port) 976{ 977 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 978 979 /* Called with port lock taken so we can only return cached value */ 980 return one->old_mctrl; 981} 982 983static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl) 984{ 985 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 986 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 987 988 one->config.flags |= SC16IS7XX_RECONF_MD; 989 kthread_queue_work(&s->kworker, &one->reg_work); 990} 991 992static void sc16is7xx_break_ctl(struct uart_port *port, int break_state) 993{ 994 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG, 995 SC16IS7XX_LCR_TXBREAK_BIT, 996 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0); 997} 998 999static void sc16is7xx_set_termios(struct uart_port *port, 1000 struct ktermios *termios, 1001 const struct ktermios *old) 1002{ 1003 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1004 unsigned int lcr, flow = 0; 1005 int baud; 1006 unsigned long flags; 1007 1008 kthread_cancel_delayed_work_sync(&one->ms_work); 1009 1010 /* Mask termios capabilities we don't support */ 1011 termios->c_cflag &= ~CMSPAR; 1012 1013 /* Word size */ 1014 switch (termios->c_cflag & CSIZE) { 1015 case CS5: 1016 lcr = SC16IS7XX_LCR_WORD_LEN_5; 1017 break; 1018 case CS6: 1019 lcr = SC16IS7XX_LCR_WORD_LEN_6; 1020 break; 1021 case CS7: 1022 lcr = SC16IS7XX_LCR_WORD_LEN_7; 1023 break; 1024 case CS8: 1025 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1026 break; 1027 default: 1028 lcr = SC16IS7XX_LCR_WORD_LEN_8; 1029 termios->c_cflag &= ~CSIZE; 1030 termios->c_cflag |= CS8; 1031 break; 1032 } 1033 1034 /* Parity */ 1035 if (termios->c_cflag & PARENB) { 1036 lcr |= SC16IS7XX_LCR_PARITY_BIT; 1037 if (!(termios->c_cflag & PARODD)) 1038 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT; 1039 } 1040 1041 /* Stop bits */ 1042 if (termios->c_cflag & CSTOPB) 1043 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */ 1044 1045 /* Set read status mask */ 1046 port->read_status_mask = SC16IS7XX_LSR_OE_BIT; 1047 if (termios->c_iflag & INPCK) 1048 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT | 1049 SC16IS7XX_LSR_FE_BIT; 1050 if (termios->c_iflag & (BRKINT | PARMRK)) 1051 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT; 1052 1053 /* Set status ignore mask */ 1054 port->ignore_status_mask = 0; 1055 if (termios->c_iflag & IGNBRK) 1056 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT; 1057 if (!(termios->c_cflag & CREAD)) 1058 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK; 1059 1060 /* As above, claim the mutex while accessing the EFR. */ 1061 mutex_lock(&one->efr_lock); 1062 1063 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 1064 SC16IS7XX_LCR_CONF_MODE_B); 1065 1066 /* Configure flow control */ 1067 regcache_cache_bypass(one->regmap, true); 1068 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]); 1069 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]); 1070 1071 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1072 if (termios->c_cflag & CRTSCTS) { 1073 flow |= SC16IS7XX_EFR_AUTOCTS_BIT | 1074 SC16IS7XX_EFR_AUTORTS_BIT; 1075 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1076 } 1077 if (termios->c_iflag & IXON) 1078 flow |= SC16IS7XX_EFR_SWFLOW3_BIT; 1079 if (termios->c_iflag & IXOFF) 1080 flow |= SC16IS7XX_EFR_SWFLOW1_BIT; 1081 1082 sc16is7xx_port_update(port, 1083 SC16IS7XX_EFR_REG, 1084 SC16IS7XX_EFR_FLOWCTRL_BITS, 1085 flow); 1086 regcache_cache_bypass(one->regmap, false); 1087 1088 /* Update LCR register */ 1089 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr); 1090 1091 mutex_unlock(&one->efr_lock); 1092 1093 /* Get baud rate generator configuration */ 1094 baud = uart_get_baud_rate(port, termios, old, 1095 port->uartclk / 16 / 4 / 0xffff, 1096 port->uartclk / 16); 1097 1098 /* Setup baudrate generator */ 1099 baud = sc16is7xx_set_baud(port, baud); 1100 1101 uart_port_lock_irqsave(port, &flags); 1102 1103 /* Update timeout according to new baud rate */ 1104 uart_update_timeout(port, termios->c_cflag, baud); 1105 1106 if (UART_ENABLE_MS(port, termios->c_cflag)) 1107 sc16is7xx_enable_ms(port); 1108 1109 uart_port_unlock_irqrestore(port, flags); 1110} 1111 1112static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios, 1113 struct serial_rs485 *rs485) 1114{ 1115 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1116 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1117 1118 if (rs485->flags & SER_RS485_ENABLED) { 1119 /* 1120 * RTS signal is handled by HW, it's timing can't be influenced. 1121 * However, it's sometimes useful to delay TX even without RTS 1122 * control therefore we try to handle .delay_rts_before_send. 1123 */ 1124 if (rs485->delay_rts_after_send) 1125 return -EINVAL; 1126 } 1127 1128 one->config.flags |= SC16IS7XX_RECONF_RS485; 1129 kthread_queue_work(&s->kworker, &one->reg_work); 1130 1131 return 0; 1132} 1133 1134static int sc16is7xx_startup(struct uart_port *port) 1135{ 1136 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1137 unsigned int val; 1138 unsigned long flags; 1139 1140 sc16is7xx_power(port, 1); 1141 1142 /* Reset FIFOs*/ 1143 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT; 1144 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val); 1145 udelay(5); 1146 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, 1147 SC16IS7XX_FCR_FIFO_BIT); 1148 1149 /* Enable EFR */ 1150 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, 1151 SC16IS7XX_LCR_CONF_MODE_B); 1152 1153 regcache_cache_bypass(one->regmap, true); 1154 1155 /* Enable write access to enhanced features and internal clock div */ 1156 sc16is7xx_port_update(port, SC16IS7XX_EFR_REG, 1157 SC16IS7XX_EFR_ENABLE_BIT, 1158 SC16IS7XX_EFR_ENABLE_BIT); 1159 1160 /* Enable TCR/TLR */ 1161 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1162 SC16IS7XX_MCR_TCRTLR_BIT, 1163 SC16IS7XX_MCR_TCRTLR_BIT); 1164 1165 /* Configure flow control levels */ 1166 /* Flow control halt level 48, resume level 24 */ 1167 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG, 1168 SC16IS7XX_TCR_RX_RESUME(24) | 1169 SC16IS7XX_TCR_RX_HALT(48)); 1170 1171 regcache_cache_bypass(one->regmap, false); 1172 1173 /* Now, initialize the UART */ 1174 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8); 1175 1176 /* Enable IrDA mode if requested in DT */ 1177 /* This bit must be written with LCR[7] = 0 */ 1178 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG, 1179 SC16IS7XX_MCR_IRDA_BIT, 1180 one->irda_mode ? 1181 SC16IS7XX_MCR_IRDA_BIT : 0); 1182 1183 /* Enable the Rx and Tx FIFO */ 1184 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1185 SC16IS7XX_EFCR_RXDISABLE_BIT | 1186 SC16IS7XX_EFCR_TXDISABLE_BIT, 1187 0); 1188 1189 /* Enable RX, CTS change and modem lines interrupts */ 1190 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_CTSI_BIT | 1191 SC16IS7XX_IER_MSI_BIT; 1192 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); 1193 1194 /* Enable modem status polling */ 1195 uart_port_lock_irqsave(port, &flags); 1196 sc16is7xx_enable_ms(port); 1197 uart_port_unlock_irqrestore(port, flags); 1198 1199 return 0; 1200} 1201 1202static void sc16is7xx_shutdown(struct uart_port *port) 1203{ 1204 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1205 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port); 1206 1207 kthread_cancel_delayed_work_sync(&one->ms_work); 1208 1209 /* Disable all interrupts */ 1210 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0); 1211 /* Disable TX/RX */ 1212 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, 1213 SC16IS7XX_EFCR_RXDISABLE_BIT | 1214 SC16IS7XX_EFCR_TXDISABLE_BIT, 1215 SC16IS7XX_EFCR_RXDISABLE_BIT | 1216 SC16IS7XX_EFCR_TXDISABLE_BIT); 1217 1218 sc16is7xx_power(port, 0); 1219 1220 kthread_flush_worker(&s->kworker); 1221} 1222 1223static const char *sc16is7xx_type(struct uart_port *port) 1224{ 1225 struct sc16is7xx_port *s = dev_get_drvdata(port->dev); 1226 1227 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL; 1228} 1229 1230static int sc16is7xx_request_port(struct uart_port *port) 1231{ 1232 /* Do nothing */ 1233 return 0; 1234} 1235 1236static void sc16is7xx_config_port(struct uart_port *port, int flags) 1237{ 1238 if (flags & UART_CONFIG_TYPE) 1239 port->type = PORT_SC16IS7XX; 1240} 1241 1242static int sc16is7xx_verify_port(struct uart_port *port, 1243 struct serial_struct *s) 1244{ 1245 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX)) 1246 return -EINVAL; 1247 if (s->irq != port->irq) 1248 return -EINVAL; 1249 1250 return 0; 1251} 1252 1253static void sc16is7xx_pm(struct uart_port *port, unsigned int state, 1254 unsigned int oldstate) 1255{ 1256 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0); 1257} 1258 1259static void sc16is7xx_null_void(struct uart_port *port) 1260{ 1261 /* Do nothing */ 1262} 1263 1264static const struct uart_ops sc16is7xx_ops = { 1265 .tx_empty = sc16is7xx_tx_empty, 1266 .set_mctrl = sc16is7xx_set_mctrl, 1267 .get_mctrl = sc16is7xx_get_mctrl, 1268 .stop_tx = sc16is7xx_stop_tx, 1269 .start_tx = sc16is7xx_start_tx, 1270 .throttle = sc16is7xx_throttle, 1271 .unthrottle = sc16is7xx_unthrottle, 1272 .stop_rx = sc16is7xx_stop_rx, 1273 .enable_ms = sc16is7xx_enable_ms, 1274 .break_ctl = sc16is7xx_break_ctl, 1275 .startup = sc16is7xx_startup, 1276 .shutdown = sc16is7xx_shutdown, 1277 .set_termios = sc16is7xx_set_termios, 1278 .type = sc16is7xx_type, 1279 .request_port = sc16is7xx_request_port, 1280 .release_port = sc16is7xx_null_void, 1281 .config_port = sc16is7xx_config_port, 1282 .verify_port = sc16is7xx_verify_port, 1283 .pm = sc16is7xx_pm, 1284}; 1285 1286#ifdef CONFIG_GPIOLIB 1287static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset) 1288{ 1289 unsigned int val; 1290 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1291 struct uart_port *port = &s->p[0].port; 1292 1293 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1294 1295 return !!(val & BIT(offset)); 1296} 1297 1298static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) 1299{ 1300 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1301 struct uart_port *port = &s->p[0].port; 1302 1303 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), 1304 val ? BIT(offset) : 0); 1305} 1306 1307static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip, 1308 unsigned offset) 1309{ 1310 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1311 struct uart_port *port = &s->p[0].port; 1312 1313 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0); 1314 1315 return 0; 1316} 1317 1318static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, 1319 unsigned offset, int val) 1320{ 1321 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1322 struct uart_port *port = &s->p[0].port; 1323 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); 1324 1325 if (val) 1326 state |= BIT(offset); 1327 else 1328 state &= ~BIT(offset); 1329 1330 /* 1331 * If we write IOSTATE first, and then IODIR, the output value is not 1332 * transferred to the corresponding I/O pin. 1333 * The datasheet states that each register bit will be transferred to 1334 * the corresponding I/O pin programmed as output when writing to 1335 * IOSTATE. Therefore, configure direction first with IODIR, and then 1336 * set value after with IOSTATE. 1337 */ 1338 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 1339 BIT(offset)); 1340 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); 1341 1342 return 0; 1343} 1344 1345static int sc16is7xx_gpio_init_valid_mask(struct gpio_chip *chip, 1346 unsigned long *valid_mask, 1347 unsigned int ngpios) 1348{ 1349 struct sc16is7xx_port *s = gpiochip_get_data(chip); 1350 1351 *valid_mask = s->gpio_valid_mask; 1352 1353 return 0; 1354} 1355 1356static int sc16is7xx_setup_gpio_chip(struct sc16is7xx_port *s) 1357{ 1358 struct device *dev = s->p[0].port.dev; 1359 1360 if (!s->devtype->nr_gpio) 1361 return 0; 1362 1363 switch (s->mctrl_mask) { 1364 case 0: 1365 s->gpio_valid_mask = GENMASK(7, 0); 1366 break; 1367 case SC16IS7XX_IOCONTROL_MODEM_A_BIT: 1368 s->gpio_valid_mask = GENMASK(3, 0); 1369 break; 1370 case SC16IS7XX_IOCONTROL_MODEM_B_BIT: 1371 s->gpio_valid_mask = GENMASK(7, 4); 1372 break; 1373 default: 1374 break; 1375 } 1376 1377 if (s->gpio_valid_mask == 0) 1378 return 0; 1379 1380 s->gpio.owner = THIS_MODULE; 1381 s->gpio.parent = dev; 1382 s->gpio.label = dev_name(dev); 1383 s->gpio.init_valid_mask = sc16is7xx_gpio_init_valid_mask; 1384 s->gpio.direction_input = sc16is7xx_gpio_direction_input; 1385 s->gpio.get = sc16is7xx_gpio_get; 1386 s->gpio.direction_output = sc16is7xx_gpio_direction_output; 1387 s->gpio.set = sc16is7xx_gpio_set; 1388 s->gpio.base = -1; 1389 s->gpio.ngpio = s->devtype->nr_gpio; 1390 s->gpio.can_sleep = 1; 1391 1392 return gpiochip_add_data(&s->gpio, s); 1393} 1394#endif 1395 1396/* 1397 * Configure ports designated to operate as modem control lines. 1398 */ 1399static int sc16is7xx_setup_mctrl_ports(struct sc16is7xx_port *s, 1400 struct regmap *regmap) 1401{ 1402 int i; 1403 int ret; 1404 int count; 1405 u32 mctrl_port[2]; 1406 struct device *dev = s->p[0].port.dev; 1407 1408 count = device_property_count_u32(dev, "nxp,modem-control-line-ports"); 1409 if (count < 0 || count > ARRAY_SIZE(mctrl_port)) 1410 return 0; 1411 1412 ret = device_property_read_u32_array(dev, "nxp,modem-control-line-ports", 1413 mctrl_port, count); 1414 if (ret) 1415 return ret; 1416 1417 s->mctrl_mask = 0; 1418 1419 for (i = 0; i < count; i++) { 1420 /* Use GPIO lines as modem control lines */ 1421 if (mctrl_port[i] == 0) 1422 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_A_BIT; 1423 else if (mctrl_port[i] == 1) 1424 s->mctrl_mask |= SC16IS7XX_IOCONTROL_MODEM_B_BIT; 1425 } 1426 1427 if (s->mctrl_mask) 1428 regmap_update_bits( 1429 regmap, 1430 SC16IS7XX_IOCONTROL_REG, 1431 SC16IS7XX_IOCONTROL_MODEM_A_BIT | 1432 SC16IS7XX_IOCONTROL_MODEM_B_BIT, s->mctrl_mask); 1433 1434 return 0; 1435} 1436 1437static const struct serial_rs485 sc16is7xx_rs485_supported = { 1438 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND, 1439 .delay_rts_before_send = 1, 1440 .delay_rts_after_send = 1, /* Not supported but keep returning -EINVAL */ 1441}; 1442 1443static int sc16is7xx_probe(struct device *dev, 1444 const struct sc16is7xx_devtype *devtype, 1445 struct regmap *regmaps[], int irq) 1446{ 1447 unsigned long freq = 0, *pfreq = dev_get_platdata(dev); 1448 unsigned int val; 1449 u32 uartclk = 0; 1450 int i, ret; 1451 struct sc16is7xx_port *s; 1452 1453 for (i = 0; i < devtype->nr_uart; i++) 1454 if (IS_ERR(regmaps[i])) 1455 return PTR_ERR(regmaps[i]); 1456 1457 /* 1458 * This device does not have an identification register that would 1459 * tell us if we are really connected to the correct device. 1460 * The best we can do is to check if communication is at all possible. 1461 * 1462 * Note: regmap[0] is used in the probe function to access registers 1463 * common to all channels/ports, as it is guaranteed to be present on 1464 * all variants. 1465 */ 1466 ret = regmap_read(regmaps[0], SC16IS7XX_LSR_REG, &val); 1467 if (ret < 0) 1468 return -EPROBE_DEFER; 1469 1470 /* Alloc port structure */ 1471 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL); 1472 if (!s) { 1473 dev_err(dev, "Error allocating port structure\n"); 1474 return -ENOMEM; 1475 } 1476 1477 /* Always ask for fixed clock rate from a property. */ 1478 device_property_read_u32(dev, "clock-frequency", &uartclk); 1479 1480 s->clk = devm_clk_get_optional(dev, NULL); 1481 if (IS_ERR(s->clk)) 1482 return PTR_ERR(s->clk); 1483 1484 ret = clk_prepare_enable(s->clk); 1485 if (ret) 1486 return ret; 1487 1488 freq = clk_get_rate(s->clk); 1489 if (freq == 0) { 1490 if (uartclk) 1491 freq = uartclk; 1492 if (pfreq) 1493 freq = *pfreq; 1494 if (freq) 1495 dev_dbg(dev, "Clock frequency: %luHz\n", freq); 1496 else 1497 return -EINVAL; 1498 } 1499 1500 s->devtype = devtype; 1501 dev_set_drvdata(dev, s); 1502 1503 kthread_init_worker(&s->kworker); 1504 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker, 1505 "sc16is7xx"); 1506 if (IS_ERR(s->kworker_task)) { 1507 ret = PTR_ERR(s->kworker_task); 1508 goto out_clk; 1509 } 1510 sched_set_fifo(s->kworker_task); 1511 1512 /* reset device, purging any pending irq / data */ 1513 regmap_write(regmaps[0], SC16IS7XX_IOCONTROL_REG, 1514 SC16IS7XX_IOCONTROL_SRESET_BIT); 1515 1516 for (i = 0; i < devtype->nr_uart; ++i) { 1517 s->p[i].port.line = find_first_zero_bit(&sc16is7xx_lines, 1518 SC16IS7XX_MAX_DEVS); 1519 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) { 1520 ret = -ERANGE; 1521 goto out_ports; 1522 } 1523 1524 /* Initialize port data */ 1525 s->p[i].port.dev = dev; 1526 s->p[i].port.irq = irq; 1527 s->p[i].port.type = PORT_SC16IS7XX; 1528 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE; 1529 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1530 s->p[i].port.iobase = i; 1531 /* 1532 * Use all ones as membase to make sure uart_configure_port() in 1533 * serial_core.c does not abort for SPI/I2C devices where the 1534 * membase address is not applicable. 1535 */ 1536 s->p[i].port.membase = (void __iomem *)~0; 1537 s->p[i].port.iotype = UPIO_PORT; 1538 s->p[i].port.uartclk = freq; 1539 s->p[i].port.rs485_config = sc16is7xx_config_rs485; 1540 s->p[i].port.rs485_supported = sc16is7xx_rs485_supported; 1541 s->p[i].port.ops = &sc16is7xx_ops; 1542 s->p[i].old_mctrl = 0; 1543 s->p[i].regmap = regmaps[i]; 1544 1545 mutex_init(&s->p[i].efr_lock); 1546 1547 ret = uart_get_rs485_mode(&s->p[i].port); 1548 if (ret) 1549 goto out_ports; 1550 1551 /* Disable all interrupts */ 1552 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0); 1553 /* Disable TX/RX */ 1554 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG, 1555 SC16IS7XX_EFCR_RXDISABLE_BIT | 1556 SC16IS7XX_EFCR_TXDISABLE_BIT); 1557 1558 /* Initialize kthread work structs */ 1559 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc); 1560 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc); 1561 kthread_init_delayed_work(&s->p[i].ms_work, sc16is7xx_ms_proc); 1562 1563 /* Register port */ 1564 ret = uart_add_one_port(&sc16is7xx_uart, &s->p[i].port); 1565 if (ret) 1566 goto out_ports; 1567 1568 set_bit(s->p[i].port.line, &sc16is7xx_lines); 1569 1570 /* Enable EFR */ 1571 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 1572 SC16IS7XX_LCR_CONF_MODE_B); 1573 1574 regcache_cache_bypass(regmaps[i], true); 1575 1576 /* Enable write access to enhanced features */ 1577 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG, 1578 SC16IS7XX_EFR_ENABLE_BIT); 1579 1580 regcache_cache_bypass(regmaps[i], false); 1581 1582 /* Restore access to general registers */ 1583 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00); 1584 1585 /* Go to suspend mode */ 1586 sc16is7xx_power(&s->p[i].port, 0); 1587 } 1588 1589 if (dev->of_node) { 1590 struct property *prop; 1591 const __be32 *p; 1592 u32 u; 1593 1594 of_property_for_each_u32(dev->of_node, "irda-mode-ports", 1595 prop, p, u) 1596 if (u < devtype->nr_uart) 1597 s->p[u].irda_mode = true; 1598 } 1599 1600 ret = sc16is7xx_setup_mctrl_ports(s, regmaps[0]); 1601 if (ret) 1602 goto out_ports; 1603 1604#ifdef CONFIG_GPIOLIB 1605 ret = sc16is7xx_setup_gpio_chip(s); 1606 if (ret) 1607 goto out_ports; 1608#endif 1609 1610 /* 1611 * Setup interrupt. We first try to acquire the IRQ line as level IRQ. 1612 * If that succeeds, we can allow sharing the interrupt as well. 1613 * In case the interrupt controller doesn't support that, we fall 1614 * back to a non-shared falling-edge trigger. 1615 */ 1616 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1617 IRQF_TRIGGER_LOW | IRQF_SHARED | 1618 IRQF_ONESHOT, 1619 dev_name(dev), s); 1620 if (!ret) 1621 return 0; 1622 1623 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_irq, 1624 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1625 dev_name(dev), s); 1626 if (!ret) 1627 return 0; 1628 1629#ifdef CONFIG_GPIOLIB 1630 if (s->gpio_valid_mask) 1631 gpiochip_remove(&s->gpio); 1632#endif 1633 1634out_ports: 1635 for (i = 0; i < devtype->nr_uart; i++) 1636 if (test_and_clear_bit(s->p[i].port.line, &sc16is7xx_lines)) 1637 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1638 1639 kthread_stop(s->kworker_task); 1640 1641out_clk: 1642 clk_disable_unprepare(s->clk); 1643 1644 return ret; 1645} 1646 1647static void sc16is7xx_remove(struct device *dev) 1648{ 1649 struct sc16is7xx_port *s = dev_get_drvdata(dev); 1650 int i; 1651 1652#ifdef CONFIG_GPIOLIB 1653 if (s->gpio_valid_mask) 1654 gpiochip_remove(&s->gpio); 1655#endif 1656 1657 for (i = 0; i < s->devtype->nr_uart; i++) { 1658 kthread_cancel_delayed_work_sync(&s->p[i].ms_work); 1659 if (test_and_clear_bit(s->p[i].port.line, &sc16is7xx_lines)) 1660 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port); 1661 sc16is7xx_power(&s->p[i].port, 0); 1662 } 1663 1664 kthread_flush_worker(&s->kworker); 1665 kthread_stop(s->kworker_task); 1666 1667 clk_disable_unprepare(s->clk); 1668} 1669 1670static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = { 1671 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, }, 1672 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, }, 1673 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, }, 1674 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, }, 1675 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, }, 1676 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, }, 1677 { } 1678}; 1679MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids); 1680 1681static struct regmap_config regcfg = { 1682 .reg_bits = 5, 1683 .pad_bits = 3, 1684 .val_bits = 8, 1685 .cache_type = REGCACHE_RBTREE, 1686 .volatile_reg = sc16is7xx_regmap_volatile, 1687 .precious_reg = sc16is7xx_regmap_precious, 1688 .writeable_noinc_reg = sc16is7xx_regmap_noinc, 1689 .readable_noinc_reg = sc16is7xx_regmap_noinc, 1690 .max_raw_read = SC16IS7XX_FIFO_SIZE, 1691 .max_raw_write = SC16IS7XX_FIFO_SIZE, 1692 .max_register = SC16IS7XX_EFCR_REG, 1693}; 1694 1695static const char *sc16is7xx_regmap_name(u8 port_id) 1696{ 1697 switch (port_id) { 1698 case 0: return "port0"; 1699 case 1: return "port1"; 1700 default: 1701 WARN_ON(true); 1702 return NULL; 1703 } 1704} 1705 1706static unsigned int sc16is7xx_regmap_port_mask(unsigned int port_id) 1707{ 1708 /* CH1,CH0 are at bits 2:1. */ 1709 return port_id << 1; 1710} 1711 1712#ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1713static int sc16is7xx_spi_probe(struct spi_device *spi) 1714{ 1715 const struct sc16is7xx_devtype *devtype; 1716 struct regmap *regmaps[2]; 1717 unsigned int i; 1718 int ret; 1719 1720 /* Setup SPI bus */ 1721 spi->bits_per_word = 8; 1722 /* For all variants, only mode 0 is supported */ 1723 if ((spi->mode & SPI_MODE_X_MASK) != SPI_MODE_0) 1724 return dev_err_probe(&spi->dev, -EINVAL, "Unsupported SPI mode\n"); 1725 1726 spi->mode = spi->mode ? : SPI_MODE_0; 1727 spi->max_speed_hz = spi->max_speed_hz ? : 4 * HZ_PER_MHZ; 1728 ret = spi_setup(spi); 1729 if (ret) 1730 return ret; 1731 1732 if (spi->dev.of_node) { 1733 devtype = device_get_match_data(&spi->dev); 1734 if (!devtype) 1735 return -ENODEV; 1736 } else { 1737 const struct spi_device_id *id_entry = spi_get_device_id(spi); 1738 1739 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data; 1740 } 1741 1742 for (i = 0; i < devtype->nr_uart; i++) { 1743 regcfg.name = sc16is7xx_regmap_name(i); 1744 /* 1745 * If read_flag_mask is 0, the regmap code sets it to a default 1746 * of 0x80. Since we specify our own mask, we must add the READ 1747 * bit ourselves: 1748 */ 1749 regcfg.read_flag_mask = sc16is7xx_regmap_port_mask(i) | 1750 SC16IS7XX_SPI_READ_BIT; 1751 regcfg.write_flag_mask = sc16is7xx_regmap_port_mask(i); 1752 regmaps[i] = devm_regmap_init_spi(spi, ®cfg); 1753 } 1754 1755 return sc16is7xx_probe(&spi->dev, devtype, regmaps, spi->irq); 1756} 1757 1758static void sc16is7xx_spi_remove(struct spi_device *spi) 1759{ 1760 sc16is7xx_remove(&spi->dev); 1761} 1762 1763static const struct spi_device_id sc16is7xx_spi_id_table[] = { 1764 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1765 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, }, 1766 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, }, 1767 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1768 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1769 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1770 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1771 { } 1772}; 1773 1774MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table); 1775 1776static struct spi_driver sc16is7xx_spi_uart_driver = { 1777 .driver = { 1778 .name = SC16IS7XX_NAME, 1779 .of_match_table = sc16is7xx_dt_ids, 1780 }, 1781 .probe = sc16is7xx_spi_probe, 1782 .remove = sc16is7xx_spi_remove, 1783 .id_table = sc16is7xx_spi_id_table, 1784}; 1785 1786MODULE_ALIAS("spi:sc16is7xx"); 1787#endif 1788 1789#ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1790static int sc16is7xx_i2c_probe(struct i2c_client *i2c) 1791{ 1792 const struct i2c_device_id *id = i2c_client_get_device_id(i2c); 1793 const struct sc16is7xx_devtype *devtype; 1794 struct regmap *regmaps[2]; 1795 unsigned int i; 1796 1797 if (i2c->dev.of_node) { 1798 devtype = device_get_match_data(&i2c->dev); 1799 if (!devtype) 1800 return -ENODEV; 1801 } else { 1802 devtype = (struct sc16is7xx_devtype *)id->driver_data; 1803 } 1804 1805 for (i = 0; i < devtype->nr_uart; i++) { 1806 regcfg.name = sc16is7xx_regmap_name(i); 1807 regcfg.read_flag_mask = sc16is7xx_regmap_port_mask(i); 1808 regcfg.write_flag_mask = sc16is7xx_regmap_port_mask(i); 1809 regmaps[i] = devm_regmap_init_i2c(i2c, ®cfg); 1810 } 1811 1812 return sc16is7xx_probe(&i2c->dev, devtype, regmaps, i2c->irq); 1813} 1814 1815static void sc16is7xx_i2c_remove(struct i2c_client *client) 1816{ 1817 sc16is7xx_remove(&client->dev); 1818} 1819 1820static const struct i2c_device_id sc16is7xx_i2c_id_table[] = { 1821 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, }, 1822 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, }, 1823 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, }, 1824 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, }, 1825 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, }, 1826 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, }, 1827 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, }, 1828 { } 1829}; 1830MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table); 1831 1832static struct i2c_driver sc16is7xx_i2c_uart_driver = { 1833 .driver = { 1834 .name = SC16IS7XX_NAME, 1835 .of_match_table = sc16is7xx_dt_ids, 1836 }, 1837 .probe = sc16is7xx_i2c_probe, 1838 .remove = sc16is7xx_i2c_remove, 1839 .id_table = sc16is7xx_i2c_id_table, 1840}; 1841 1842#endif 1843 1844static int __init sc16is7xx_init(void) 1845{ 1846 int ret; 1847 1848 ret = uart_register_driver(&sc16is7xx_uart); 1849 if (ret) { 1850 pr_err("Registering UART driver failed\n"); 1851 return ret; 1852 } 1853 1854#ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1855 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver); 1856 if (ret < 0) { 1857 pr_err("failed to init sc16is7xx i2c --> %d\n", ret); 1858 goto err_i2c; 1859 } 1860#endif 1861 1862#ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1863 ret = spi_register_driver(&sc16is7xx_spi_uart_driver); 1864 if (ret < 0) { 1865 pr_err("failed to init sc16is7xx spi --> %d\n", ret); 1866 goto err_spi; 1867 } 1868#endif 1869 return ret; 1870 1871#ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1872err_spi: 1873#endif 1874#ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1875 i2c_del_driver(&sc16is7xx_i2c_uart_driver); 1876err_i2c: 1877#endif 1878 uart_unregister_driver(&sc16is7xx_uart); 1879 return ret; 1880} 1881module_init(sc16is7xx_init); 1882 1883static void __exit sc16is7xx_exit(void) 1884{ 1885#ifdef CONFIG_SERIAL_SC16IS7XX_I2C 1886 i2c_del_driver(&sc16is7xx_i2c_uart_driver); 1887#endif 1888 1889#ifdef CONFIG_SERIAL_SC16IS7XX_SPI 1890 spi_unregister_driver(&sc16is7xx_spi_uart_driver); 1891#endif 1892 uart_unregister_driver(&sc16is7xx_uart); 1893} 1894module_exit(sc16is7xx_exit); 1895 1896MODULE_LICENSE("GPL"); 1897MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>"); 1898MODULE_DESCRIPTION("SC16IS7XX serial driver"); 1899