1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Application UART driver for: 4 * Freescale STMP37XX/STMP378X 5 * Alphascale ASM9260 6 * 7 * Author: dmitry pervushin <dimka@embeddedalley.com> 8 * 9 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de> 10 * Provide Alphascale ASM9260 support. 11 * Copyright 2008-2010 Freescale Semiconductor, Inc. 12 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. 13 */ 14 15#include <linux/kernel.h> 16#include <linux/errno.h> 17#include <linux/init.h> 18#include <linux/console.h> 19#include <linux/interrupt.h> 20#include <linux/module.h> 21#include <linux/slab.h> 22#include <linux/wait.h> 23#include <linux/tty.h> 24#include <linux/tty_driver.h> 25#include <linux/tty_flip.h> 26#include <linux/serial.h> 27#include <linux/serial_core.h> 28#include <linux/platform_device.h> 29#include <linux/device.h> 30#include <linux/clk.h> 31#include <linux/delay.h> 32#include <linux/io.h> 33#include <linux/of.h> 34#include <linux/dma-mapping.h> 35#include <linux/dmaengine.h> 36 37#include <linux/gpio/consumer.h> 38#include <linux/err.h> 39#include <linux/irq.h> 40#include "serial_mctrl_gpio.h" 41 42#define MXS_AUART_PORTS 5 43#define MXS_AUART_FIFO_SIZE 16 44 45#define SET_REG 0x4 46#define CLR_REG 0x8 47#define TOG_REG 0xc 48 49#define AUART_CTRL0 0x00000000 50#define AUART_CTRL1 0x00000010 51#define AUART_CTRL2 0x00000020 52#define AUART_LINECTRL 0x00000030 53#define AUART_LINECTRL2 0x00000040 54#define AUART_INTR 0x00000050 55#define AUART_DATA 0x00000060 56#define AUART_STAT 0x00000070 57#define AUART_DEBUG 0x00000080 58#define AUART_VERSION 0x00000090 59#define AUART_AUTOBAUD 0x000000a0 60 61#define AUART_CTRL0_SFTRST (1 << 31) 62#define AUART_CTRL0_CLKGATE (1 << 30) 63#define AUART_CTRL0_RXTO_ENABLE (1 << 27) 64#define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16) 65#define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff) 66 67#define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff) 68 69#define AUART_CTRL2_DMAONERR (1 << 26) 70#define AUART_CTRL2_TXDMAE (1 << 25) 71#define AUART_CTRL2_RXDMAE (1 << 24) 72 73#define AUART_CTRL2_CTSEN (1 << 15) 74#define AUART_CTRL2_RTSEN (1 << 14) 75#define AUART_CTRL2_RTS (1 << 11) 76#define AUART_CTRL2_RXE (1 << 9) 77#define AUART_CTRL2_TXE (1 << 8) 78#define AUART_CTRL2_UARTEN (1 << 0) 79 80#define AUART_LINECTRL_BAUD_DIV_MAX 0x003fffc0 81#define AUART_LINECTRL_BAUD_DIV_MIN 0x000000ec 82#define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16 83#define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000 84#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16) 85#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8 86#define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00 87#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8) 88#define AUART_LINECTRL_SPS (1 << 7) 89#define AUART_LINECTRL_WLEN_MASK 0x00000060 90#define AUART_LINECTRL_WLEN(v) ((((v) - 5) & 0x3) << 5) 91#define AUART_LINECTRL_FEN (1 << 4) 92#define AUART_LINECTRL_STP2 (1 << 3) 93#define AUART_LINECTRL_EPS (1 << 2) 94#define AUART_LINECTRL_PEN (1 << 1) 95#define AUART_LINECTRL_BRK (1 << 0) 96 97#define AUART_INTR_RTIEN (1 << 22) 98#define AUART_INTR_TXIEN (1 << 21) 99#define AUART_INTR_RXIEN (1 << 20) 100#define AUART_INTR_CTSMIEN (1 << 17) 101#define AUART_INTR_RTIS (1 << 6) 102#define AUART_INTR_TXIS (1 << 5) 103#define AUART_INTR_RXIS (1 << 4) 104#define AUART_INTR_CTSMIS (1 << 1) 105 106#define AUART_STAT_BUSY (1 << 29) 107#define AUART_STAT_CTS (1 << 28) 108#define AUART_STAT_TXFE (1 << 27) 109#define AUART_STAT_TXFF (1 << 25) 110#define AUART_STAT_RXFE (1 << 24) 111#define AUART_STAT_OERR (1 << 19) 112#define AUART_STAT_BERR (1 << 18) 113#define AUART_STAT_PERR (1 << 17) 114#define AUART_STAT_FERR (1 << 16) 115#define AUART_STAT_RXCOUNT_MASK 0xffff 116 117/* 118 * Start of Alphascale asm9260 defines 119 * This list contains only differences of existing bits 120 * between imx2x and asm9260 121 */ 122#define ASM9260_HW_CTRL0 0x0000 123/* 124 * RW. Tell the UART to execute the RX DMA Command. The 125 * UART will clear this bit at the end of receive execution. 126 */ 127#define ASM9260_BM_CTRL0_RXDMA_RUN BIT(28) 128/* RW. 0 use FIFO for status register; 1 use DMA */ 129#define ASM9260_BM_CTRL0_RXTO_SOURCE_STATUS BIT(25) 130/* 131 * RW. RX TIMEOUT Enable. Valid for FIFO and DMA. 132 * Warning: If this bit is set to 0, the RX timeout will not affect receive DMA 133 * operation. If this bit is set to 1, a receive timeout will cause the receive 134 * DMA logic to terminate by filling the remaining DMA bytes with garbage data. 135 */ 136#define ASM9260_BM_CTRL0_RXTO_ENABLE BIT(24) 137/* 138 * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before 139 * asserting timeout on the RX input. If the RXFIFO is not empty and the RX 140 * input is idle, then the watchdog counter will decrement each bit-time. Note 141 * 7-bit-time is added to the programmed value, so a value of zero will set 142 * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also 143 * note that the counter is reloaded at the end of each frame, so if the frame 144 * is 10 bits long and the timeout counter value is zero, then timeout will 145 * occur (when FIFO is not empty) even if the RX input is not idle. The default 146 * value is 0x3 (31 bit-time). 147 */ 148#define ASM9260_BM_CTRL0_RXTO_MASK (0xff << 16) 149/* TIMEOUT = (100*7+1)*(1/BAUD) */ 150#define ASM9260_BM_CTRL0_DEFAULT_RXTIMEOUT (20 << 16) 151 152/* TX ctrl register */ 153#define ASM9260_HW_CTRL1 0x0010 154/* 155 * RW. Tell the UART to execute the TX DMA Command. The 156 * UART will clear this bit at the end of transmit execution. 157 */ 158#define ASM9260_BM_CTRL1_TXDMA_RUN BIT(28) 159 160#define ASM9260_HW_CTRL2 0x0020 161/* 162 * RW. Receive Interrupt FIFO Level Select. 163 * The trigger points for the receive interrupt are as follows: 164 * ONE_EIGHTHS = 0x0 Trigger on FIFO full to at least 2 of 16 entries. 165 * ONE_QUARTER = 0x1 Trigger on FIFO full to at least 4 of 16 entries. 166 * ONE_HALF = 0x2 Trigger on FIFO full to at least 8 of 16 entries. 167 * THREE_QUARTERS = 0x3 Trigger on FIFO full to at least 12 of 16 entries. 168 * SEVEN_EIGHTHS = 0x4 Trigger on FIFO full to at least 14 of 16 entries. 169 */ 170#define ASM9260_BM_CTRL2_RXIFLSEL (7 << 20) 171#define ASM9260_BM_CTRL2_DEFAULT_RXIFLSEL (3 << 20) 172/* RW. Same as RXIFLSEL */ 173#define ASM9260_BM_CTRL2_TXIFLSEL (7 << 16) 174#define ASM9260_BM_CTRL2_DEFAULT_TXIFLSEL (2 << 16) 175/* RW. Set DTR. When this bit is 1, the output is 0. */ 176#define ASM9260_BM_CTRL2_DTR BIT(10) 177/* RW. Loop Back Enable */ 178#define ASM9260_BM_CTRL2_LBE BIT(7) 179#define ASM9260_BM_CTRL2_PORT_ENABLE BIT(0) 180 181#define ASM9260_HW_LINECTRL 0x0030 182/* 183 * RW. Stick Parity Select. When bits 1, 2, and 7 of this register are set, the 184 * parity bit is transmitted and checked as a 0. When bits 1 and 7 are set, 185 * and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this 186 * bit is cleared stick parity is disabled. 187 */ 188#define ASM9260_BM_LCTRL_SPS BIT(7) 189/* RW. Word length */ 190#define ASM9260_BM_LCTRL_WLEN (3 << 5) 191#define ASM9260_BM_LCTRL_CHRL_5 (0 << 5) 192#define ASM9260_BM_LCTRL_CHRL_6 (1 << 5) 193#define ASM9260_BM_LCTRL_CHRL_7 (2 << 5) 194#define ASM9260_BM_LCTRL_CHRL_8 (3 << 5) 195 196/* 197 * Interrupt register. 198 * contains the interrupt enables and the interrupt status bits 199 */ 200#define ASM9260_HW_INTR 0x0040 201/* Tx FIFO EMPTY Raw Interrupt enable */ 202#define ASM9260_BM_INTR_TFEIEN BIT(27) 203/* Overrun Error Interrupt Enable. */ 204#define ASM9260_BM_INTR_OEIEN BIT(26) 205/* Break Error Interrupt Enable. */ 206#define ASM9260_BM_INTR_BEIEN BIT(25) 207/* Parity Error Interrupt Enable. */ 208#define ASM9260_BM_INTR_PEIEN BIT(24) 209/* Framing Error Interrupt Enable. */ 210#define ASM9260_BM_INTR_FEIEN BIT(23) 211 212/* nUARTDSR Modem Interrupt Enable. */ 213#define ASM9260_BM_INTR_DSRMIEN BIT(19) 214/* nUARTDCD Modem Interrupt Enable. */ 215#define ASM9260_BM_INTR_DCDMIEN BIT(18) 216/* nUARTRI Modem Interrupt Enable. */ 217#define ASM9260_BM_INTR_RIMIEN BIT(16) 218/* Auto-Boud Timeout */ 219#define ASM9260_BM_INTR_ABTO BIT(13) 220#define ASM9260_BM_INTR_ABEO BIT(12) 221/* Tx FIFO EMPTY Raw Interrupt state */ 222#define ASM9260_BM_INTR_TFEIS BIT(11) 223/* Overrun Error */ 224#define ASM9260_BM_INTR_OEIS BIT(10) 225/* Break Error */ 226#define ASM9260_BM_INTR_BEIS BIT(9) 227/* Parity Error */ 228#define ASM9260_BM_INTR_PEIS BIT(8) 229/* Framing Error */ 230#define ASM9260_BM_INTR_FEIS BIT(7) 231#define ASM9260_BM_INTR_DSRMIS BIT(3) 232#define ASM9260_BM_INTR_DCDMIS BIT(2) 233#define ASM9260_BM_INTR_RIMIS BIT(0) 234 235/* 236 * RW. In DMA mode, up to 4 Received/Transmit characters can be accessed at a 237 * time. In PIO mode, only one character can be accessed at a time. The status 238 * register contains the receive data flags and valid bits. 239 */ 240#define ASM9260_HW_DATA 0x0050 241 242#define ASM9260_HW_STAT 0x0060 243/* RO. If 1, UARTAPP is present in this product. */ 244#define ASM9260_BM_STAT_PRESENT BIT(31) 245/* RO. If 1, HISPEED is present in this product. */ 246#define ASM9260_BM_STAT_HISPEED BIT(30) 247/* RO. Receive FIFO Full. */ 248#define ASM9260_BM_STAT_RXFULL BIT(26) 249 250/* RO. The UART Debug Register contains the state of the DMA signals. */ 251#define ASM9260_HW_DEBUG 0x0070 252/* DMA Command Run Status */ 253#define ASM9260_BM_DEBUG_TXDMARUN BIT(5) 254#define ASM9260_BM_DEBUG_RXDMARUN BIT(4) 255/* DMA Command End Status */ 256#define ASM9260_BM_DEBUG_TXCMDEND BIT(3) 257#define ASM9260_BM_DEBUG_RXCMDEND BIT(2) 258/* DMA Request Status */ 259#define ASM9260_BM_DEBUG_TXDMARQ BIT(1) 260#define ASM9260_BM_DEBUG_RXDMARQ BIT(0) 261 262#define ASM9260_HW_ILPR 0x0080 263 264#define ASM9260_HW_RS485CTRL 0x0090 265/* 266 * RW. This bit reverses the polarity of the direction control signal on the RTS 267 * (or DTR) pin. 268 * If 0, The direction control pin will be driven to logic ‘0’ when the 269 * transmitter has data to be sent. It will be driven to logic ‘1’ after the 270 * last bit of data has been transmitted. 271 */ 272#define ASM9260_BM_RS485CTRL_ONIV BIT(5) 273/* RW. Enable Auto Direction Control. */ 274#define ASM9260_BM_RS485CTRL_DIR_CTRL BIT(4) 275/* 276 * RW. If 0 and DIR_CTRL = 1, pin RTS is used for direction control. 277 * If 1 and DIR_CTRL = 1, pin DTR is used for direction control. 278 */ 279#define ASM9260_BM_RS485CTRL_PINSEL BIT(3) 280/* RW. Enable Auto Address Detect (AAD). */ 281#define ASM9260_BM_RS485CTRL_AADEN BIT(2) 282/* RW. Disable receiver. */ 283#define ASM9260_BM_RS485CTRL_RXDIS BIT(1) 284/* RW. Enable RS-485/EIA-485 Normal Multidrop Mode (NMM) */ 285#define ASM9260_BM_RS485CTRL_RS485EN BIT(0) 286 287#define ASM9260_HW_RS485ADRMATCH 0x00a0 288/* Contains the address match value. */ 289#define ASM9260_BM_RS485ADRMATCH_MASK (0xff << 0) 290 291#define ASM9260_HW_RS485DLY 0x00b0 292/* 293 * RW. Contains the direction control (RTS or DTR) delay value. This delay time 294 * is in periods of the baud clock. 295 */ 296#define ASM9260_BM_RS485DLY_MASK (0xff << 0) 297 298#define ASM9260_HW_AUTOBAUD 0x00c0 299/* WO. Auto-baud time-out interrupt clear bit. */ 300#define ASM9260_BM_AUTOBAUD_TO_INT_CLR BIT(9) 301/* WO. End of auto-baud interrupt clear bit. */ 302#define ASM9260_BM_AUTOBAUD_EO_INT_CLR BIT(8) 303/* Restart in case of timeout (counter restarts at next UART Rx falling edge) */ 304#define ASM9260_BM_AUTOBAUD_AUTORESTART BIT(2) 305/* Auto-baud mode select bit. 0 - Mode 0, 1 - Mode 1. */ 306#define ASM9260_BM_AUTOBAUD_MODE BIT(1) 307/* 308 * Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is 309 * automatically cleared after auto-baud completion. 310 */ 311#define ASM9260_BM_AUTOBAUD_START BIT(0) 312 313#define ASM9260_HW_CTRL3 0x00d0 314#define ASM9260_BM_CTRL3_OUTCLK_DIV_MASK (0xffff << 16) 315/* 316 * RW. Provide clk over OUTCLK pin. In case of asm9260 it can be configured on 317 * pins 137 and 144. 318 */ 319#define ASM9260_BM_CTRL3_MASTERMODE BIT(6) 320/* RW. Baud Rate Mode: 1 - Enable sync mode. 0 - async mode. */ 321#define ASM9260_BM_CTRL3_SYNCMODE BIT(4) 322/* RW. 1 - MSB bit send frist; 0 - LSB bit frist. */ 323#define ASM9260_BM_CTRL3_MSBF BIT(2) 324/* RW. 1 - sample rate = 8 x Baudrate; 0 - sample rate = 16 x Baudrate. */ 325#define ASM9260_BM_CTRL3_BAUD8 BIT(1) 326/* RW. 1 - Set word length to 9bit. 0 - use ASM9260_BM_LCTRL_WLEN */ 327#define ASM9260_BM_CTRL3_9BIT BIT(0) 328 329#define ASM9260_HW_ISO7816_CTRL 0x00e0 330/* RW. Enable High Speed mode. */ 331#define ASM9260_BM_ISO7816CTRL_HS BIT(12) 332/* Disable Successive Receive NACK */ 333#define ASM9260_BM_ISO7816CTRL_DS_NACK BIT(8) 334#define ASM9260_BM_ISO7816CTRL_MAX_ITER_MASK (0xff << 4) 335/* Receive NACK Inhibit */ 336#define ASM9260_BM_ISO7816CTRL_INACK BIT(3) 337#define ASM9260_BM_ISO7816CTRL_NEG_DATA BIT(2) 338/* RW. 1 - ISO7816 mode; 0 - USART mode */ 339#define ASM9260_BM_ISO7816CTRL_ENABLE BIT(0) 340 341#define ASM9260_HW_ISO7816_ERRCNT 0x00f0 342/* Parity error counter. Will be cleared after reading */ 343#define ASM9260_BM_ISO7816_NB_ERRORS_MASK (0xff << 0) 344 345#define ASM9260_HW_ISO7816_STATUS 0x0100 346/* Max number of Repetitions Reached */ 347#define ASM9260_BM_ISO7816_STAT_ITERATION BIT(0) 348 349/* End of Alphascale asm9260 defines */ 350 351static struct uart_driver auart_driver; 352 353enum mxs_auart_type { 354 IMX23_AUART, 355 IMX28_AUART, 356 ASM9260_AUART, 357}; 358 359struct vendor_data { 360 const u16 *reg_offset; 361}; 362 363enum { 364 REG_CTRL0, 365 REG_CTRL1, 366 REG_CTRL2, 367 REG_LINECTRL, 368 REG_LINECTRL2, 369 REG_INTR, 370 REG_DATA, 371 REG_STAT, 372 REG_DEBUG, 373 REG_VERSION, 374 REG_AUTOBAUD, 375 376 /* The size of the array - must be last */ 377 REG_ARRAY_SIZE, 378}; 379 380static const u16 mxs_asm9260_offsets[REG_ARRAY_SIZE] = { 381 [REG_CTRL0] = ASM9260_HW_CTRL0, 382 [REG_CTRL1] = ASM9260_HW_CTRL1, 383 [REG_CTRL2] = ASM9260_HW_CTRL2, 384 [REG_LINECTRL] = ASM9260_HW_LINECTRL, 385 [REG_INTR] = ASM9260_HW_INTR, 386 [REG_DATA] = ASM9260_HW_DATA, 387 [REG_STAT] = ASM9260_HW_STAT, 388 [REG_DEBUG] = ASM9260_HW_DEBUG, 389 [REG_AUTOBAUD] = ASM9260_HW_AUTOBAUD, 390}; 391 392static const u16 mxs_stmp37xx_offsets[REG_ARRAY_SIZE] = { 393 [REG_CTRL0] = AUART_CTRL0, 394 [REG_CTRL1] = AUART_CTRL1, 395 [REG_CTRL2] = AUART_CTRL2, 396 [REG_LINECTRL] = AUART_LINECTRL, 397 [REG_LINECTRL2] = AUART_LINECTRL2, 398 [REG_INTR] = AUART_INTR, 399 [REG_DATA] = AUART_DATA, 400 [REG_STAT] = AUART_STAT, 401 [REG_DEBUG] = AUART_DEBUG, 402 [REG_VERSION] = AUART_VERSION, 403 [REG_AUTOBAUD] = AUART_AUTOBAUD, 404}; 405 406static const struct vendor_data vendor_alphascale_asm9260 = { 407 .reg_offset = mxs_asm9260_offsets, 408}; 409 410static const struct vendor_data vendor_freescale_stmp37xx = { 411 .reg_offset = mxs_stmp37xx_offsets, 412}; 413 414struct mxs_auart_port { 415 struct uart_port port; 416 417#define MXS_AUART_DMA_ENABLED 0x2 418#define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */ 419#define MXS_AUART_DMA_RX_READY 3 /* bit 3 */ 420#define MXS_AUART_RTSCTS 4 /* bit 4 */ 421 unsigned long flags; 422 unsigned int mctrl_prev; 423 enum mxs_auart_type devtype; 424 const struct vendor_data *vendor; 425 426 struct clk *clk; 427 struct clk *clk_ahb; 428 struct device *dev; 429 430 /* for DMA */ 431 struct scatterlist tx_sgl; 432 struct dma_chan *tx_dma_chan; 433 void *tx_dma_buf; 434 435 struct scatterlist rx_sgl; 436 struct dma_chan *rx_dma_chan; 437 void *rx_dma_buf; 438 439 struct mctrl_gpios *gpios; 440 int gpio_irq[UART_GPIO_MAX]; 441 bool ms_irq_enabled; 442}; 443 444static const struct of_device_id mxs_auart_dt_ids[] = { 445 { 446 .compatible = "fsl,imx28-auart", 447 .data = (const void *)IMX28_AUART 448 }, { 449 .compatible = "fsl,imx23-auart", 450 .data = (const void *)IMX23_AUART 451 }, { 452 .compatible = "alphascale,asm9260-auart", 453 .data = (const void *)ASM9260_AUART 454 }, { /* sentinel */ } 455}; 456MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids); 457 458static inline int is_imx28_auart(struct mxs_auart_port *s) 459{ 460 return s->devtype == IMX28_AUART; 461} 462 463static inline int is_asm9260_auart(struct mxs_auart_port *s) 464{ 465 return s->devtype == ASM9260_AUART; 466} 467 468static inline bool auart_dma_enabled(struct mxs_auart_port *s) 469{ 470 return s->flags & MXS_AUART_DMA_ENABLED; 471} 472 473static unsigned int mxs_reg_to_offset(const struct mxs_auart_port *uap, 474 unsigned int reg) 475{ 476 return uap->vendor->reg_offset[reg]; 477} 478 479static unsigned int mxs_read(const struct mxs_auart_port *uap, 480 unsigned int reg) 481{ 482 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg); 483 484 return readl_relaxed(addr); 485} 486 487static void mxs_write(unsigned int val, struct mxs_auart_port *uap, 488 unsigned int reg) 489{ 490 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg); 491 492 writel_relaxed(val, addr); 493} 494 495static void mxs_set(unsigned int val, struct mxs_auart_port *uap, 496 unsigned int reg) 497{ 498 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg); 499 500 writel_relaxed(val, addr + SET_REG); 501} 502 503static void mxs_clr(unsigned int val, struct mxs_auart_port *uap, 504 unsigned int reg) 505{ 506 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg); 507 508 writel_relaxed(val, addr + CLR_REG); 509} 510 511static void mxs_auart_stop_tx(struct uart_port *u); 512 513#define to_auart_port(u) container_of(u, struct mxs_auart_port, port) 514 515static void mxs_auart_tx_chars(struct mxs_auart_port *s); 516 517static void dma_tx_callback(void *param) 518{ 519 struct mxs_auart_port *s = param; 520 struct circ_buf *xmit = &s->port.state->xmit; 521 522 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE); 523 524 /* clear the bit used to serialize the DMA tx. */ 525 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); 526 smp_mb__after_atomic(); 527 528 /* wake up the possible processes. */ 529 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 530 uart_write_wakeup(&s->port); 531 532 mxs_auart_tx_chars(s); 533} 534 535static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size) 536{ 537 struct dma_async_tx_descriptor *desc; 538 struct scatterlist *sgl = &s->tx_sgl; 539 struct dma_chan *channel = s->tx_dma_chan; 540 u32 pio; 541 542 /* [1] : send PIO. Note, the first pio word is CTRL1. */ 543 pio = AUART_CTRL1_XFER_COUNT(size); 544 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio, 545 1, DMA_TRANS_NONE, 0); 546 if (!desc) { 547 dev_err(s->dev, "step 1 error\n"); 548 return -EINVAL; 549 } 550 551 /* [2] : set DMA buffer. */ 552 sg_init_one(sgl, s->tx_dma_buf, size); 553 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE); 554 desc = dmaengine_prep_slave_sg(channel, sgl, 555 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 556 if (!desc) { 557 dev_err(s->dev, "step 2 error\n"); 558 return -EINVAL; 559 } 560 561 /* [3] : submit the DMA */ 562 desc->callback = dma_tx_callback; 563 desc->callback_param = s; 564 dmaengine_submit(desc); 565 dma_async_issue_pending(channel); 566 return 0; 567} 568 569static void mxs_auart_tx_chars(struct mxs_auart_port *s) 570{ 571 struct circ_buf *xmit = &s->port.state->xmit; 572 bool pending; 573 u8 ch; 574 575 if (auart_dma_enabled(s)) { 576 u32 i = 0; 577 int size; 578 void *buffer = s->tx_dma_buf; 579 580 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags)) 581 return; 582 583 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { 584 size = min_t(u32, UART_XMIT_SIZE - i, 585 CIRC_CNT_TO_END(xmit->head, 586 xmit->tail, 587 UART_XMIT_SIZE)); 588 memcpy(buffer + i, xmit->buf + xmit->tail, size); 589 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1); 590 591 i += size; 592 if (i >= UART_XMIT_SIZE) 593 break; 594 } 595 596 if (uart_tx_stopped(&s->port)) 597 mxs_auart_stop_tx(&s->port); 598 599 if (i) { 600 mxs_auart_dma_tx(s, i); 601 } else { 602 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); 603 smp_mb__after_atomic(); 604 } 605 return; 606 } 607 608 pending = uart_port_tx_flags(&s->port, ch, UART_TX_NOSTOP, 609 !(mxs_read(s, REG_STAT) & AUART_STAT_TXFF), 610 mxs_write(ch, s, REG_DATA)); 611 if (pending) 612 mxs_set(AUART_INTR_TXIEN, s, REG_INTR); 613 else 614 mxs_clr(AUART_INTR_TXIEN, s, REG_INTR); 615 616 if (uart_tx_stopped(&s->port)) 617 mxs_auart_stop_tx(&s->port); 618} 619 620static void mxs_auart_rx_char(struct mxs_auart_port *s) 621{ 622 u32 stat; 623 u8 c, flag; 624 625 c = mxs_read(s, REG_DATA); 626 stat = mxs_read(s, REG_STAT); 627 628 flag = TTY_NORMAL; 629 s->port.icount.rx++; 630 631 if (stat & AUART_STAT_BERR) { 632 s->port.icount.brk++; 633 if (uart_handle_break(&s->port)) 634 goto out; 635 } else if (stat & AUART_STAT_PERR) { 636 s->port.icount.parity++; 637 } else if (stat & AUART_STAT_FERR) { 638 s->port.icount.frame++; 639 } 640 641 /* 642 * Mask off conditions which should be ingored. 643 */ 644 stat &= s->port.read_status_mask; 645 646 if (stat & AUART_STAT_BERR) { 647 flag = TTY_BREAK; 648 } else if (stat & AUART_STAT_PERR) 649 flag = TTY_PARITY; 650 else if (stat & AUART_STAT_FERR) 651 flag = TTY_FRAME; 652 653 if (stat & AUART_STAT_OERR) 654 s->port.icount.overrun++; 655 656 if (uart_handle_sysrq_char(&s->port, c)) 657 goto out; 658 659 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag); 660out: 661 mxs_write(stat, s, REG_STAT); 662} 663 664static void mxs_auart_rx_chars(struct mxs_auart_port *s) 665{ 666 u32 stat = 0; 667 668 for (;;) { 669 stat = mxs_read(s, REG_STAT); 670 if (stat & AUART_STAT_RXFE) 671 break; 672 mxs_auart_rx_char(s); 673 } 674 675 mxs_write(stat, s, REG_STAT); 676 tty_flip_buffer_push(&s->port.state->port); 677} 678 679static int mxs_auart_request_port(struct uart_port *u) 680{ 681 return 0; 682} 683 684static int mxs_auart_verify_port(struct uart_port *u, 685 struct serial_struct *ser) 686{ 687 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX) 688 return -EINVAL; 689 return 0; 690} 691 692static void mxs_auart_config_port(struct uart_port *u, int flags) 693{ 694} 695 696static const char *mxs_auart_type(struct uart_port *u) 697{ 698 struct mxs_auart_port *s = to_auart_port(u); 699 700 return dev_name(s->dev); 701} 702 703static void mxs_auart_release_port(struct uart_port *u) 704{ 705} 706 707static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl) 708{ 709 struct mxs_auart_port *s = to_auart_port(u); 710 711 u32 ctrl = mxs_read(s, REG_CTRL2); 712 713 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS); 714 if (mctrl & TIOCM_RTS) { 715 if (uart_cts_enabled(u)) 716 ctrl |= AUART_CTRL2_RTSEN; 717 else 718 ctrl |= AUART_CTRL2_RTS; 719 } 720 721 mxs_write(ctrl, s, REG_CTRL2); 722 723 mctrl_gpio_set(s->gpios, mctrl); 724} 725 726#define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS) 727static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl) 728{ 729 u32 mctrl_diff; 730 731 mctrl_diff = mctrl ^ s->mctrl_prev; 732 s->mctrl_prev = mctrl; 733 if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled && 734 s->port.state != NULL) { 735 if (mctrl_diff & TIOCM_RI) 736 s->port.icount.rng++; 737 if (mctrl_diff & TIOCM_DSR) 738 s->port.icount.dsr++; 739 if (mctrl_diff & TIOCM_CD) 740 uart_handle_dcd_change(&s->port, mctrl & TIOCM_CD); 741 if (mctrl_diff & TIOCM_CTS) 742 uart_handle_cts_change(&s->port, mctrl & TIOCM_CTS); 743 744 wake_up_interruptible(&s->port.state->port.delta_msr_wait); 745 } 746 return mctrl; 747} 748 749static u32 mxs_auart_get_mctrl(struct uart_port *u) 750{ 751 struct mxs_auart_port *s = to_auart_port(u); 752 u32 stat = mxs_read(s, REG_STAT); 753 u32 mctrl = 0; 754 755 if (stat & AUART_STAT_CTS) 756 mctrl |= TIOCM_CTS; 757 758 return mctrl_gpio_get(s->gpios, &mctrl); 759} 760 761/* 762 * Enable modem status interrupts 763 */ 764static void mxs_auart_enable_ms(struct uart_port *port) 765{ 766 struct mxs_auart_port *s = to_auart_port(port); 767 768 /* 769 * Interrupt should not be enabled twice 770 */ 771 if (s->ms_irq_enabled) 772 return; 773 774 s->ms_irq_enabled = true; 775 776 if (s->gpio_irq[UART_GPIO_CTS] >= 0) 777 enable_irq(s->gpio_irq[UART_GPIO_CTS]); 778 /* TODO: enable AUART_INTR_CTSMIEN otherwise */ 779 780 if (s->gpio_irq[UART_GPIO_DSR] >= 0) 781 enable_irq(s->gpio_irq[UART_GPIO_DSR]); 782 783 if (s->gpio_irq[UART_GPIO_RI] >= 0) 784 enable_irq(s->gpio_irq[UART_GPIO_RI]); 785 786 if (s->gpio_irq[UART_GPIO_DCD] >= 0) 787 enable_irq(s->gpio_irq[UART_GPIO_DCD]); 788} 789 790/* 791 * Disable modem status interrupts 792 */ 793static void mxs_auart_disable_ms(struct uart_port *port) 794{ 795 struct mxs_auart_port *s = to_auart_port(port); 796 797 /* 798 * Interrupt should not be disabled twice 799 */ 800 if (!s->ms_irq_enabled) 801 return; 802 803 s->ms_irq_enabled = false; 804 805 if (s->gpio_irq[UART_GPIO_CTS] >= 0) 806 disable_irq(s->gpio_irq[UART_GPIO_CTS]); 807 /* TODO: disable AUART_INTR_CTSMIEN otherwise */ 808 809 if (s->gpio_irq[UART_GPIO_DSR] >= 0) 810 disable_irq(s->gpio_irq[UART_GPIO_DSR]); 811 812 if (s->gpio_irq[UART_GPIO_RI] >= 0) 813 disable_irq(s->gpio_irq[UART_GPIO_RI]); 814 815 if (s->gpio_irq[UART_GPIO_DCD] >= 0) 816 disable_irq(s->gpio_irq[UART_GPIO_DCD]); 817} 818 819static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s); 820static void dma_rx_callback(void *arg) 821{ 822 struct mxs_auart_port *s = (struct mxs_auart_port *) arg; 823 struct tty_port *port = &s->port.state->port; 824 int count; 825 u32 stat; 826 827 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE); 828 829 stat = mxs_read(s, REG_STAT); 830 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR | 831 AUART_STAT_PERR | AUART_STAT_FERR); 832 833 count = stat & AUART_STAT_RXCOUNT_MASK; 834 tty_insert_flip_string(port, s->rx_dma_buf, count); 835 836 mxs_write(stat, s, REG_STAT); 837 tty_flip_buffer_push(port); 838 839 /* start the next DMA for RX. */ 840 mxs_auart_dma_prep_rx(s); 841} 842 843static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s) 844{ 845 struct dma_async_tx_descriptor *desc; 846 struct scatterlist *sgl = &s->rx_sgl; 847 struct dma_chan *channel = s->rx_dma_chan; 848 u32 pio[1]; 849 850 /* [1] : send PIO */ 851 pio[0] = AUART_CTRL0_RXTO_ENABLE 852 | AUART_CTRL0_RXTIMEOUT(0x80) 853 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE); 854 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio, 855 1, DMA_TRANS_NONE, 0); 856 if (!desc) { 857 dev_err(s->dev, "step 1 error\n"); 858 return -EINVAL; 859 } 860 861 /* [2] : send DMA request */ 862 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE); 863 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE); 864 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM, 865 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 866 if (!desc) { 867 dev_err(s->dev, "step 2 error\n"); 868 return -1; 869 } 870 871 /* [3] : submit the DMA, but do not issue it. */ 872 desc->callback = dma_rx_callback; 873 desc->callback_param = s; 874 dmaengine_submit(desc); 875 dma_async_issue_pending(channel); 876 return 0; 877} 878 879static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s) 880{ 881 if (s->tx_dma_chan) { 882 dma_release_channel(s->tx_dma_chan); 883 s->tx_dma_chan = NULL; 884 } 885 if (s->rx_dma_chan) { 886 dma_release_channel(s->rx_dma_chan); 887 s->rx_dma_chan = NULL; 888 } 889 890 kfree(s->tx_dma_buf); 891 kfree(s->rx_dma_buf); 892 s->tx_dma_buf = NULL; 893 s->rx_dma_buf = NULL; 894} 895 896static void mxs_auart_dma_exit(struct mxs_auart_port *s) 897{ 898 899 mxs_clr(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR, 900 s, REG_CTRL2); 901 902 mxs_auart_dma_exit_channel(s); 903 s->flags &= ~MXS_AUART_DMA_ENABLED; 904 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); 905 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags); 906} 907 908static int mxs_auart_dma_init(struct mxs_auart_port *s) 909{ 910 if (auart_dma_enabled(s)) 911 return 0; 912 913 /* init for RX */ 914 s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx"); 915 if (!s->rx_dma_chan) 916 goto err_out; 917 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA); 918 if (!s->rx_dma_buf) 919 goto err_out; 920 921 /* init for TX */ 922 s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx"); 923 if (!s->tx_dma_chan) 924 goto err_out; 925 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA); 926 if (!s->tx_dma_buf) 927 goto err_out; 928 929 /* set the flags */ 930 s->flags |= MXS_AUART_DMA_ENABLED; 931 dev_dbg(s->dev, "enabled the DMA support."); 932 933 /* The DMA buffer is now the FIFO the TTY subsystem can use */ 934 s->port.fifosize = UART_XMIT_SIZE; 935 936 return 0; 937 938err_out: 939 mxs_auart_dma_exit_channel(s); 940 return -EINVAL; 941 942} 943 944#define RTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_RTS) 945#define CTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_CTS) 946static void mxs_auart_settermios(struct uart_port *u, 947 struct ktermios *termios, 948 const struct ktermios *old) 949{ 950 struct mxs_auart_port *s = to_auart_port(u); 951 u32 ctrl, ctrl2, div; 952 unsigned int cflag, baud, baud_min, baud_max; 953 954 cflag = termios->c_cflag; 955 956 ctrl = AUART_LINECTRL_FEN; 957 ctrl2 = mxs_read(s, REG_CTRL2); 958 959 ctrl |= AUART_LINECTRL_WLEN(tty_get_char_size(cflag)); 960 961 /* parity */ 962 if (cflag & PARENB) { 963 ctrl |= AUART_LINECTRL_PEN; 964 if ((cflag & PARODD) == 0) 965 ctrl |= AUART_LINECTRL_EPS; 966 if (cflag & CMSPAR) 967 ctrl |= AUART_LINECTRL_SPS; 968 } 969 970 u->read_status_mask = AUART_STAT_OERR; 971 972 if (termios->c_iflag & INPCK) 973 u->read_status_mask |= AUART_STAT_PERR; 974 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 975 u->read_status_mask |= AUART_STAT_BERR; 976 977 /* 978 * Characters to ignore 979 */ 980 u->ignore_status_mask = 0; 981 if (termios->c_iflag & IGNPAR) 982 u->ignore_status_mask |= AUART_STAT_PERR; 983 if (termios->c_iflag & IGNBRK) { 984 u->ignore_status_mask |= AUART_STAT_BERR; 985 /* 986 * If we're ignoring parity and break indicators, 987 * ignore overruns too (for real raw support). 988 */ 989 if (termios->c_iflag & IGNPAR) 990 u->ignore_status_mask |= AUART_STAT_OERR; 991 } 992 993 /* 994 * ignore all characters if CREAD is not set 995 */ 996 if (cflag & CREAD) 997 ctrl2 |= AUART_CTRL2_RXE; 998 else 999 ctrl2 &= ~AUART_CTRL2_RXE; 1000 1001 /* figure out the stop bits requested */ 1002 if (cflag & CSTOPB) 1003 ctrl |= AUART_LINECTRL_STP2; 1004 1005 /* figure out the hardware flow control settings */ 1006 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN); 1007 if (cflag & CRTSCTS) { 1008 /* 1009 * The DMA has a bug(see errata:2836) in mx23. 1010 * So we can not implement the DMA for auart in mx23, 1011 * we can only implement the DMA support for auart 1012 * in mx28. 1013 */ 1014 if (is_imx28_auart(s) 1015 && test_bit(MXS_AUART_RTSCTS, &s->flags)) { 1016 if (!mxs_auart_dma_init(s)) 1017 /* enable DMA tranfer */ 1018 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE 1019 | AUART_CTRL2_DMAONERR; 1020 } 1021 /* Even if RTS is GPIO line RTSEN can be enabled because 1022 * the pinctrl configuration decides about RTS pin function */ 1023 ctrl2 |= AUART_CTRL2_RTSEN; 1024 if (CTS_AT_AUART()) 1025 ctrl2 |= AUART_CTRL2_CTSEN; 1026 } 1027 1028 /* set baud rate */ 1029 if (is_asm9260_auart(s)) { 1030 baud = uart_get_baud_rate(u, termios, old, 1031 u->uartclk * 4 / 0x3FFFFF, 1032 u->uartclk / 16); 1033 div = u->uartclk * 4 / baud; 1034 } else { 1035 baud_min = DIV_ROUND_UP(u->uartclk * 32, 1036 AUART_LINECTRL_BAUD_DIV_MAX); 1037 baud_max = u->uartclk * 32 / AUART_LINECTRL_BAUD_DIV_MIN; 1038 baud = uart_get_baud_rate(u, termios, old, baud_min, baud_max); 1039 div = DIV_ROUND_CLOSEST(u->uartclk * 32, baud); 1040 } 1041 1042 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F); 1043 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6); 1044 mxs_write(ctrl, s, REG_LINECTRL); 1045 1046 mxs_write(ctrl2, s, REG_CTRL2); 1047 1048 uart_update_timeout(u, termios->c_cflag, baud); 1049 1050 /* prepare for the DMA RX. */ 1051 if (auart_dma_enabled(s) && 1052 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) { 1053 if (!mxs_auart_dma_prep_rx(s)) { 1054 /* Disable the normal RX interrupt. */ 1055 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN, 1056 s, REG_INTR); 1057 } else { 1058 mxs_auart_dma_exit(s); 1059 dev_err(s->dev, "We can not start up the DMA.\n"); 1060 } 1061 } 1062 1063 /* CTS flow-control and modem-status interrupts */ 1064 if (UART_ENABLE_MS(u, termios->c_cflag)) 1065 mxs_auart_enable_ms(u); 1066 else 1067 mxs_auart_disable_ms(u); 1068} 1069 1070static void mxs_auart_set_ldisc(struct uart_port *port, 1071 struct ktermios *termios) 1072{ 1073 if (termios->c_line == N_PPS) { 1074 port->flags |= UPF_HARDPPS_CD; 1075 mxs_auart_enable_ms(port); 1076 } else { 1077 port->flags &= ~UPF_HARDPPS_CD; 1078 } 1079} 1080 1081static irqreturn_t mxs_auart_irq_handle(int irq, void *context) 1082{ 1083 u32 istat; 1084 struct mxs_auart_port *s = context; 1085 u32 mctrl_temp = s->mctrl_prev; 1086 u32 stat = mxs_read(s, REG_STAT); 1087 1088 istat = mxs_read(s, REG_INTR); 1089 1090 /* ack irq */ 1091 mxs_clr(istat & (AUART_INTR_RTIS | AUART_INTR_TXIS | AUART_INTR_RXIS 1092 | AUART_INTR_CTSMIS), s, REG_INTR); 1093 1094 /* 1095 * Dealing with GPIO interrupt 1096 */ 1097 if (irq == s->gpio_irq[UART_GPIO_CTS] || 1098 irq == s->gpio_irq[UART_GPIO_DCD] || 1099 irq == s->gpio_irq[UART_GPIO_DSR] || 1100 irq == s->gpio_irq[UART_GPIO_RI]) 1101 mxs_auart_modem_status(s, 1102 mctrl_gpio_get(s->gpios, &mctrl_temp)); 1103 1104 if (istat & AUART_INTR_CTSMIS) { 1105 if (CTS_AT_AUART() && s->ms_irq_enabled) 1106 uart_handle_cts_change(&s->port, 1107 stat & AUART_STAT_CTS); 1108 mxs_clr(AUART_INTR_CTSMIS, s, REG_INTR); 1109 istat &= ~AUART_INTR_CTSMIS; 1110 } 1111 1112 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) { 1113 if (!auart_dma_enabled(s)) 1114 mxs_auart_rx_chars(s); 1115 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS); 1116 } 1117 1118 if (istat & AUART_INTR_TXIS) { 1119 mxs_auart_tx_chars(s); 1120 istat &= ~AUART_INTR_TXIS; 1121 } 1122 1123 return IRQ_HANDLED; 1124} 1125 1126static void mxs_auart_reset_deassert(struct mxs_auart_port *s) 1127{ 1128 int i; 1129 unsigned int reg; 1130 1131 mxs_clr(AUART_CTRL0_SFTRST, s, REG_CTRL0); 1132 1133 for (i = 0; i < 10000; i++) { 1134 reg = mxs_read(s, REG_CTRL0); 1135 if (!(reg & AUART_CTRL0_SFTRST)) 1136 break; 1137 udelay(3); 1138 } 1139 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0); 1140} 1141 1142static void mxs_auart_reset_assert(struct mxs_auart_port *s) 1143{ 1144 int i; 1145 u32 reg; 1146 1147 reg = mxs_read(s, REG_CTRL0); 1148 /* if already in reset state, keep it untouched */ 1149 if (reg & AUART_CTRL0_SFTRST) 1150 return; 1151 1152 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0); 1153 mxs_set(AUART_CTRL0_SFTRST, s, REG_CTRL0); 1154 1155 for (i = 0; i < 1000; i++) { 1156 reg = mxs_read(s, REG_CTRL0); 1157 /* reset is finished when the clock is gated */ 1158 if (reg & AUART_CTRL0_CLKGATE) 1159 return; 1160 udelay(10); 1161 } 1162 1163 dev_err(s->dev, "Failed to reset the unit."); 1164} 1165 1166static int mxs_auart_startup(struct uart_port *u) 1167{ 1168 int ret; 1169 struct mxs_auart_port *s = to_auart_port(u); 1170 1171 ret = clk_prepare_enable(s->clk); 1172 if (ret) 1173 return ret; 1174 1175 if (uart_console(u)) { 1176 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0); 1177 } else { 1178 /* reset the unit to a well known state */ 1179 mxs_auart_reset_assert(s); 1180 mxs_auart_reset_deassert(s); 1181 } 1182 1183 mxs_set(AUART_CTRL2_UARTEN, s, REG_CTRL2); 1184 1185 mxs_write(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN, 1186 s, REG_INTR); 1187 1188 /* Reset FIFO size (it could have changed if DMA was enabled) */ 1189 u->fifosize = MXS_AUART_FIFO_SIZE; 1190 1191 /* 1192 * Enable fifo so all four bytes of a DMA word are written to 1193 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes) 1194 */ 1195 mxs_set(AUART_LINECTRL_FEN, s, REG_LINECTRL); 1196 1197 /* get initial status of modem lines */ 1198 mctrl_gpio_get(s->gpios, &s->mctrl_prev); 1199 1200 s->ms_irq_enabled = false; 1201 return 0; 1202} 1203 1204static void mxs_auart_shutdown(struct uart_port *u) 1205{ 1206 struct mxs_auart_port *s = to_auart_port(u); 1207 1208 mxs_auart_disable_ms(u); 1209 1210 if (auart_dma_enabled(s)) 1211 mxs_auart_dma_exit(s); 1212 1213 if (uart_console(u)) { 1214 mxs_clr(AUART_CTRL2_UARTEN, s, REG_CTRL2); 1215 1216 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN | 1217 AUART_INTR_CTSMIEN, s, REG_INTR); 1218 mxs_set(AUART_CTRL0_CLKGATE, s, REG_CTRL0); 1219 } else { 1220 mxs_auart_reset_assert(s); 1221 } 1222 1223 clk_disable_unprepare(s->clk); 1224} 1225 1226static unsigned int mxs_auart_tx_empty(struct uart_port *u) 1227{ 1228 struct mxs_auart_port *s = to_auart_port(u); 1229 1230 if ((mxs_read(s, REG_STAT) & 1231 (AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE) 1232 return TIOCSER_TEMT; 1233 1234 return 0; 1235} 1236 1237static void mxs_auart_start_tx(struct uart_port *u) 1238{ 1239 struct mxs_auart_port *s = to_auart_port(u); 1240 1241 /* enable transmitter */ 1242 mxs_set(AUART_CTRL2_TXE, s, REG_CTRL2); 1243 1244 mxs_auart_tx_chars(s); 1245} 1246 1247static void mxs_auart_stop_tx(struct uart_port *u) 1248{ 1249 struct mxs_auart_port *s = to_auart_port(u); 1250 1251 mxs_clr(AUART_CTRL2_TXE, s, REG_CTRL2); 1252} 1253 1254static void mxs_auart_stop_rx(struct uart_port *u) 1255{ 1256 struct mxs_auart_port *s = to_auart_port(u); 1257 1258 mxs_clr(AUART_CTRL2_RXE, s, REG_CTRL2); 1259} 1260 1261static void mxs_auart_break_ctl(struct uart_port *u, int ctl) 1262{ 1263 struct mxs_auart_port *s = to_auart_port(u); 1264 1265 if (ctl) 1266 mxs_set(AUART_LINECTRL_BRK, s, REG_LINECTRL); 1267 else 1268 mxs_clr(AUART_LINECTRL_BRK, s, REG_LINECTRL); 1269} 1270 1271static const struct uart_ops mxs_auart_ops = { 1272 .tx_empty = mxs_auart_tx_empty, 1273 .start_tx = mxs_auart_start_tx, 1274 .stop_tx = mxs_auart_stop_tx, 1275 .stop_rx = mxs_auart_stop_rx, 1276 .enable_ms = mxs_auart_enable_ms, 1277 .break_ctl = mxs_auart_break_ctl, 1278 .set_mctrl = mxs_auart_set_mctrl, 1279 .get_mctrl = mxs_auart_get_mctrl, 1280 .startup = mxs_auart_startup, 1281 .shutdown = mxs_auart_shutdown, 1282 .set_termios = mxs_auart_settermios, 1283 .set_ldisc = mxs_auart_set_ldisc, 1284 .type = mxs_auart_type, 1285 .release_port = mxs_auart_release_port, 1286 .request_port = mxs_auart_request_port, 1287 .config_port = mxs_auart_config_port, 1288 .verify_port = mxs_auart_verify_port, 1289}; 1290 1291static struct mxs_auart_port *auart_port[MXS_AUART_PORTS]; 1292 1293#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE 1294static void mxs_auart_console_putchar(struct uart_port *port, unsigned char ch) 1295{ 1296 struct mxs_auart_port *s = to_auart_port(port); 1297 unsigned int to = 1000; 1298 1299 while (mxs_read(s, REG_STAT) & AUART_STAT_TXFF) { 1300 if (!to--) 1301 break; 1302 udelay(1); 1303 } 1304 1305 mxs_write(ch, s, REG_DATA); 1306} 1307 1308static void 1309auart_console_write(struct console *co, const char *str, unsigned int count) 1310{ 1311 struct mxs_auart_port *s; 1312 struct uart_port *port; 1313 unsigned int old_ctrl0, old_ctrl2; 1314 unsigned int to = 20000; 1315 1316 if (co->index >= MXS_AUART_PORTS || co->index < 0) 1317 return; 1318 1319 s = auart_port[co->index]; 1320 port = &s->port; 1321 1322 clk_enable(s->clk); 1323 1324 /* First save the CR then disable the interrupts */ 1325 old_ctrl2 = mxs_read(s, REG_CTRL2); 1326 old_ctrl0 = mxs_read(s, REG_CTRL0); 1327 1328 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0); 1329 mxs_set(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, s, REG_CTRL2); 1330 1331 uart_console_write(port, str, count, mxs_auart_console_putchar); 1332 1333 /* Finally, wait for transmitter to become empty ... */ 1334 while (mxs_read(s, REG_STAT) & AUART_STAT_BUSY) { 1335 udelay(1); 1336 if (!to--) 1337 break; 1338 } 1339 1340 /* 1341 * ... and restore the TCR if we waited long enough for the transmitter 1342 * to be idle. This might keep the transmitter enabled although it is 1343 * unused, but that is better than to disable it while it is still 1344 * transmitting. 1345 */ 1346 if (!(mxs_read(s, REG_STAT) & AUART_STAT_BUSY)) { 1347 mxs_write(old_ctrl0, s, REG_CTRL0); 1348 mxs_write(old_ctrl2, s, REG_CTRL2); 1349 } 1350 1351 clk_disable(s->clk); 1352} 1353 1354static void __init 1355auart_console_get_options(struct mxs_auart_port *s, int *baud, 1356 int *parity, int *bits) 1357{ 1358 struct uart_port *port = &s->port; 1359 unsigned int lcr_h, quot; 1360 1361 if (!(mxs_read(s, REG_CTRL2) & AUART_CTRL2_UARTEN)) 1362 return; 1363 1364 lcr_h = mxs_read(s, REG_LINECTRL); 1365 1366 *parity = 'n'; 1367 if (lcr_h & AUART_LINECTRL_PEN) { 1368 if (lcr_h & AUART_LINECTRL_EPS) 1369 *parity = 'e'; 1370 else 1371 *parity = 'o'; 1372 } 1373 1374 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(7)) 1375 *bits = 7; 1376 else 1377 *bits = 8; 1378 1379 quot = ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVINT_MASK)) 1380 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6); 1381 quot |= ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVFRAC_MASK)) 1382 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT; 1383 if (quot == 0) 1384 quot = 1; 1385 1386 *baud = (port->uartclk << 2) / quot; 1387} 1388 1389static int __init 1390auart_console_setup(struct console *co, char *options) 1391{ 1392 struct mxs_auart_port *s; 1393 int baud = 9600; 1394 int bits = 8; 1395 int parity = 'n'; 1396 int flow = 'n'; 1397 int ret; 1398 1399 /* 1400 * Check whether an invalid uart number has been specified, and 1401 * if so, search for the first available port that does have 1402 * console support. 1403 */ 1404 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port)) 1405 co->index = 0; 1406 s = auart_port[co->index]; 1407 if (!s) 1408 return -ENODEV; 1409 1410 ret = clk_prepare_enable(s->clk); 1411 if (ret) 1412 return ret; 1413 1414 if (options) 1415 uart_parse_options(options, &baud, &parity, &bits, &flow); 1416 else 1417 auart_console_get_options(s, &baud, &parity, &bits); 1418 1419 ret = uart_set_options(&s->port, co, baud, parity, bits, flow); 1420 1421 clk_disable_unprepare(s->clk); 1422 1423 return ret; 1424} 1425 1426static struct console auart_console = { 1427 .name = "ttyAPP", 1428 .write = auart_console_write, 1429 .device = uart_console_device, 1430 .setup = auart_console_setup, 1431 .flags = CON_PRINTBUFFER, 1432 .index = -1, 1433 .data = &auart_driver, 1434}; 1435#endif 1436 1437static struct uart_driver auart_driver = { 1438 .owner = THIS_MODULE, 1439 .driver_name = "ttyAPP", 1440 .dev_name = "ttyAPP", 1441 .major = 0, 1442 .minor = 0, 1443 .nr = MXS_AUART_PORTS, 1444#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE 1445 .cons = &auart_console, 1446#endif 1447}; 1448 1449static void mxs_init_regs(struct mxs_auart_port *s) 1450{ 1451 if (is_asm9260_auart(s)) 1452 s->vendor = &vendor_alphascale_asm9260; 1453 else 1454 s->vendor = &vendor_freescale_stmp37xx; 1455} 1456 1457static int mxs_get_clks(struct mxs_auart_port *s, 1458 struct platform_device *pdev) 1459{ 1460 int err; 1461 1462 if (!is_asm9260_auart(s)) { 1463 s->clk = devm_clk_get(&pdev->dev, NULL); 1464 return PTR_ERR_OR_ZERO(s->clk); 1465 } 1466 1467 s->clk = devm_clk_get(s->dev, "mod"); 1468 if (IS_ERR(s->clk)) { 1469 dev_err(s->dev, "Failed to get \"mod\" clk\n"); 1470 return PTR_ERR(s->clk); 1471 } 1472 1473 s->clk_ahb = devm_clk_get(s->dev, "ahb"); 1474 if (IS_ERR(s->clk_ahb)) { 1475 dev_err(s->dev, "Failed to get \"ahb\" clk\n"); 1476 return PTR_ERR(s->clk_ahb); 1477 } 1478 1479 err = clk_prepare_enable(s->clk_ahb); 1480 if (err) { 1481 dev_err(s->dev, "Failed to enable ahb_clk!\n"); 1482 return err; 1483 } 1484 1485 err = clk_set_rate(s->clk, clk_get_rate(s->clk_ahb)); 1486 if (err) { 1487 dev_err(s->dev, "Failed to set rate!\n"); 1488 goto disable_clk_ahb; 1489 } 1490 1491 err = clk_prepare_enable(s->clk); 1492 if (err) { 1493 dev_err(s->dev, "Failed to enable clk!\n"); 1494 goto disable_clk_ahb; 1495 } 1496 1497 return 0; 1498 1499disable_clk_ahb: 1500 clk_disable_unprepare(s->clk_ahb); 1501 return err; 1502} 1503 1504static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev) 1505{ 1506 enum mctrl_gpio_idx i; 1507 struct gpio_desc *gpiod; 1508 1509 s->gpios = mctrl_gpio_init_noauto(dev, 0); 1510 if (IS_ERR(s->gpios)) 1511 return PTR_ERR(s->gpios); 1512 1513 /* Block (enabled before) DMA option if RTS or CTS is GPIO line */ 1514 if (!RTS_AT_AUART() || !CTS_AT_AUART()) { 1515 if (test_bit(MXS_AUART_RTSCTS, &s->flags)) 1516 dev_warn(dev, 1517 "DMA and flow control via gpio may cause some problems. DMA disabled!\n"); 1518 clear_bit(MXS_AUART_RTSCTS, &s->flags); 1519 } 1520 1521 for (i = 0; i < UART_GPIO_MAX; i++) { 1522 gpiod = mctrl_gpio_to_gpiod(s->gpios, i); 1523 if (gpiod && (gpiod_get_direction(gpiod) == 1)) 1524 s->gpio_irq[i] = gpiod_to_irq(gpiod); 1525 else 1526 s->gpio_irq[i] = -EINVAL; 1527 } 1528 1529 return 0; 1530} 1531 1532static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s) 1533{ 1534 enum mctrl_gpio_idx i; 1535 1536 for (i = 0; i < UART_GPIO_MAX; i++) 1537 if (s->gpio_irq[i] >= 0) 1538 free_irq(s->gpio_irq[i], s); 1539} 1540 1541static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s) 1542{ 1543 int *irq = s->gpio_irq; 1544 enum mctrl_gpio_idx i; 1545 int err = 0; 1546 1547 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) { 1548 if (irq[i] < 0) 1549 continue; 1550 1551 irq_set_status_flags(irq[i], IRQ_NOAUTOEN); 1552 err = request_irq(irq[i], mxs_auart_irq_handle, 1553 IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s); 1554 if (err) 1555 dev_err(s->dev, "%s - Can't get %d irq\n", 1556 __func__, irq[i]); 1557 } 1558 1559 /* 1560 * If something went wrong, rollback. 1561 * Be careful: i may be unsigned. 1562 */ 1563 while (err && (i-- > 0)) 1564 if (irq[i] >= 0) 1565 free_irq(irq[i], s); 1566 1567 return err; 1568} 1569 1570static int mxs_auart_probe(struct platform_device *pdev) 1571{ 1572 struct device_node *np = pdev->dev.of_node; 1573 struct mxs_auart_port *s; 1574 u32 version; 1575 int ret, irq; 1576 struct resource *r; 1577 1578 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL); 1579 if (!s) 1580 return -ENOMEM; 1581 1582 s->port.dev = &pdev->dev; 1583 s->dev = &pdev->dev; 1584 1585 ret = of_alias_get_id(np, "serial"); 1586 if (ret < 0) { 1587 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret); 1588 return ret; 1589 } 1590 s->port.line = ret; 1591 1592 if (of_property_read_bool(np, "uart-has-rtscts") || 1593 of_property_read_bool(np, "fsl,uart-has-rtscts") /* deprecated */) 1594 set_bit(MXS_AUART_RTSCTS, &s->flags); 1595 1596 if (s->port.line >= ARRAY_SIZE(auart_port)) { 1597 dev_err(&pdev->dev, "serial%d out of range\n", s->port.line); 1598 return -EINVAL; 1599 } 1600 1601 s->devtype = (enum mxs_auart_type)of_device_get_match_data(&pdev->dev); 1602 1603 ret = mxs_get_clks(s, pdev); 1604 if (ret) 1605 return ret; 1606 1607 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1608 if (!r) { 1609 ret = -ENXIO; 1610 goto out_disable_clks; 1611 } 1612 1613 s->port.mapbase = r->start; 1614 s->port.membase = ioremap(r->start, resource_size(r)); 1615 if (!s->port.membase) { 1616 ret = -ENOMEM; 1617 goto out_disable_clks; 1618 } 1619 s->port.ops = &mxs_auart_ops; 1620 s->port.iotype = UPIO_MEM; 1621 s->port.fifosize = MXS_AUART_FIFO_SIZE; 1622 s->port.uartclk = clk_get_rate(s->clk); 1623 s->port.type = PORT_IMX; 1624 s->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_MXS_AUART_CONSOLE); 1625 1626 mxs_init_regs(s); 1627 1628 s->mctrl_prev = 0; 1629 1630 irq = platform_get_irq(pdev, 0); 1631 if (irq < 0) { 1632 ret = irq; 1633 goto out_iounmap; 1634 } 1635 1636 s->port.irq = irq; 1637 ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0, 1638 dev_name(&pdev->dev), s); 1639 if (ret) 1640 goto out_iounmap; 1641 1642 platform_set_drvdata(pdev, s); 1643 1644 ret = mxs_auart_init_gpios(s, &pdev->dev); 1645 if (ret) { 1646 dev_err(&pdev->dev, "Failed to initialize GPIOs.\n"); 1647 goto out_iounmap; 1648 } 1649 1650 /* 1651 * Get the GPIO lines IRQ 1652 */ 1653 ret = mxs_auart_request_gpio_irq(s); 1654 if (ret) 1655 goto out_iounmap; 1656 1657 auart_port[s->port.line] = s; 1658 1659 mxs_auart_reset_deassert(s); 1660 1661 ret = uart_add_one_port(&auart_driver, &s->port); 1662 if (ret) 1663 goto out_free_qpio_irq; 1664 1665 /* ASM9260 don't have version reg */ 1666 if (is_asm9260_auart(s)) { 1667 dev_info(&pdev->dev, "Found APPUART ASM9260\n"); 1668 } else { 1669 version = mxs_read(s, REG_VERSION); 1670 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n", 1671 (version >> 24) & 0xff, 1672 (version >> 16) & 0xff, version & 0xffff); 1673 } 1674 1675 return 0; 1676 1677out_free_qpio_irq: 1678 mxs_auart_free_gpio_irq(s); 1679 auart_port[pdev->id] = NULL; 1680 1681out_iounmap: 1682 iounmap(s->port.membase); 1683 1684out_disable_clks: 1685 if (is_asm9260_auart(s)) { 1686 clk_disable_unprepare(s->clk); 1687 clk_disable_unprepare(s->clk_ahb); 1688 } 1689 return ret; 1690} 1691 1692static int mxs_auart_remove(struct platform_device *pdev) 1693{ 1694 struct mxs_auart_port *s = platform_get_drvdata(pdev); 1695 1696 uart_remove_one_port(&auart_driver, &s->port); 1697 auart_port[pdev->id] = NULL; 1698 mxs_auart_free_gpio_irq(s); 1699 iounmap(s->port.membase); 1700 if (is_asm9260_auart(s)) { 1701 clk_disable_unprepare(s->clk); 1702 clk_disable_unprepare(s->clk_ahb); 1703 } 1704 1705 return 0; 1706} 1707 1708static struct platform_driver mxs_auart_driver = { 1709 .probe = mxs_auart_probe, 1710 .remove = mxs_auart_remove, 1711 .driver = { 1712 .name = "mxs-auart", 1713 .of_match_table = mxs_auart_dt_ids, 1714 }, 1715}; 1716 1717static int __init mxs_auart_init(void) 1718{ 1719 int r; 1720 1721 r = uart_register_driver(&auart_driver); 1722 if (r) 1723 goto out; 1724 1725 r = platform_driver_register(&mxs_auart_driver); 1726 if (r) 1727 goto out_err; 1728 1729 return 0; 1730out_err: 1731 uart_unregister_driver(&auart_driver); 1732out: 1733 return r; 1734} 1735 1736static void __exit mxs_auart_exit(void) 1737{ 1738 platform_driver_unregister(&mxs_auart_driver); 1739 uart_unregister_driver(&auart_driver); 1740} 1741 1742module_init(mxs_auart_init); 1743module_exit(mxs_auart_exit); 1744MODULE_LICENSE("GPL"); 1745MODULE_DESCRIPTION("Freescale MXS application uart driver"); 1746MODULE_ALIAS("platform:mxs-auart"); 1747