1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver 4 * 5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru> 6 * 7 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org> 8 * Based on max3110.c, by Feng Tang <feng.tang@intel.com> 9 * Based on max3107.c, by Aavamobile 10 */ 11 12#include <linux/bitops.h> 13#include <linux/clk.h> 14#include <linux/delay.h> 15#include <linux/device.h> 16#include <linux/gpio/driver.h> 17#include <linux/i2c.h> 18#include <linux/module.h> 19#include <linux/mod_devicetable.h> 20#include <linux/property.h> 21#include <linux/regmap.h> 22#include <linux/serial_core.h> 23#include <linux/serial.h> 24#include <linux/tty.h> 25#include <linux/tty_flip.h> 26#include <linux/spi/spi.h> 27#include <linux/uaccess.h> 28 29#define MAX310X_NAME "max310x" 30#define MAX310X_MAJOR 204 31#define MAX310X_MINOR 209 32#define MAX310X_UART_NRMAX 16 33 34/* MAX310X register definitions */ 35#define MAX310X_RHR_REG (0x00) /* RX FIFO */ 36#define MAX310X_THR_REG (0x00) /* TX FIFO */ 37#define MAX310X_IRQEN_REG (0x01) /* IRQ enable */ 38#define MAX310X_IRQSTS_REG (0x02) /* IRQ status */ 39#define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ 40#define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ 41#define MAX310X_REG_05 (0x05) 42#define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */ 43#define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ 44#define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ 45#define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ 46#define MAX310X_MODE1_REG (0x09) /* MODE1 */ 47#define MAX310X_MODE2_REG (0x0a) /* MODE2 */ 48#define MAX310X_LCR_REG (0x0b) /* LCR */ 49#define MAX310X_RXTO_REG (0x0c) /* RX timeout */ 50#define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */ 51#define MAX310X_IRDA_REG (0x0e) /* IRDA settings */ 52#define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */ 53#define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */ 54#define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */ 55#define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */ 56#define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */ 57#define MAX310X_XON1_REG (0x14) /* XON1 character */ 58#define MAX310X_XON2_REG (0x15) /* XON2 character */ 59#define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */ 60#define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */ 61#define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */ 62#define MAX310X_GPIODATA_REG (0x19) /* GPIO data */ 63#define MAX310X_PLLCFG_REG (0x1a) /* PLL config */ 64#define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */ 65#define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ 66#define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ 67#define MAX310X_CLKSRC_REG (0x1e) /* Clock source */ 68#define MAX310X_REG_1F (0x1f) 69 70#define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */ 71 72#define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */ 73#define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */ 74 75/* Extended registers */ 76#define MAX310X_SPI_REVID_EXTREG MAX310X_REG_05 /* Revision ID */ 77#define MAX310X_I2C_REVID_EXTREG (0x25) /* Revision ID */ 78 79/* IRQ register bits */ 80#define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ 81#define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */ 82#define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */ 83#define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */ 84#define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */ 85#define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */ 86#define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */ 87#define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */ 88 89/* LSR register bits */ 90#define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */ 91#define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */ 92#define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */ 93#define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */ 94#define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */ 95#define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */ 96#define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */ 97 98/* Special character register bits */ 99#define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */ 100#define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */ 101#define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */ 102#define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */ 103#define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */ 104#define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */ 105 106/* Status register bits */ 107#define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */ 108#define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */ 109#define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */ 110#define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */ 111#define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */ 112#define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ 113 114/* MODE1 register bits */ 115#define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */ 116#define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */ 117#define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */ 118#define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */ 119#define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */ 120#define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ 121#define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ 122#define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */ 123 124/* MODE2 register bits */ 125#define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */ 126#define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */ 127#define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */ 128#define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */ 129#define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ 130#define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */ 131#define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */ 132#define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */ 133 134/* LCR register bits */ 135#define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 136#define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 137 * 138 * Word length bits table: 139 * 00 -> 5 bit words 140 * 01 -> 6 bit words 141 * 10 -> 7 bit words 142 * 11 -> 8 bit words 143 */ 144#define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 145 * 146 * STOP length bit table: 147 * 0 -> 1 stop bit 148 * 1 -> 1-1.5 stop bits if 149 * word length is 5, 150 * 2 stop bits otherwise 151 */ 152#define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 153#define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 154#define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 155#define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 156#define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */ 157 158/* IRDA register bits */ 159#define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */ 160#define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ 161 162/* Flow control trigger level register masks */ 163#define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */ 164#define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */ 165#define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f) 166#define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4) 167 168/* FIFO interrupt trigger level register masks */ 169#define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */ 170#define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */ 171#define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f) 172#define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4) 173 174/* Flow control register bits */ 175#define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */ 176#define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */ 177#define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs 178 * are used in conjunction with 179 * XOFF2 for definition of 180 * special character */ 181#define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */ 182#define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ 183#define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1 184 * 185 * SWFLOW bits 1 & 0 table: 186 * 00 -> no transmitter flow 187 * control 188 * 01 -> receiver compares 189 * XON2 and XOFF2 190 * and controls 191 * transmitter 192 * 10 -> receiver compares 193 * XON1 and XOFF1 194 * and controls 195 * transmitter 196 * 11 -> receiver compares 197 * XON1, XON2, XOFF1 and 198 * XOFF2 and controls 199 * transmitter 200 */ 201#define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ 202#define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3 203 * 204 * SWFLOW bits 3 & 2 table: 205 * 00 -> no received flow 206 * control 207 * 01 -> transmitter generates 208 * XON2 and XOFF2 209 * 10 -> transmitter generates 210 * XON1 and XOFF1 211 * 11 -> transmitter generates 212 * XON1, XON2, XOFF1 and 213 * XOFF2 214 */ 215 216/* PLL configuration register masks */ 217#define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */ 218#define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */ 219 220/* Baud rate generator configuration register bits */ 221#define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ 222#define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */ 223 224/* Clock source register bits */ 225#define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */ 226#define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */ 227#define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */ 228#define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ 229#define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ 230 231/* Global commands */ 232#define MAX310X_EXTREG_ENBL (0xce) 233#define MAX310X_EXTREG_DSBL (0xcd) 234 235/* Misc definitions */ 236#define MAX310X_FIFO_SIZE (128) 237#define MAX310x_REV_MASK (0xf8) 238#define MAX310X_WRITE_BIT 0x80 239 240/* Port startup definitions */ 241#define MAX310X_PORT_STARTUP_WAIT_RETRIES 20 /* Number of retries */ 242#define MAX310X_PORT_STARTUP_WAIT_DELAY_MS 10 /* Delay between retries */ 243 244/* Crystal-related definitions */ 245#define MAX310X_XTAL_WAIT_RETRIES 20 /* Number of retries */ 246#define MAX310X_XTAL_WAIT_DELAY_MS 10 /* Delay between retries */ 247 248/* MAX3107 specific */ 249#define MAX3107_REV_ID (0xa0) 250 251/* MAX3109 specific */ 252#define MAX3109_REV_ID (0xc0) 253 254/* MAX14830 specific */ 255#define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */ 256#define MAX14830_REV_ID (0xb0) 257 258struct max310x_if_cfg { 259 int (*extended_reg_enable)(struct device *dev, bool enable); 260 261 unsigned int rev_id_reg; 262}; 263 264struct max310x_devtype { 265 struct { 266 unsigned short min; 267 unsigned short max; 268 } slave_addr; 269 char name[9]; 270 int nr; 271 u8 mode1; 272 int (*detect)(struct device *); 273 void (*power)(struct uart_port *, int); 274}; 275 276struct max310x_one { 277 struct uart_port port; 278 struct work_struct tx_work; 279 struct work_struct md_work; 280 struct work_struct rs_work; 281 struct regmap *regmap; 282 283 u8 rx_buf[MAX310X_FIFO_SIZE]; 284}; 285#define to_max310x_port(_port) \ 286 container_of(_port, struct max310x_one, port) 287 288struct max310x_port { 289 const struct max310x_devtype *devtype; 290 const struct max310x_if_cfg *if_cfg; 291 struct regmap *regmap; 292 struct clk *clk; 293#ifdef CONFIG_GPIOLIB 294 struct gpio_chip gpio; 295#endif 296 struct max310x_one p[]; 297}; 298 299static struct uart_driver max310x_uart = { 300 .owner = THIS_MODULE, 301 .driver_name = MAX310X_NAME, 302 .dev_name = "ttyMAX", 303 .major = MAX310X_MAJOR, 304 .minor = MAX310X_MINOR, 305 .nr = MAX310X_UART_NRMAX, 306}; 307 308static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX); 309 310static u8 max310x_port_read(struct uart_port *port, u8 reg) 311{ 312 struct max310x_one *one = to_max310x_port(port); 313 unsigned int val = 0; 314 315 regmap_read(one->regmap, reg, &val); 316 317 return val; 318} 319 320static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) 321{ 322 struct max310x_one *one = to_max310x_port(port); 323 324 regmap_write(one->regmap, reg, val); 325} 326 327static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) 328{ 329 struct max310x_one *one = to_max310x_port(port); 330 331 regmap_update_bits(one->regmap, reg, mask, val); 332} 333 334static int max3107_detect(struct device *dev) 335{ 336 struct max310x_port *s = dev_get_drvdata(dev); 337 unsigned int val = 0; 338 int ret; 339 340 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); 341 if (ret) 342 return ret; 343 344 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) { 345 dev_err(dev, 346 "%s ID 0x%02x does not match\n", s->devtype->name, val); 347 return -ENODEV; 348 } 349 350 return 0; 351} 352 353static int max3108_detect(struct device *dev) 354{ 355 struct max310x_port *s = dev_get_drvdata(dev); 356 unsigned int val = 0; 357 int ret; 358 359 /* MAX3108 have not REV ID register, we just check default value 360 * from clocksource register to make sure everything works. 361 */ 362 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); 363 if (ret) 364 return ret; 365 366 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) { 367 dev_err(dev, "%s not present\n", s->devtype->name); 368 return -ENODEV; 369 } 370 371 return 0; 372} 373 374static int max3109_detect(struct device *dev) 375{ 376 struct max310x_port *s = dev_get_drvdata(dev); 377 unsigned int val = 0; 378 int ret; 379 380 ret = s->if_cfg->extended_reg_enable(dev, true); 381 if (ret) 382 return ret; 383 384 regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val); 385 s->if_cfg->extended_reg_enable(dev, false); 386 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) { 387 dev_err(dev, 388 "%s ID 0x%02x does not match\n", s->devtype->name, val); 389 return -ENODEV; 390 } 391 392 return 0; 393} 394 395static void max310x_power(struct uart_port *port, int on) 396{ 397 max310x_port_update(port, MAX310X_MODE1_REG, 398 MAX310X_MODE1_FORCESLEEP_BIT, 399 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT); 400 if (on) 401 msleep(50); 402} 403 404static int max14830_detect(struct device *dev) 405{ 406 struct max310x_port *s = dev_get_drvdata(dev); 407 unsigned int val = 0; 408 int ret; 409 410 ret = s->if_cfg->extended_reg_enable(dev, true); 411 if (ret) 412 return ret; 413 414 regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val); 415 s->if_cfg->extended_reg_enable(dev, false); 416 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) { 417 dev_err(dev, 418 "%s ID 0x%02x does not match\n", s->devtype->name, val); 419 return -ENODEV; 420 } 421 422 return 0; 423} 424 425static void max14830_power(struct uart_port *port, int on) 426{ 427 max310x_port_update(port, MAX310X_BRGCFG_REG, 428 MAX14830_BRGCFG_CLKDIS_BIT, 429 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT); 430 if (on) 431 msleep(50); 432} 433 434static const struct max310x_devtype max3107_devtype = { 435 .name = "MAX3107", 436 .nr = 1, 437 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT | MAX310X_MODE1_IRQSEL_BIT, 438 .detect = max3107_detect, 439 .power = max310x_power, 440 .slave_addr = { 441 .min = 0x2c, 442 .max = 0x2f, 443 }, 444}; 445 446static const struct max310x_devtype max3108_devtype = { 447 .name = "MAX3108", 448 .nr = 1, 449 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 450 .detect = max3108_detect, 451 .power = max310x_power, 452 .slave_addr = { 453 .min = 0x60, 454 .max = 0x6f, 455 }, 456}; 457 458static const struct max310x_devtype max3109_devtype = { 459 .name = "MAX3109", 460 .nr = 2, 461 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 462 .detect = max3109_detect, 463 .power = max310x_power, 464 .slave_addr = { 465 .min = 0x60, 466 .max = 0x6f, 467 }, 468}; 469 470static const struct max310x_devtype max14830_devtype = { 471 .name = "MAX14830", 472 .nr = 4, 473 .mode1 = MAX310X_MODE1_IRQSEL_BIT, 474 .detect = max14830_detect, 475 .power = max14830_power, 476 .slave_addr = { 477 .min = 0x60, 478 .max = 0x6f, 479 }, 480}; 481 482static bool max310x_reg_writeable(struct device *dev, unsigned int reg) 483{ 484 switch (reg) { 485 case MAX310X_IRQSTS_REG: 486 case MAX310X_LSR_IRQSTS_REG: 487 case MAX310X_SPCHR_IRQSTS_REG: 488 case MAX310X_STS_IRQSTS_REG: 489 case MAX310X_TXFIFOLVL_REG: 490 case MAX310X_RXFIFOLVL_REG: 491 return false; 492 default: 493 break; 494 } 495 496 return true; 497} 498 499static bool max310x_reg_volatile(struct device *dev, unsigned int reg) 500{ 501 switch (reg) { 502 case MAX310X_RHR_REG: 503 case MAX310X_IRQSTS_REG: 504 case MAX310X_LSR_IRQSTS_REG: 505 case MAX310X_SPCHR_IRQSTS_REG: 506 case MAX310X_STS_IRQSTS_REG: 507 case MAX310X_TXFIFOLVL_REG: 508 case MAX310X_RXFIFOLVL_REG: 509 case MAX310X_GPIODATA_REG: 510 case MAX310X_BRGDIVLSB_REG: 511 case MAX310X_REG_05: 512 case MAX310X_REG_1F: 513 return true; 514 default: 515 break; 516 } 517 518 return false; 519} 520 521static bool max310x_reg_precious(struct device *dev, unsigned int reg) 522{ 523 switch (reg) { 524 case MAX310X_RHR_REG: 525 case MAX310X_IRQSTS_REG: 526 case MAX310X_SPCHR_IRQSTS_REG: 527 case MAX310X_STS_IRQSTS_REG: 528 return true; 529 default: 530 break; 531 } 532 533 return false; 534} 535 536static bool max310x_reg_noinc(struct device *dev, unsigned int reg) 537{ 538 return reg == MAX310X_RHR_REG; 539} 540 541static int max310x_set_baud(struct uart_port *port, int baud) 542{ 543 unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0; 544 545 /* 546 * Calculate the integer divisor first. Select a proper mode 547 * in case if the requested baud is too high for the pre-defined 548 * clocks frequency. 549 */ 550 div = port->uartclk / baud; 551 if (div < 8) { 552 /* Mode x4 */ 553 c = 4; 554 mode = MAX310X_BRGCFG_4XMODE_BIT; 555 } else if (div < 16) { 556 /* Mode x2 */ 557 c = 8; 558 mode = MAX310X_BRGCFG_2XMODE_BIT; 559 } else { 560 c = 16; 561 } 562 563 /* Calculate the divisor in accordance with the fraction coefficient */ 564 div /= c; 565 F = c*baud; 566 567 /* Calculate the baud rate fraction */ 568 if (div > 0) 569 frac = (16*(port->uartclk % F)) / F; 570 else 571 div = 1; 572 573 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8); 574 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div); 575 max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode); 576 577 /* Return the actual baud rate we just programmed */ 578 return (16*port->uartclk) / (c*(16*div + frac)); 579} 580 581static int max310x_update_best_err(unsigned long f, long *besterr) 582{ 583 /* Use baudrate 115200 for calculate error */ 584 long err = f % (460800 * 16); 585 586 if ((*besterr < 0) || (*besterr > err)) { 587 *besterr = err; 588 return 0; 589 } 590 591 return 1; 592} 593 594static s32 max310x_set_ref_clk(struct device *dev, struct max310x_port *s, 595 unsigned long freq, bool xtal) 596{ 597 unsigned int div, clksrc, pllcfg = 0; 598 long besterr = -1; 599 unsigned long fdiv, fmul, bestfreq = freq; 600 601 /* First, update error without PLL */ 602 max310x_update_best_err(freq, &besterr); 603 604 /* Try all possible PLL dividers */ 605 for (div = 1; (div <= 63) && besterr; div++) { 606 fdiv = DIV_ROUND_CLOSEST(freq, div); 607 608 /* Try multiplier 6 */ 609 fmul = fdiv * 6; 610 if ((fdiv >= 500000) && (fdiv <= 800000)) 611 if (!max310x_update_best_err(fmul, &besterr)) { 612 pllcfg = (0 << 6) | div; 613 bestfreq = fmul; 614 } 615 /* Try multiplier 48 */ 616 fmul = fdiv * 48; 617 if ((fdiv >= 850000) && (fdiv <= 1200000)) 618 if (!max310x_update_best_err(fmul, &besterr)) { 619 pllcfg = (1 << 6) | div; 620 bestfreq = fmul; 621 } 622 /* Try multiplier 96 */ 623 fmul = fdiv * 96; 624 if ((fdiv >= 425000) && (fdiv <= 1000000)) 625 if (!max310x_update_best_err(fmul, &besterr)) { 626 pllcfg = (2 << 6) | div; 627 bestfreq = fmul; 628 } 629 /* Try multiplier 144 */ 630 fmul = fdiv * 144; 631 if ((fdiv >= 390000) && (fdiv <= 667000)) 632 if (!max310x_update_best_err(fmul, &besterr)) { 633 pllcfg = (3 << 6) | div; 634 bestfreq = fmul; 635 } 636 } 637 638 /* Configure clock source */ 639 clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0); 640 641 /* Configure PLL */ 642 if (pllcfg) { 643 clksrc |= MAX310X_CLKSRC_PLL_BIT; 644 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); 645 } else 646 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT; 647 648 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); 649 650 /* Wait for crystal */ 651 if (xtal) { 652 bool stable = false; 653 unsigned int try = 0, val = 0; 654 655 do { 656 msleep(MAX310X_XTAL_WAIT_DELAY_MS); 657 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val); 658 659 if (val & MAX310X_STS_CLKREADY_BIT) 660 stable = true; 661 } while (!stable && (++try < MAX310X_XTAL_WAIT_RETRIES)); 662 663 if (!stable) 664 return dev_err_probe(dev, -EAGAIN, 665 "clock is not stable\n"); 666 } 667 668 return bestfreq; 669} 670 671static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len) 672{ 673 struct max310x_one *one = to_max310x_port(port); 674 675 regmap_noinc_write(one->regmap, MAX310X_THR_REG, txbuf, len); 676} 677 678static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len) 679{ 680 struct max310x_one *one = to_max310x_port(port); 681 682 regmap_noinc_read(one->regmap, MAX310X_RHR_REG, rxbuf, len); 683} 684 685static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) 686{ 687 struct max310x_one *one = to_max310x_port(port); 688 unsigned int sts, i; 689 u8 ch, flag; 690 691 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) { 692 /* We are just reading, happily ignoring any error conditions. 693 * Break condition, parity checking, framing errors -- they 694 * are all ignored. That means that we can do a batch-read. 695 * 696 * There is a small opportunity for race if the RX FIFO 697 * overruns while we're reading the buffer; the datasheets says 698 * that the LSR register applies to the "current" character. 699 * That's also the reason why we cannot do batched reads when 700 * asked to check the individual statuses. 701 * */ 702 703 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 704 max310x_batch_read(port, one->rx_buf, rxlen); 705 706 port->icount.rx += rxlen; 707 flag = TTY_NORMAL; 708 sts &= port->read_status_mask; 709 710 if (sts & MAX310X_LSR_RXOVR_BIT) { 711 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n"); 712 port->icount.overrun++; 713 } 714 715 for (i = 0; i < (rxlen - 1); ++i) 716 uart_insert_char(port, sts, 0, one->rx_buf[i], flag); 717 718 /* 719 * Handle the overrun case for the last character only, since 720 * the RxFIFO overflow happens after it is pushed to the FIFO 721 * tail. 722 */ 723 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, 724 one->rx_buf[rxlen-1], flag); 725 726 } else { 727 if (unlikely(rxlen >= port->fifosize)) { 728 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n"); 729 port->icount.buf_overrun++; 730 /* Ensure sanity of RX level */ 731 rxlen = port->fifosize; 732 } 733 734 while (rxlen--) { 735 ch = max310x_port_read(port, MAX310X_RHR_REG); 736 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 737 738 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT | 739 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT; 740 741 port->icount.rx++; 742 flag = TTY_NORMAL; 743 744 if (unlikely(sts)) { 745 if (sts & MAX310X_LSR_RXBRK_BIT) { 746 port->icount.brk++; 747 if (uart_handle_break(port)) 748 continue; 749 } else if (sts & MAX310X_LSR_RXPAR_BIT) 750 port->icount.parity++; 751 else if (sts & MAX310X_LSR_FRERR_BIT) 752 port->icount.frame++; 753 else if (sts & MAX310X_LSR_RXOVR_BIT) 754 port->icount.overrun++; 755 756 sts &= port->read_status_mask; 757 if (sts & MAX310X_LSR_RXBRK_BIT) 758 flag = TTY_BREAK; 759 else if (sts & MAX310X_LSR_RXPAR_BIT) 760 flag = TTY_PARITY; 761 else if (sts & MAX310X_LSR_FRERR_BIT) 762 flag = TTY_FRAME; 763 else if (sts & MAX310X_LSR_RXOVR_BIT) 764 flag = TTY_OVERRUN; 765 } 766 767 if (uart_handle_sysrq_char(port, ch)) 768 continue; 769 770 if (sts & port->ignore_status_mask) 771 continue; 772 773 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag); 774 } 775 } 776 777 tty_flip_buffer_push(&port->state->port); 778} 779 780static void max310x_handle_tx(struct uart_port *port) 781{ 782 struct circ_buf *xmit = &port->state->xmit; 783 unsigned int txlen, to_send, until_end; 784 785 if (unlikely(port->x_char)) { 786 max310x_port_write(port, MAX310X_THR_REG, port->x_char); 787 port->icount.tx++; 788 port->x_char = 0; 789 return; 790 } 791 792 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 793 return; 794 795 /* Get length of data pending in circular buffer */ 796 to_send = uart_circ_chars_pending(xmit); 797 until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 798 if (likely(to_send)) { 799 /* Limit to size of TX FIFO */ 800 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 801 txlen = port->fifosize - txlen; 802 to_send = (to_send > txlen) ? txlen : to_send; 803 804 if (until_end < to_send) { 805 /* It's a circ buffer -- wrap around. 806 * We could do that in one SPI transaction, but meh. */ 807 max310x_batch_write(port, xmit->buf + xmit->tail, until_end); 808 max310x_batch_write(port, xmit->buf, to_send - until_end); 809 } else { 810 max310x_batch_write(port, xmit->buf + xmit->tail, to_send); 811 } 812 uart_xmit_advance(port, to_send); 813 } 814 815 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 816 uart_write_wakeup(port); 817} 818 819static void max310x_start_tx(struct uart_port *port) 820{ 821 struct max310x_one *one = to_max310x_port(port); 822 823 schedule_work(&one->tx_work); 824} 825 826static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno) 827{ 828 struct uart_port *port = &s->p[portno].port; 829 irqreturn_t res = IRQ_NONE; 830 831 do { 832 unsigned int ists, lsr, rxlen; 833 834 /* Read IRQ status & RX FIFO level */ 835 ists = max310x_port_read(port, MAX310X_IRQSTS_REG); 836 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG); 837 if (!ists && !rxlen) 838 break; 839 840 res = IRQ_HANDLED; 841 842 if (ists & MAX310X_IRQ_CTS_BIT) { 843 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 844 uart_handle_cts_change(port, lsr & MAX310X_LSR_CTS_BIT); 845 } 846 if (rxlen) 847 max310x_handle_rx(port, rxlen); 848 if (ists & MAX310X_IRQ_TXEMPTY_BIT) 849 max310x_start_tx(port); 850 } while (1); 851 return res; 852} 853 854static irqreturn_t max310x_ist(int irq, void *dev_id) 855{ 856 struct max310x_port *s = (struct max310x_port *)dev_id; 857 bool handled = false; 858 859 if (s->devtype->nr > 1) { 860 do { 861 unsigned int val = ~0; 862 863 WARN_ON_ONCE(regmap_read(s->regmap, 864 MAX310X_GLOBALIRQ_REG, &val)); 865 val = ((1 << s->devtype->nr) - 1) & ~val; 866 if (!val) 867 break; 868 if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED) 869 handled = true; 870 } while (1); 871 } else { 872 if (max310x_port_irq(s, 0) == IRQ_HANDLED) 873 handled = true; 874 } 875 876 return IRQ_RETVAL(handled); 877} 878 879static void max310x_tx_proc(struct work_struct *ws) 880{ 881 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work); 882 883 max310x_handle_tx(&one->port); 884} 885 886static unsigned int max310x_tx_empty(struct uart_port *port) 887{ 888 u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 889 890 return lvl ? 0 : TIOCSER_TEMT; 891} 892 893static unsigned int max310x_get_mctrl(struct uart_port *port) 894{ 895 /* DCD and DSR are not wired and CTS/RTS is handled automatically 896 * so just indicate DSR and CAR asserted 897 */ 898 return TIOCM_DSR | TIOCM_CAR; 899} 900 901static void max310x_md_proc(struct work_struct *ws) 902{ 903 struct max310x_one *one = container_of(ws, struct max310x_one, md_work); 904 905 max310x_port_update(&one->port, MAX310X_MODE2_REG, 906 MAX310X_MODE2_LOOPBACK_BIT, 907 (one->port.mctrl & TIOCM_LOOP) ? 908 MAX310X_MODE2_LOOPBACK_BIT : 0); 909} 910 911static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) 912{ 913 struct max310x_one *one = to_max310x_port(port); 914 915 schedule_work(&one->md_work); 916} 917 918static void max310x_break_ctl(struct uart_port *port, int break_state) 919{ 920 max310x_port_update(port, MAX310X_LCR_REG, 921 MAX310X_LCR_TXBREAK_BIT, 922 break_state ? MAX310X_LCR_TXBREAK_BIT : 0); 923} 924 925static void max310x_set_termios(struct uart_port *port, 926 struct ktermios *termios, 927 const struct ktermios *old) 928{ 929 unsigned int lcr = 0, flow = 0; 930 int baud; 931 932 /* Mask termios capabilities we don't support */ 933 termios->c_cflag &= ~CMSPAR; 934 935 /* Word size */ 936 switch (termios->c_cflag & CSIZE) { 937 case CS5: 938 break; 939 case CS6: 940 lcr = MAX310X_LCR_LENGTH0_BIT; 941 break; 942 case CS7: 943 lcr = MAX310X_LCR_LENGTH1_BIT; 944 break; 945 case CS8: 946 default: 947 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT; 948 break; 949 } 950 951 /* Parity */ 952 if (termios->c_cflag & PARENB) { 953 lcr |= MAX310X_LCR_PARITY_BIT; 954 if (!(termios->c_cflag & PARODD)) 955 lcr |= MAX310X_LCR_EVENPARITY_BIT; 956 } 957 958 /* Stop bits */ 959 if (termios->c_cflag & CSTOPB) 960 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */ 961 962 /* Update LCR register */ 963 max310x_port_write(port, MAX310X_LCR_REG, lcr); 964 965 /* Set read status mask */ 966 port->read_status_mask = MAX310X_LSR_RXOVR_BIT; 967 if (termios->c_iflag & INPCK) 968 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | 969 MAX310X_LSR_FRERR_BIT; 970 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 971 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; 972 973 /* Set status ignore mask */ 974 port->ignore_status_mask = 0; 975 if (termios->c_iflag & IGNBRK) 976 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; 977 if (!(termios->c_cflag & CREAD)) 978 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | 979 MAX310X_LSR_RXOVR_BIT | 980 MAX310X_LSR_FRERR_BIT | 981 MAX310X_LSR_RXBRK_BIT; 982 983 /* Configure flow control */ 984 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); 985 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); 986 987 /* Disable transmitter before enabling AutoCTS or auto transmitter 988 * flow control 989 */ 990 if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) { 991 max310x_port_update(port, MAX310X_MODE1_REG, 992 MAX310X_MODE1_TXDIS_BIT, 993 MAX310X_MODE1_TXDIS_BIT); 994 } 995 996 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 997 998 if (termios->c_cflag & CRTSCTS) { 999 /* Enable AUTORTS and AUTOCTS */ 1000 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1001 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT | 1002 MAX310X_FLOWCTRL_AUTORTS_BIT; 1003 } 1004 if (termios->c_iflag & IXON) 1005 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT | 1006 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 1007 if (termios->c_iflag & IXOFF) { 1008 port->status |= UPSTAT_AUTOXOFF; 1009 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT | 1010 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 1011 } 1012 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); 1013 1014 /* Enable transmitter after disabling AutoCTS and auto transmitter 1015 * flow control 1016 */ 1017 if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) { 1018 max310x_port_update(port, MAX310X_MODE1_REG, 1019 MAX310X_MODE1_TXDIS_BIT, 1020 0); 1021 } 1022 1023 /* Get baud rate generator configuration */ 1024 baud = uart_get_baud_rate(port, termios, old, 1025 port->uartclk / 16 / 0xffff, 1026 port->uartclk / 4); 1027 1028 /* Setup baudrate generator */ 1029 baud = max310x_set_baud(port, baud); 1030 1031 /* Update timeout according to new baud rate */ 1032 uart_update_timeout(port, termios->c_cflag, baud); 1033} 1034 1035static void max310x_rs_proc(struct work_struct *ws) 1036{ 1037 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work); 1038 unsigned int delay, mode1 = 0, mode2 = 0; 1039 1040 delay = (one->port.rs485.delay_rts_before_send << 4) | 1041 one->port.rs485.delay_rts_after_send; 1042 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay); 1043 1044 if (one->port.rs485.flags & SER_RS485_ENABLED) { 1045 mode1 = MAX310X_MODE1_TRNSCVCTRL_BIT; 1046 1047 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX)) 1048 mode2 = MAX310X_MODE2_ECHOSUPR_BIT; 1049 } 1050 1051 max310x_port_update(&one->port, MAX310X_MODE1_REG, 1052 MAX310X_MODE1_TRNSCVCTRL_BIT, mode1); 1053 max310x_port_update(&one->port, MAX310X_MODE2_REG, 1054 MAX310X_MODE2_ECHOSUPR_BIT, mode2); 1055} 1056 1057static int max310x_rs485_config(struct uart_port *port, struct ktermios *termios, 1058 struct serial_rs485 *rs485) 1059{ 1060 struct max310x_one *one = to_max310x_port(port); 1061 1062 if ((rs485->delay_rts_before_send > 0x0f) || 1063 (rs485->delay_rts_after_send > 0x0f)) 1064 return -ERANGE; 1065 1066 port->rs485 = *rs485; 1067 1068 schedule_work(&one->rs_work); 1069 1070 return 0; 1071} 1072 1073static int max310x_startup(struct uart_port *port) 1074{ 1075 struct max310x_port *s = dev_get_drvdata(port->dev); 1076 unsigned int val; 1077 1078 s->devtype->power(port, 1); 1079 1080 /* Configure MODE1 register */ 1081 max310x_port_update(port, MAX310X_MODE1_REG, 1082 MAX310X_MODE1_TRNSCVCTRL_BIT, 0); 1083 1084 /* Configure MODE2 register & Reset FIFOs*/ 1085 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT; 1086 max310x_port_write(port, MAX310X_MODE2_REG, val); 1087 max310x_port_update(port, MAX310X_MODE2_REG, 1088 MAX310X_MODE2_FIFORST_BIT, 0); 1089 1090 /* Configure mode1/mode2 to have rs485/rs232 enabled at startup */ 1091 val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) | 1092 clamp(port->rs485.delay_rts_after_send, 0U, 15U); 1093 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val); 1094 1095 if (port->rs485.flags & SER_RS485_ENABLED) { 1096 max310x_port_update(port, MAX310X_MODE1_REG, 1097 MAX310X_MODE1_TRNSCVCTRL_BIT, 1098 MAX310X_MODE1_TRNSCVCTRL_BIT); 1099 1100 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 1101 max310x_port_update(port, MAX310X_MODE2_REG, 1102 MAX310X_MODE2_ECHOSUPR_BIT, 1103 MAX310X_MODE2_ECHOSUPR_BIT); 1104 } 1105 1106 /* Configure flow control levels */ 1107 /* Flow control halt level 96, resume level 48 */ 1108 max310x_port_write(port, MAX310X_FLOWLVL_REG, 1109 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96)); 1110 1111 /* Clear IRQ status register */ 1112 max310x_port_read(port, MAX310X_IRQSTS_REG); 1113 1114 /* Enable RX, TX, CTS change interrupts */ 1115 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT; 1116 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); 1117 1118 return 0; 1119} 1120 1121static void max310x_shutdown(struct uart_port *port) 1122{ 1123 struct max310x_port *s = dev_get_drvdata(port->dev); 1124 1125 /* Disable all interrupts */ 1126 max310x_port_write(port, MAX310X_IRQEN_REG, 0); 1127 1128 s->devtype->power(port, 0); 1129} 1130 1131static const char *max310x_type(struct uart_port *port) 1132{ 1133 struct max310x_port *s = dev_get_drvdata(port->dev); 1134 1135 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; 1136} 1137 1138static int max310x_request_port(struct uart_port *port) 1139{ 1140 /* Do nothing */ 1141 return 0; 1142} 1143 1144static void max310x_config_port(struct uart_port *port, int flags) 1145{ 1146 if (flags & UART_CONFIG_TYPE) 1147 port->type = PORT_MAX310X; 1148} 1149 1150static int max310x_verify_port(struct uart_port *port, struct serial_struct *s) 1151{ 1152 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) 1153 return -EINVAL; 1154 if (s->irq != port->irq) 1155 return -EINVAL; 1156 1157 return 0; 1158} 1159 1160static void max310x_null_void(struct uart_port *port) 1161{ 1162 /* Do nothing */ 1163} 1164 1165static const struct uart_ops max310x_ops = { 1166 .tx_empty = max310x_tx_empty, 1167 .set_mctrl = max310x_set_mctrl, 1168 .get_mctrl = max310x_get_mctrl, 1169 .stop_tx = max310x_null_void, 1170 .start_tx = max310x_start_tx, 1171 .stop_rx = max310x_null_void, 1172 .break_ctl = max310x_break_ctl, 1173 .startup = max310x_startup, 1174 .shutdown = max310x_shutdown, 1175 .set_termios = max310x_set_termios, 1176 .type = max310x_type, 1177 .request_port = max310x_request_port, 1178 .release_port = max310x_null_void, 1179 .config_port = max310x_config_port, 1180 .verify_port = max310x_verify_port, 1181}; 1182 1183static int __maybe_unused max310x_suspend(struct device *dev) 1184{ 1185 struct max310x_port *s = dev_get_drvdata(dev); 1186 int i; 1187 1188 for (i = 0; i < s->devtype->nr; i++) { 1189 uart_suspend_port(&max310x_uart, &s->p[i].port); 1190 s->devtype->power(&s->p[i].port, 0); 1191 } 1192 1193 return 0; 1194} 1195 1196static int __maybe_unused max310x_resume(struct device *dev) 1197{ 1198 struct max310x_port *s = dev_get_drvdata(dev); 1199 int i; 1200 1201 for (i = 0; i < s->devtype->nr; i++) { 1202 s->devtype->power(&s->p[i].port, 1); 1203 uart_resume_port(&max310x_uart, &s->p[i].port); 1204 } 1205 1206 return 0; 1207} 1208 1209static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume); 1210 1211#ifdef CONFIG_GPIOLIB 1212static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset) 1213{ 1214 unsigned int val; 1215 struct max310x_port *s = gpiochip_get_data(chip); 1216 struct uart_port *port = &s->p[offset / 4].port; 1217 1218 val = max310x_port_read(port, MAX310X_GPIODATA_REG); 1219 1220 return !!((val >> 4) & (1 << (offset % 4))); 1221} 1222 1223static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1224{ 1225 struct max310x_port *s = gpiochip_get_data(chip); 1226 struct uart_port *port = &s->p[offset / 4].port; 1227 1228 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1229 value ? 1 << (offset % 4) : 0); 1230} 1231 1232static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1233{ 1234 struct max310x_port *s = gpiochip_get_data(chip); 1235 struct uart_port *port = &s->p[offset / 4].port; 1236 1237 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0); 1238 1239 return 0; 1240} 1241 1242static int max310x_gpio_direction_output(struct gpio_chip *chip, 1243 unsigned offset, int value) 1244{ 1245 struct max310x_port *s = gpiochip_get_data(chip); 1246 struct uart_port *port = &s->p[offset / 4].port; 1247 1248 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1249 value ? 1 << (offset % 4) : 0); 1250 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 1251 1 << (offset % 4)); 1252 1253 return 0; 1254} 1255 1256static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 1257 unsigned long config) 1258{ 1259 struct max310x_port *s = gpiochip_get_data(chip); 1260 struct uart_port *port = &s->p[offset / 4].port; 1261 1262 switch (pinconf_to_config_param(config)) { 1263 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1264 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1265 1 << ((offset % 4) + 4), 1266 1 << ((offset % 4) + 4)); 1267 return 0; 1268 case PIN_CONFIG_DRIVE_PUSH_PULL: 1269 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1270 1 << ((offset % 4) + 4), 0); 1271 return 0; 1272 default: 1273 return -ENOTSUPP; 1274 } 1275} 1276#endif 1277 1278static const struct serial_rs485 max310x_rs485_supported = { 1279 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX, 1280 .delay_rts_before_send = 1, 1281 .delay_rts_after_send = 1, 1282}; 1283 1284static int max310x_probe(struct device *dev, const struct max310x_devtype *devtype, 1285 const struct max310x_if_cfg *if_cfg, 1286 struct regmap *regmaps[], int irq) 1287{ 1288 int i, ret, fmin, fmax, freq; 1289 struct max310x_port *s; 1290 s32 uartclk = 0; 1291 bool xtal; 1292 1293 for (i = 0; i < devtype->nr; i++) 1294 if (IS_ERR(regmaps[i])) 1295 return PTR_ERR(regmaps[i]); 1296 1297 /* Alloc port structure */ 1298 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL); 1299 if (!s) { 1300 dev_err(dev, "Error allocating port structure\n"); 1301 return -ENOMEM; 1302 } 1303 1304 /* Always ask for fixed clock rate from a property. */ 1305 device_property_read_u32(dev, "clock-frequency", &uartclk); 1306 1307 xtal = device_property_match_string(dev, "clock-names", "osc") < 0; 1308 if (xtal) 1309 s->clk = devm_clk_get_optional(dev, "xtal"); 1310 else 1311 s->clk = devm_clk_get_optional(dev, "osc"); 1312 if (IS_ERR(s->clk)) 1313 return PTR_ERR(s->clk); 1314 1315 ret = clk_prepare_enable(s->clk); 1316 if (ret) 1317 return ret; 1318 1319 freq = clk_get_rate(s->clk); 1320 if (freq == 0) 1321 freq = uartclk; 1322 if (freq == 0) { 1323 dev_err(dev, "Cannot get clock rate\n"); 1324 ret = -EINVAL; 1325 goto out_clk; 1326 } 1327 1328 if (xtal) { 1329 fmin = 1000000; 1330 fmax = 4000000; 1331 } else { 1332 fmin = 500000; 1333 fmax = 35000000; 1334 } 1335 1336 /* Check frequency limits */ 1337 if (freq < fmin || freq > fmax) { 1338 ret = -ERANGE; 1339 goto out_clk; 1340 } 1341 1342 s->regmap = regmaps[0]; 1343 s->devtype = devtype; 1344 s->if_cfg = if_cfg; 1345 dev_set_drvdata(dev, s); 1346 1347 /* Check device to ensure we are talking to what we expect */ 1348 ret = devtype->detect(dev); 1349 if (ret) 1350 goto out_clk; 1351 1352 for (i = 0; i < devtype->nr; i++) { 1353 bool started = false; 1354 unsigned int try = 0, val = 0; 1355 1356 /* Reset port */ 1357 regmap_write(regmaps[i], MAX310X_MODE2_REG, 1358 MAX310X_MODE2_RST_BIT); 1359 /* Clear port reset */ 1360 regmap_write(regmaps[i], MAX310X_MODE2_REG, 0); 1361 1362 /* Wait for port startup */ 1363 do { 1364 msleep(MAX310X_PORT_STARTUP_WAIT_DELAY_MS); 1365 regmap_read(regmaps[i], MAX310X_BRGDIVLSB_REG, &val); 1366 1367 if (val == 0x01) 1368 started = true; 1369 } while (!started && (++try < MAX310X_PORT_STARTUP_WAIT_RETRIES)); 1370 1371 if (!started) { 1372 ret = dev_err_probe(dev, -EAGAIN, "port reset failed\n"); 1373 goto out_uart; 1374 } 1375 1376 regmap_write(regmaps[i], MAX310X_MODE1_REG, devtype->mode1); 1377 } 1378 1379 uartclk = max310x_set_ref_clk(dev, s, freq, xtal); 1380 if (uartclk < 0) { 1381 ret = uartclk; 1382 goto out_uart; 1383 } 1384 1385 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); 1386 1387 for (i = 0; i < devtype->nr; i++) { 1388 unsigned int line; 1389 1390 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX); 1391 if (line == MAX310X_UART_NRMAX) { 1392 ret = -ERANGE; 1393 goto out_uart; 1394 } 1395 1396 /* Initialize port data */ 1397 s->p[i].port.line = line; 1398 s->p[i].port.dev = dev; 1399 s->p[i].port.irq = irq; 1400 s->p[i].port.type = PORT_MAX310X; 1401 s->p[i].port.fifosize = MAX310X_FIFO_SIZE; 1402 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1403 s->p[i].port.iotype = UPIO_PORT; 1404 s->p[i].port.iobase = i; 1405 /* 1406 * Use all ones as membase to make sure uart_configure_port() in 1407 * serial_core.c does not abort for SPI/I2C devices where the 1408 * membase address is not applicable. 1409 */ 1410 s->p[i].port.membase = (void __iomem *)~0; 1411 s->p[i].port.uartclk = uartclk; 1412 s->p[i].port.rs485_config = max310x_rs485_config; 1413 s->p[i].port.rs485_supported = max310x_rs485_supported; 1414 s->p[i].port.ops = &max310x_ops; 1415 s->p[i].regmap = regmaps[i]; 1416 1417 /* Disable all interrupts */ 1418 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); 1419 /* Clear IRQ status register */ 1420 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); 1421 /* Initialize queue for start TX */ 1422 INIT_WORK(&s->p[i].tx_work, max310x_tx_proc); 1423 /* Initialize queue for changing LOOPBACK mode */ 1424 INIT_WORK(&s->p[i].md_work, max310x_md_proc); 1425 /* Initialize queue for changing RS485 mode */ 1426 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc); 1427 1428 /* Register port */ 1429 ret = uart_add_one_port(&max310x_uart, &s->p[i].port); 1430 if (ret) { 1431 s->p[i].port.dev = NULL; 1432 goto out_uart; 1433 } 1434 set_bit(line, max310x_lines); 1435 1436 /* Go to suspend mode */ 1437 devtype->power(&s->p[i].port, 0); 1438 } 1439 1440#ifdef CONFIG_GPIOLIB 1441 /* Setup GPIO controller */ 1442 s->gpio.owner = THIS_MODULE; 1443 s->gpio.parent = dev; 1444 s->gpio.label = devtype->name; 1445 s->gpio.direction_input = max310x_gpio_direction_input; 1446 s->gpio.get = max310x_gpio_get; 1447 s->gpio.direction_output= max310x_gpio_direction_output; 1448 s->gpio.set = max310x_gpio_set; 1449 s->gpio.set_config = max310x_gpio_set_config; 1450 s->gpio.base = -1; 1451 s->gpio.ngpio = devtype->nr * 4; 1452 s->gpio.can_sleep = 1; 1453 ret = devm_gpiochip_add_data(dev, &s->gpio, s); 1454 if (ret) 1455 goto out_uart; 1456#endif 1457 1458 /* Setup interrupt */ 1459 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist, 1460 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s); 1461 if (!ret) 1462 return 0; 1463 1464 dev_err(dev, "Unable to request IRQ %i\n", irq); 1465 1466out_uart: 1467 for (i = 0; i < devtype->nr; i++) { 1468 if (s->p[i].port.dev) { 1469 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1470 clear_bit(s->p[i].port.line, max310x_lines); 1471 } 1472 } 1473 1474out_clk: 1475 clk_disable_unprepare(s->clk); 1476 1477 return ret; 1478} 1479 1480static void max310x_remove(struct device *dev) 1481{ 1482 struct max310x_port *s = dev_get_drvdata(dev); 1483 int i; 1484 1485 for (i = 0; i < s->devtype->nr; i++) { 1486 cancel_work_sync(&s->p[i].tx_work); 1487 cancel_work_sync(&s->p[i].md_work); 1488 cancel_work_sync(&s->p[i].rs_work); 1489 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1490 clear_bit(s->p[i].port.line, max310x_lines); 1491 s->devtype->power(&s->p[i].port, 0); 1492 } 1493 1494 clk_disable_unprepare(s->clk); 1495} 1496 1497static const struct of_device_id __maybe_unused max310x_dt_ids[] = { 1498 { .compatible = "maxim,max3107", .data = &max3107_devtype, }, 1499 { .compatible = "maxim,max3108", .data = &max3108_devtype, }, 1500 { .compatible = "maxim,max3109", .data = &max3109_devtype, }, 1501 { .compatible = "maxim,max14830", .data = &max14830_devtype }, 1502 { } 1503}; 1504MODULE_DEVICE_TABLE(of, max310x_dt_ids); 1505 1506static struct regmap_config regcfg = { 1507 .reg_bits = 8, 1508 .val_bits = 8, 1509 .write_flag_mask = MAX310X_WRITE_BIT, 1510 .cache_type = REGCACHE_RBTREE, 1511 .max_register = MAX310X_REG_1F, 1512 .writeable_reg = max310x_reg_writeable, 1513 .volatile_reg = max310x_reg_volatile, 1514 .precious_reg = max310x_reg_precious, 1515 .writeable_noinc_reg = max310x_reg_noinc, 1516 .readable_noinc_reg = max310x_reg_noinc, 1517 .max_raw_read = MAX310X_FIFO_SIZE, 1518 .max_raw_write = MAX310X_FIFO_SIZE, 1519}; 1520 1521#ifdef CONFIG_SPI_MASTER 1522static int max310x_spi_extended_reg_enable(struct device *dev, bool enable) 1523{ 1524 struct max310x_port *s = dev_get_drvdata(dev); 1525 1526 return regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, 1527 enable ? MAX310X_EXTREG_ENBL : MAX310X_EXTREG_DSBL); 1528} 1529 1530static const struct max310x_if_cfg __maybe_unused max310x_spi_if_cfg = { 1531 .extended_reg_enable = max310x_spi_extended_reg_enable, 1532 .rev_id_reg = MAX310X_SPI_REVID_EXTREG, 1533}; 1534 1535static int max310x_spi_probe(struct spi_device *spi) 1536{ 1537 const struct max310x_devtype *devtype; 1538 struct regmap *regmaps[4]; 1539 unsigned int i; 1540 int ret; 1541 1542 /* Setup SPI bus */ 1543 spi->bits_per_word = 8; 1544 spi->mode = spi->mode ? : SPI_MODE_0; 1545 spi->max_speed_hz = spi->max_speed_hz ? : 26000000; 1546 ret = spi_setup(spi); 1547 if (ret) 1548 return ret; 1549 1550 devtype = device_get_match_data(&spi->dev); 1551 if (!devtype) 1552 devtype = (struct max310x_devtype *)spi_get_device_id(spi)->driver_data; 1553 1554 for (i = 0; i < devtype->nr; i++) { 1555 u8 port_mask = i * 0x20; 1556 regcfg.read_flag_mask = port_mask; 1557 regcfg.write_flag_mask = port_mask | MAX310X_WRITE_BIT; 1558 regmaps[i] = devm_regmap_init_spi(spi, ®cfg); 1559 } 1560 1561 return max310x_probe(&spi->dev, devtype, &max310x_spi_if_cfg, regmaps, spi->irq); 1562} 1563 1564static void max310x_spi_remove(struct spi_device *spi) 1565{ 1566 max310x_remove(&spi->dev); 1567} 1568 1569static const struct spi_device_id max310x_id_table[] = { 1570 { "max3107", (kernel_ulong_t)&max3107_devtype, }, 1571 { "max3108", (kernel_ulong_t)&max3108_devtype, }, 1572 { "max3109", (kernel_ulong_t)&max3109_devtype, }, 1573 { "max14830", (kernel_ulong_t)&max14830_devtype, }, 1574 { } 1575}; 1576MODULE_DEVICE_TABLE(spi, max310x_id_table); 1577 1578static struct spi_driver max310x_spi_driver = { 1579 .driver = { 1580 .name = MAX310X_NAME, 1581 .of_match_table = max310x_dt_ids, 1582 .pm = &max310x_pm_ops, 1583 }, 1584 .probe = max310x_spi_probe, 1585 .remove = max310x_spi_remove, 1586 .id_table = max310x_id_table, 1587}; 1588#endif 1589 1590#ifdef CONFIG_I2C 1591static int max310x_i2c_extended_reg_enable(struct device *dev, bool enable) 1592{ 1593 return 0; 1594} 1595 1596static struct regmap_config regcfg_i2c = { 1597 .reg_bits = 8, 1598 .val_bits = 8, 1599 .cache_type = REGCACHE_RBTREE, 1600 .writeable_reg = max310x_reg_writeable, 1601 .volatile_reg = max310x_reg_volatile, 1602 .precious_reg = max310x_reg_precious, 1603 .max_register = MAX310X_I2C_REVID_EXTREG, 1604 .writeable_noinc_reg = max310x_reg_noinc, 1605 .readable_noinc_reg = max310x_reg_noinc, 1606 .max_raw_read = MAX310X_FIFO_SIZE, 1607 .max_raw_write = MAX310X_FIFO_SIZE, 1608}; 1609 1610static const struct max310x_if_cfg max310x_i2c_if_cfg = { 1611 .extended_reg_enable = max310x_i2c_extended_reg_enable, 1612 .rev_id_reg = MAX310X_I2C_REVID_EXTREG, 1613}; 1614 1615static unsigned short max310x_i2c_slave_addr(unsigned short addr, 1616 unsigned int nr) 1617{ 1618 /* 1619 * For MAX14830 and MAX3109, the slave address depends on what the 1620 * A0 and A1 pins are tied to. 1621 * See Table I2C Address Map of the datasheet. 1622 * Based on that table, the following formulas were determined. 1623 * UART1 - UART0 = 0x10 1624 * UART2 - UART1 = 0x20 + 0x10 1625 * UART3 - UART2 = 0x10 1626 */ 1627 1628 addr -= nr * 0x10; 1629 1630 if (nr >= 2) 1631 addr -= 0x20; 1632 1633 return addr; 1634} 1635 1636static int max310x_i2c_probe(struct i2c_client *client) 1637{ 1638 const struct max310x_devtype *devtype; 1639 struct i2c_client *port_client; 1640 struct regmap *regmaps[4]; 1641 unsigned int i; 1642 u8 port_addr; 1643 1644 devtype = device_get_match_data(&client->dev); 1645 if (!devtype) 1646 return dev_err_probe(&client->dev, -ENODEV, "Failed to match device\n"); 1647 1648 if (client->addr < devtype->slave_addr.min || 1649 client->addr > devtype->slave_addr.max) 1650 return dev_err_probe(&client->dev, -EINVAL, 1651 "Slave addr 0x%x outside of range [0x%x, 0x%x]\n", 1652 client->addr, devtype->slave_addr.min, 1653 devtype->slave_addr.max); 1654 1655 regmaps[0] = devm_regmap_init_i2c(client, ®cfg_i2c); 1656 1657 for (i = 1; i < devtype->nr; i++) { 1658 port_addr = max310x_i2c_slave_addr(client->addr, i); 1659 port_client = devm_i2c_new_dummy_device(&client->dev, 1660 client->adapter, 1661 port_addr); 1662 1663 regmaps[i] = devm_regmap_init_i2c(port_client, ®cfg_i2c); 1664 } 1665 1666 return max310x_probe(&client->dev, devtype, &max310x_i2c_if_cfg, 1667 regmaps, client->irq); 1668} 1669 1670static void max310x_i2c_remove(struct i2c_client *client) 1671{ 1672 max310x_remove(&client->dev); 1673} 1674 1675static struct i2c_driver max310x_i2c_driver = { 1676 .driver = { 1677 .name = MAX310X_NAME, 1678 .of_match_table = max310x_dt_ids, 1679 .pm = &max310x_pm_ops, 1680 }, 1681 .probe = max310x_i2c_probe, 1682 .remove = max310x_i2c_remove, 1683}; 1684#endif 1685 1686static int __init max310x_uart_init(void) 1687{ 1688 int ret; 1689 1690 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX); 1691 1692 ret = uart_register_driver(&max310x_uart); 1693 if (ret) 1694 return ret; 1695 1696#ifdef CONFIG_SPI_MASTER 1697 ret = spi_register_driver(&max310x_spi_driver); 1698 if (ret) 1699 goto err_spi_register; 1700#endif 1701 1702#ifdef CONFIG_I2C 1703 ret = i2c_add_driver(&max310x_i2c_driver); 1704 if (ret) 1705 goto err_i2c_register; 1706#endif 1707 1708 return 0; 1709 1710#ifdef CONFIG_I2C 1711err_i2c_register: 1712 spi_unregister_driver(&max310x_spi_driver); 1713#endif 1714 1715err_spi_register: 1716 uart_unregister_driver(&max310x_uart); 1717 1718 return ret; 1719} 1720module_init(max310x_uart_init); 1721 1722static void __exit max310x_uart_exit(void) 1723{ 1724#ifdef CONFIG_I2C 1725 i2c_del_driver(&max310x_i2c_driver); 1726#endif 1727 1728#ifdef CONFIG_SPI_MASTER 1729 spi_unregister_driver(&max310x_spi_driver); 1730#endif 1731 1732 uart_unregister_driver(&max310x_uart); 1733} 1734module_exit(max310x_uart_exit); 1735 1736MODULE_LICENSE("GPL"); 1737MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1738MODULE_DESCRIPTION("MAX310X serial driver"); 1739