1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Driver for CPM (SCC/SMC) serial ports; core driver 4 * 5 * Based on arch/ppc/cpm2_io/uart.c by Dan Malek 6 * Based on ppc8xx.c by Thomas Gleixner 7 * Based on drivers/serial/amba.c by Russell King 8 * 9 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2) 10 * Pantelis Antoniou (panto@intracom.gr) (CPM1) 11 * 12 * Copyright (C) 2004, 2007 Freescale Semiconductor, Inc. 13 * (C) 2004 Intracom, S.A. 14 * (C) 2005-2006 MontaVista Software, Inc. 15 * Vitaly Bordug <vbordug@ru.mvista.com> 16 */ 17 18#include <linux/module.h> 19#include <linux/tty.h> 20#include <linux/tty_flip.h> 21#include <linux/ioport.h> 22#include <linux/init.h> 23#include <linux/serial.h> 24#include <linux/console.h> 25#include <linux/sysrq.h> 26#include <linux/device.h> 27#include <linux/memblock.h> 28#include <linux/dma-mapping.h> 29#include <linux/of_address.h> 30#include <linux/of_irq.h> 31#include <linux/of_platform.h> 32#include <linux/gpio/consumer.h> 33#include <linux/clk.h> 34 35#include <sysdev/fsl_soc.h> 36 37#include <asm/io.h> 38#include <asm/irq.h> 39#include <asm/delay.h> 40#include <asm/udbg.h> 41 42#include <linux/serial_core.h> 43#include <linux/kernel.h> 44 45#include "cpm_uart.h" 46 47 48/**************************************************************/ 49 50static int cpm_uart_tx_pump(struct uart_port *port); 51static void cpm_uart_initbd(struct uart_cpm_port *pinfo); 52 53/**************************************************************/ 54 55#define HW_BUF_SPD_THRESHOLD 2400 56 57static void cpm_line_cr_cmd(struct uart_cpm_port *port, int cmd) 58{ 59 cpm_command(port->command, cmd); 60} 61 62/* 63 * Check, if transmit buffers are processed 64*/ 65static unsigned int cpm_uart_tx_empty(struct uart_port *port) 66{ 67 struct uart_cpm_port *pinfo = 68 container_of(port, struct uart_cpm_port, port); 69 cbd_t __iomem *bdp = pinfo->tx_bd_base; 70 int ret = 0; 71 72 while (1) { 73 if (in_be16(&bdp->cbd_sc) & BD_SC_READY) 74 break; 75 76 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) { 77 ret = TIOCSER_TEMT; 78 break; 79 } 80 bdp++; 81 } 82 83 pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret); 84 85 return ret; 86} 87 88static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 89{ 90 struct uart_cpm_port *pinfo = 91 container_of(port, struct uart_cpm_port, port); 92 93 if (pinfo->gpios[GPIO_RTS]) 94 gpiod_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS)); 95 96 if (pinfo->gpios[GPIO_DTR]) 97 gpiod_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR)); 98} 99 100static unsigned int cpm_uart_get_mctrl(struct uart_port *port) 101{ 102 struct uart_cpm_port *pinfo = 103 container_of(port, struct uart_cpm_port, port); 104 unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 105 106 if (pinfo->gpios[GPIO_CTS]) { 107 if (gpiod_get_value(pinfo->gpios[GPIO_CTS])) 108 mctrl &= ~TIOCM_CTS; 109 } 110 111 if (pinfo->gpios[GPIO_DSR]) { 112 if (gpiod_get_value(pinfo->gpios[GPIO_DSR])) 113 mctrl &= ~TIOCM_DSR; 114 } 115 116 if (pinfo->gpios[GPIO_DCD]) { 117 if (gpiod_get_value(pinfo->gpios[GPIO_DCD])) 118 mctrl &= ~TIOCM_CAR; 119 } 120 121 if (pinfo->gpios[GPIO_RI]) { 122 if (!gpiod_get_value(pinfo->gpios[GPIO_RI])) 123 mctrl |= TIOCM_RNG; 124 } 125 126 return mctrl; 127} 128 129/* 130 * Stop transmitter 131 */ 132static void cpm_uart_stop_tx(struct uart_port *port) 133{ 134 struct uart_cpm_port *pinfo = 135 container_of(port, struct uart_cpm_port, port); 136 smc_t __iomem *smcp = pinfo->smcp; 137 scc_t __iomem *sccp = pinfo->sccp; 138 139 pr_debug("CPM uart[%d]:stop tx\n", port->line); 140 141 if (IS_SMC(pinfo)) 142 clrbits8(&smcp->smc_smcm, SMCM_TX); 143 else 144 clrbits16(&sccp->scc_sccm, UART_SCCM_TX); 145} 146 147/* 148 * Start transmitter 149 */ 150static void cpm_uart_start_tx(struct uart_port *port) 151{ 152 struct uart_cpm_port *pinfo = 153 container_of(port, struct uart_cpm_port, port); 154 smc_t __iomem *smcp = pinfo->smcp; 155 scc_t __iomem *sccp = pinfo->sccp; 156 157 pr_debug("CPM uart[%d]:start tx\n", port->line); 158 159 if (IS_SMC(pinfo)) { 160 if (in_8(&smcp->smc_smcm) & SMCM_TX) 161 return; 162 } else { 163 if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX) 164 return; 165 } 166 167 if (cpm_uart_tx_pump(port) != 0) { 168 if (IS_SMC(pinfo)) { 169 setbits8(&smcp->smc_smcm, SMCM_TX); 170 } else { 171 setbits16(&sccp->scc_sccm, UART_SCCM_TX); 172 } 173 } 174} 175 176/* 177 * Stop receiver 178 */ 179static void cpm_uart_stop_rx(struct uart_port *port) 180{ 181 struct uart_cpm_port *pinfo = 182 container_of(port, struct uart_cpm_port, port); 183 smc_t __iomem *smcp = pinfo->smcp; 184 scc_t __iomem *sccp = pinfo->sccp; 185 186 pr_debug("CPM uart[%d]:stop rx\n", port->line); 187 188 if (IS_SMC(pinfo)) 189 clrbits8(&smcp->smc_smcm, SMCM_RX); 190 else 191 clrbits16(&sccp->scc_sccm, UART_SCCM_RX); 192} 193 194/* 195 * Generate a break. 196 */ 197static void cpm_uart_break_ctl(struct uart_port *port, int break_state) 198{ 199 struct uart_cpm_port *pinfo = 200 container_of(port, struct uart_cpm_port, port); 201 202 pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line, 203 break_state); 204 205 if (break_state) 206 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); 207 else 208 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); 209} 210 211/* 212 * Transmit characters, refill buffer descriptor, if possible 213 */ 214static void cpm_uart_int_tx(struct uart_port *port) 215{ 216 pr_debug("CPM uart[%d]:TX INT\n", port->line); 217 218 cpm_uart_tx_pump(port); 219} 220 221#ifdef CONFIG_CONSOLE_POLL 222static int serial_polled; 223#endif 224 225/* 226 * Receive characters 227 */ 228static void cpm_uart_int_rx(struct uart_port *port) 229{ 230 int i; 231 unsigned char ch; 232 u8 *cp; 233 struct tty_port *tport = &port->state->port; 234 struct uart_cpm_port *pinfo = 235 container_of(port, struct uart_cpm_port, port); 236 cbd_t __iomem *bdp; 237 u16 status; 238 unsigned int flg; 239 240 pr_debug("CPM uart[%d]:RX INT\n", port->line); 241 242 /* Just loop through the closed BDs and copy the characters into 243 * the buffer. 244 */ 245 bdp = pinfo->rx_cur; 246 for (;;) { 247#ifdef CONFIG_CONSOLE_POLL 248 if (unlikely(serial_polled)) { 249 serial_polled = 0; 250 return; 251 } 252#endif 253 /* get status */ 254 status = in_be16(&bdp->cbd_sc); 255 /* If this one is empty, return happy */ 256 if (status & BD_SC_EMPTY) 257 break; 258 259 /* get number of characters, and check spce in flip-buffer */ 260 i = in_be16(&bdp->cbd_datlen); 261 262 /* If we have not enough room in tty flip buffer, then we try 263 * later, which will be the next rx-interrupt or a timeout 264 */ 265 if (tty_buffer_request_room(tport, i) < i) { 266 printk(KERN_WARNING "No room in flip buffer\n"); 267 return; 268 } 269 270 /* get pointer */ 271 cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); 272 273 /* loop through the buffer */ 274 while (i-- > 0) { 275 ch = *cp++; 276 port->icount.rx++; 277 flg = TTY_NORMAL; 278 279 if (status & 280 (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV)) 281 goto handle_error; 282 if (uart_handle_sysrq_char(port, ch)) 283 continue; 284#ifdef CONFIG_CONSOLE_POLL 285 if (unlikely(serial_polled)) { 286 serial_polled = 0; 287 return; 288 } 289#endif 290 error_return: 291 tty_insert_flip_char(tport, ch, flg); 292 293 } /* End while (i--) */ 294 295 /* This BD is ready to be used again. Clear status. get next */ 296 clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR | 297 BD_SC_OV | BD_SC_ID); 298 setbits16(&bdp->cbd_sc, BD_SC_EMPTY); 299 300 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 301 bdp = pinfo->rx_bd_base; 302 else 303 bdp++; 304 305 } /* End for (;;) */ 306 307 /* Write back buffer pointer */ 308 pinfo->rx_cur = bdp; 309 310 /* activate BH processing */ 311 tty_flip_buffer_push(tport); 312 313 return; 314 315 /* Error processing */ 316 317 handle_error: 318 /* Statistics */ 319 if (status & BD_SC_BR) 320 port->icount.brk++; 321 if (status & BD_SC_PR) 322 port->icount.parity++; 323 if (status & BD_SC_FR) 324 port->icount.frame++; 325 if (status & BD_SC_OV) 326 port->icount.overrun++; 327 328 /* Mask out ignored conditions */ 329 status &= port->read_status_mask; 330 331 /* Handle the remaining ones */ 332 if (status & BD_SC_BR) 333 flg = TTY_BREAK; 334 else if (status & BD_SC_PR) 335 flg = TTY_PARITY; 336 else if (status & BD_SC_FR) 337 flg = TTY_FRAME; 338 339 /* overrun does not affect the current character ! */ 340 if (status & BD_SC_OV) { 341 ch = 0; 342 flg = TTY_OVERRUN; 343 /* We skip this buffer */ 344 /* CHECK: Is really nothing senseful there */ 345 /* ASSUMPTION: it contains nothing valid */ 346 i = 0; 347 } 348 port->sysrq = 0; 349 goto error_return; 350} 351 352/* 353 * Asynchron mode interrupt handler 354 */ 355static irqreturn_t cpm_uart_int(int irq, void *data) 356{ 357 u8 events; 358 struct uart_port *port = data; 359 struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; 360 smc_t __iomem *smcp = pinfo->smcp; 361 scc_t __iomem *sccp = pinfo->sccp; 362 363 pr_debug("CPM uart[%d]:IRQ\n", port->line); 364 365 if (IS_SMC(pinfo)) { 366 events = in_8(&smcp->smc_smce); 367 out_8(&smcp->smc_smce, events); 368 if (events & SMCM_BRKE) 369 uart_handle_break(port); 370 if (events & SMCM_RX) 371 cpm_uart_int_rx(port); 372 if (events & SMCM_TX) 373 cpm_uart_int_tx(port); 374 } else { 375 events = in_be16(&sccp->scc_scce); 376 out_be16(&sccp->scc_scce, events); 377 if (events & UART_SCCM_BRKE) 378 uart_handle_break(port); 379 if (events & UART_SCCM_RX) 380 cpm_uart_int_rx(port); 381 if (events & UART_SCCM_TX) 382 cpm_uart_int_tx(port); 383 } 384 return (events) ? IRQ_HANDLED : IRQ_NONE; 385} 386 387static int cpm_uart_startup(struct uart_port *port) 388{ 389 int retval; 390 struct uart_cpm_port *pinfo = 391 container_of(port, struct uart_cpm_port, port); 392 393 pr_debug("CPM uart[%d]:startup\n", port->line); 394 395 /* If the port is not the console, make sure rx is disabled. */ 396 if (!(pinfo->flags & FLAG_CONSOLE)) { 397 /* Disable UART rx */ 398 if (IS_SMC(pinfo)) { 399 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN); 400 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX); 401 } else { 402 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR); 403 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); 404 } 405 cpm_uart_initbd(pinfo); 406 if (IS_SMC(pinfo)) { 407 out_be32(&pinfo->smcup->smc_rstate, 0); 408 out_be32(&pinfo->smcup->smc_tstate, 0); 409 out_be16(&pinfo->smcup->smc_rbptr, 410 in_be16(&pinfo->smcup->smc_rbase)); 411 out_be16(&pinfo->smcup->smc_tbptr, 412 in_be16(&pinfo->smcup->smc_tbase)); 413 } else { 414 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); 415 } 416 } 417 /* Install interrupt handler. */ 418 retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port); 419 if (retval) 420 return retval; 421 422 /* Startup rx-int */ 423 if (IS_SMC(pinfo)) { 424 setbits8(&pinfo->smcp->smc_smcm, SMCM_RX); 425 setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN)); 426 } else { 427 setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); 428 setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT)); 429 } 430 431 return 0; 432} 433 434inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo) 435{ 436 set_current_state(TASK_UNINTERRUPTIBLE); 437 schedule_timeout(pinfo->wait_closing); 438} 439 440/* 441 * Shutdown the uart 442 */ 443static void cpm_uart_shutdown(struct uart_port *port) 444{ 445 struct uart_cpm_port *pinfo = 446 container_of(port, struct uart_cpm_port, port); 447 448 pr_debug("CPM uart[%d]:shutdown\n", port->line); 449 450 /* free interrupt handler */ 451 free_irq(port->irq, port); 452 453 /* If the port is not the console, disable Rx and Tx. */ 454 if (!(pinfo->flags & FLAG_CONSOLE)) { 455 /* Wait for all the BDs marked sent */ 456 while(!cpm_uart_tx_empty(port)) { 457 set_current_state(TASK_UNINTERRUPTIBLE); 458 schedule_timeout(2); 459 } 460 461 if (pinfo->wait_closing) 462 cpm_uart_wait_until_send(pinfo); 463 464 /* Stop uarts */ 465 if (IS_SMC(pinfo)) { 466 smc_t __iomem *smcp = pinfo->smcp; 467 clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 468 clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX); 469 } else { 470 scc_t __iomem *sccp = pinfo->sccp; 471 clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 472 clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); 473 } 474 475 /* Shut them really down and reinit buffer descriptors */ 476 if (IS_SMC(pinfo)) { 477 out_be16(&pinfo->smcup->smc_brkcr, 0); 478 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); 479 } else { 480 out_be16(&pinfo->sccup->scc_brkcr, 0); 481 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); 482 } 483 484 cpm_uart_initbd(pinfo); 485 } 486} 487 488static void cpm_uart_set_termios(struct uart_port *port, 489 struct ktermios *termios, 490 const struct ktermios *old) 491{ 492 int baud; 493 unsigned long flags; 494 u16 cval, scval, prev_mode; 495 struct uart_cpm_port *pinfo = 496 container_of(port, struct uart_cpm_port, port); 497 smc_t __iomem *smcp = pinfo->smcp; 498 scc_t __iomem *sccp = pinfo->sccp; 499 int maxidl; 500 501 pr_debug("CPM uart[%d]:set_termios\n", port->line); 502 503 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 504 if (baud < HW_BUF_SPD_THRESHOLD || port->flags & UPF_LOW_LATENCY) 505 pinfo->rx_fifosize = 1; 506 else 507 pinfo->rx_fifosize = RX_BUF_SIZE; 508 509 /* MAXIDL is the timeout after which a receive buffer is closed 510 * when not full if no more characters are received. 511 * We calculate it from the baudrate so that the duration is 512 * always the same at standard rates: about 4ms. 513 */ 514 maxidl = baud / 2400; 515 if (maxidl < 1) 516 maxidl = 1; 517 if (maxidl > 0x10) 518 maxidl = 0x10; 519 520 cval = 0; 521 scval = 0; 522 523 if (termios->c_cflag & CSTOPB) { 524 cval |= SMCMR_SL; /* Two stops */ 525 scval |= SCU_PSMR_SL; 526 } 527 528 if (termios->c_cflag & PARENB) { 529 cval |= SMCMR_PEN; 530 scval |= SCU_PSMR_PEN; 531 if (!(termios->c_cflag & PARODD)) { 532 cval |= SMCMR_PM_EVEN; 533 scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP); 534 } 535 } 536 537 /* 538 * Update the timeout 539 */ 540 uart_update_timeout(port, termios->c_cflag, baud); 541 542 /* 543 * Set up parity check flag 544 */ 545 port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV); 546 if (termios->c_iflag & INPCK) 547 port->read_status_mask |= BD_SC_FR | BD_SC_PR; 548 if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK)) 549 port->read_status_mask |= BD_SC_BR; 550 551 /* 552 * Characters to ignore 553 */ 554 port->ignore_status_mask = 0; 555 if (termios->c_iflag & IGNPAR) 556 port->ignore_status_mask |= BD_SC_PR | BD_SC_FR; 557 if (termios->c_iflag & IGNBRK) { 558 port->ignore_status_mask |= BD_SC_BR; 559 /* 560 * If we're ignore parity and break indicators, ignore 561 * overruns too. (For real raw support). 562 */ 563 if (termios->c_iflag & IGNPAR) 564 port->ignore_status_mask |= BD_SC_OV; 565 } 566 /* 567 * !!! ignore all characters if CREAD is not set 568 */ 569 if ((termios->c_cflag & CREAD) == 0) 570 port->read_status_mask &= ~BD_SC_EMPTY; 571 572 spin_lock_irqsave(&port->lock, flags); 573 574 if (IS_SMC(pinfo)) { 575 unsigned int bits = tty_get_frame_size(termios->c_cflag); 576 577 /* 578 * MRBLR can be changed while an SMC/SCC is operating only 579 * if it is done in a single bus cycle with one 16-bit move 580 * (not two 8-bit bus cycles back-to-back). This occurs when 581 * the cp shifts control to the next RxBD, so the change does 582 * not take effect immediately. To guarantee the exact RxBD 583 * on which the change occurs, change MRBLR only while the 584 * SMC/SCC receiver is disabled. 585 */ 586 out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize); 587 out_be16(&pinfo->smcup->smc_maxidl, maxidl); 588 589 /* Set the mode register. We want to keep a copy of the 590 * enables, because we want to put them back if they were 591 * present. 592 */ 593 prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN); 594 /* Output in *one* operation, so we don't interrupt RX/TX if they 595 * were already enabled. 596 * Character length programmed into the register is frame bits minus 1. 597 */ 598 out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits - 1) | cval | 599 SMCMR_SM_UART | prev_mode); 600 } else { 601 unsigned int bits = tty_get_char_size(termios->c_cflag); 602 603 out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize); 604 out_be16(&pinfo->sccup->scc_maxidl, maxidl); 605 out_be16(&sccp->scc_psmr, (UART_LCR_WLEN(bits) << 12) | scval); 606 } 607 608 if (pinfo->clk) 609 clk_set_rate(pinfo->clk, baud); 610 else 611 cpm_setbrg(pinfo->brg - 1, baud); 612 spin_unlock_irqrestore(&port->lock, flags); 613} 614 615static const char *cpm_uart_type(struct uart_port *port) 616{ 617 pr_debug("CPM uart[%d]:uart_type\n", port->line); 618 619 return port->type == PORT_CPM ? "CPM UART" : NULL; 620} 621 622/* 623 * verify the new serial_struct (for TIOCSSERIAL). 624 */ 625static int cpm_uart_verify_port(struct uart_port *port, 626 struct serial_struct *ser) 627{ 628 int ret = 0; 629 630 pr_debug("CPM uart[%d]:verify_port\n", port->line); 631 632 if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM) 633 ret = -EINVAL; 634 if (ser->irq < 0 || ser->irq >= nr_irqs) 635 ret = -EINVAL; 636 if (ser->baud_base < 9600) 637 ret = -EINVAL; 638 return ret; 639} 640 641/* 642 * Transmit characters, refill buffer descriptor, if possible 643 */ 644static int cpm_uart_tx_pump(struct uart_port *port) 645{ 646 cbd_t __iomem *bdp; 647 u8 *p; 648 int count; 649 struct uart_cpm_port *pinfo = 650 container_of(port, struct uart_cpm_port, port); 651 struct circ_buf *xmit = &port->state->xmit; 652 653 /* Handle xon/xoff */ 654 if (port->x_char) { 655 /* Pick next descriptor and fill from buffer */ 656 bdp = pinfo->tx_cur; 657 658 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); 659 660 *p++ = port->x_char; 661 662 out_be16(&bdp->cbd_datlen, 1); 663 setbits16(&bdp->cbd_sc, BD_SC_READY); 664 /* Get next BD. */ 665 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 666 bdp = pinfo->tx_bd_base; 667 else 668 bdp++; 669 pinfo->tx_cur = bdp; 670 671 port->icount.tx++; 672 port->x_char = 0; 673 return 1; 674 } 675 676 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 677 cpm_uart_stop_tx(port); 678 return 0; 679 } 680 681 /* Pick next descriptor and fill from buffer */ 682 bdp = pinfo->tx_cur; 683 684 while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) && !uart_circ_empty(xmit)) { 685 count = 0; 686 p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); 687 while (count < pinfo->tx_fifosize) { 688 *p++ = xmit->buf[xmit->tail]; 689 uart_xmit_advance(port, 1); 690 count++; 691 if (uart_circ_empty(xmit)) 692 break; 693 } 694 out_be16(&bdp->cbd_datlen, count); 695 setbits16(&bdp->cbd_sc, BD_SC_READY); 696 /* Get next BD. */ 697 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 698 bdp = pinfo->tx_bd_base; 699 else 700 bdp++; 701 } 702 pinfo->tx_cur = bdp; 703 704 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 705 uart_write_wakeup(port); 706 707 if (uart_circ_empty(xmit)) { 708 cpm_uart_stop_tx(port); 709 return 0; 710 } 711 712 return 1; 713} 714 715/* 716 * init buffer descriptors 717 */ 718static void cpm_uart_initbd(struct uart_cpm_port *pinfo) 719{ 720 int i; 721 u8 *mem_addr; 722 cbd_t __iomem *bdp; 723 724 pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line); 725 726 /* Set the physical address of the host memory 727 * buffers in the buffer descriptors, and the 728 * virtual address for us to work with. 729 */ 730 mem_addr = pinfo->mem_addr; 731 bdp = pinfo->rx_cur = pinfo->rx_bd_base; 732 for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) { 733 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 734 out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT); 735 mem_addr += pinfo->rx_fifosize; 736 } 737 738 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 739 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT); 740 741 /* Set the physical address of the host memory 742 * buffers in the buffer descriptors, and the 743 * virtual address for us to work with. 744 */ 745 mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize); 746 bdp = pinfo->tx_cur = pinfo->tx_bd_base; 747 for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) { 748 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 749 out_be16(&bdp->cbd_sc, BD_SC_INTRPT); 750 mem_addr += pinfo->tx_fifosize; 751 } 752 753 out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); 754 out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT); 755} 756 757static void cpm_uart_init_scc(struct uart_cpm_port *pinfo) 758{ 759 scc_t __iomem *scp; 760 scc_uart_t __iomem *sup; 761 762 pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line); 763 764 scp = pinfo->sccp; 765 sup = pinfo->sccup; 766 767 /* Store address */ 768 out_be16(&pinfo->sccup->scc_genscc.scc_rbase, 769 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); 770 out_be16(&pinfo->sccup->scc_genscc.scc_tbase, 771 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); 772 773 /* Set up the uart parameters in the 774 * parameter ram. 775 */ 776 777 out_8(&sup->scc_genscc.scc_rfcr, CPMFCR_GBL | CPMFCR_EB); 778 out_8(&sup->scc_genscc.scc_tfcr, CPMFCR_GBL | CPMFCR_EB); 779 780 out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize); 781 out_be16(&sup->scc_maxidl, 0x10); 782 out_be16(&sup->scc_brkcr, 1); 783 out_be16(&sup->scc_parec, 0); 784 out_be16(&sup->scc_frmec, 0); 785 out_be16(&sup->scc_nosec, 0); 786 out_be16(&sup->scc_brkec, 0); 787 out_be16(&sup->scc_uaddr1, 0); 788 out_be16(&sup->scc_uaddr2, 0); 789 out_be16(&sup->scc_toseq, 0); 790 out_be16(&sup->scc_char1, 0x8000); 791 out_be16(&sup->scc_char2, 0x8000); 792 out_be16(&sup->scc_char3, 0x8000); 793 out_be16(&sup->scc_char4, 0x8000); 794 out_be16(&sup->scc_char5, 0x8000); 795 out_be16(&sup->scc_char6, 0x8000); 796 out_be16(&sup->scc_char7, 0x8000); 797 out_be16(&sup->scc_char8, 0x8000); 798 out_be16(&sup->scc_rccm, 0xc0ff); 799 800 /* Send the CPM an initialize command. 801 */ 802 cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); 803 804 /* Set UART mode, 8 bit, no parity, one stop. 805 * Enable receive and transmit. 806 */ 807 out_be32(&scp->scc_gsmrh, 0); 808 out_be32(&scp->scc_gsmrl, 809 SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); 810 811 /* Enable rx interrupts and clear all pending events. */ 812 out_be16(&scp->scc_sccm, 0); 813 out_be16(&scp->scc_scce, 0xffff); 814 out_be16(&scp->scc_dsr, 0x7e7e); 815 out_be16(&scp->scc_psmr, 0x3000); 816 817 setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 818} 819 820static void cpm_uart_init_smc(struct uart_cpm_port *pinfo) 821{ 822 smc_t __iomem *sp; 823 smc_uart_t __iomem *up; 824 825 pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line); 826 827 sp = pinfo->smcp; 828 up = pinfo->smcup; 829 830 /* Store address */ 831 out_be16(&pinfo->smcup->smc_rbase, 832 (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); 833 out_be16(&pinfo->smcup->smc_tbase, 834 (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); 835 836/* 837 * In case SMC is being relocated... 838 */ 839 out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase)); 840 out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase)); 841 out_be32(&up->smc_rstate, 0); 842 out_be32(&up->smc_tstate, 0); 843 out_be16(&up->smc_brkcr, 1); /* number of break chars */ 844 out_be16(&up->smc_brkec, 0); 845 846 /* Set up the uart parameters in the 847 * parameter ram. 848 */ 849 out_8(&up->smc_rfcr, CPMFCR_GBL | CPMFCR_EB); 850 out_8(&up->smc_tfcr, CPMFCR_GBL | CPMFCR_EB); 851 852 /* Using idle character time requires some additional tuning. */ 853 out_be16(&up->smc_mrblr, pinfo->rx_fifosize); 854 out_be16(&up->smc_maxidl, 0x10); 855 out_be16(&up->smc_brklen, 0); 856 out_be16(&up->smc_brkec, 0); 857 out_be16(&up->smc_brkcr, 1); 858 859 /* Set UART mode, 8 bit, no parity, one stop. 860 * Enable receive and transmit. 861 */ 862 out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART); 863 864 /* Enable only rx interrupts clear all pending events. */ 865 out_8(&sp->smc_smcm, 0); 866 out_8(&sp->smc_smce, 0xff); 867 868 setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 869} 870 871/* 872 * Allocate DP-Ram and memory buffers. We need to allocate a transmit and 873 * receive buffer descriptors from dual port ram, and a character 874 * buffer area from host mem. If we are allocating for the console we need 875 * to do it from bootmem 876 */ 877static int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con) 878{ 879 int dpmemsz, memsz; 880 u8 __iomem *dp_mem; 881 unsigned long dp_offset; 882 u8 *mem_addr; 883 dma_addr_t dma_addr = 0; 884 885 pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line); 886 887 dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos); 888 dp_offset = cpm_muram_alloc(dpmemsz, 8); 889 if (IS_ERR_VALUE(dp_offset)) { 890 pr_err("%s: could not allocate buffer descriptors\n", __func__); 891 return -ENOMEM; 892 } 893 894 dp_mem = cpm_muram_addr(dp_offset); 895 896 memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) + 897 L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize); 898 if (IS_ENABLED(CONFIG_CPM1) && is_con) { 899 /* was hostalloc but changed cause it blows away the */ 900 /* large tlb mapping when pinning the kernel area */ 901 mem_addr = (u8 __force *)cpm_muram_addr(cpm_muram_alloc(memsz, 8)); 902 dma_addr = cpm_muram_dma((void __iomem *)mem_addr); 903 } else if (is_con) { 904 mem_addr = kzalloc(memsz, GFP_NOWAIT); 905 dma_addr = virt_to_bus(mem_addr); 906 } else { 907 mem_addr = dma_alloc_coherent(pinfo->port.dev, memsz, &dma_addr, 908 GFP_KERNEL); 909 } 910 911 if (!mem_addr) { 912 cpm_muram_free(dp_offset); 913 pr_err("%s: could not allocate coherent memory\n", __func__); 914 return -ENOMEM; 915 } 916 917 pinfo->dp_addr = dp_offset; 918 pinfo->mem_addr = mem_addr; 919 pinfo->dma_addr = dma_addr; 920 pinfo->mem_size = memsz; 921 922 pinfo->rx_buf = mem_addr; 923 pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos 924 * pinfo->rx_fifosize); 925 926 pinfo->rx_bd_base = (cbd_t __iomem *)dp_mem; 927 pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos; 928 929 return 0; 930} 931 932static void cpm_uart_freebuf(struct uart_cpm_port *pinfo) 933{ 934 dma_free_coherent(pinfo->port.dev, L1_CACHE_ALIGN(pinfo->rx_nrfifos * 935 pinfo->rx_fifosize) + 936 L1_CACHE_ALIGN(pinfo->tx_nrfifos * 937 pinfo->tx_fifosize), (void __force *)pinfo->mem_addr, 938 pinfo->dma_addr); 939 940 cpm_muram_free(pinfo->dp_addr); 941} 942 943/* 944 * Initialize port. This is called from early_console stuff 945 * so we have to be careful here ! 946 */ 947static int cpm_uart_request_port(struct uart_port *port) 948{ 949 struct uart_cpm_port *pinfo = 950 container_of(port, struct uart_cpm_port, port); 951 int ret; 952 953 pr_debug("CPM uart[%d]:request port\n", port->line); 954 955 if (pinfo->flags & FLAG_CONSOLE) 956 return 0; 957 958 if (IS_SMC(pinfo)) { 959 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); 960 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 961 } else { 962 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); 963 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 964 } 965 966 ret = cpm_uart_allocbuf(pinfo, 0); 967 968 if (ret) 969 return ret; 970 971 cpm_uart_initbd(pinfo); 972 if (IS_SMC(pinfo)) 973 cpm_uart_init_smc(pinfo); 974 else 975 cpm_uart_init_scc(pinfo); 976 977 return 0; 978} 979 980static void cpm_uart_release_port(struct uart_port *port) 981{ 982 struct uart_cpm_port *pinfo = 983 container_of(port, struct uart_cpm_port, port); 984 985 if (!(pinfo->flags & FLAG_CONSOLE)) 986 cpm_uart_freebuf(pinfo); 987} 988 989/* 990 * Configure/autoconfigure the port. 991 */ 992static void cpm_uart_config_port(struct uart_port *port, int flags) 993{ 994 pr_debug("CPM uart[%d]:config_port\n", port->line); 995 996 if (flags & UART_CONFIG_TYPE) { 997 port->type = PORT_CPM; 998 cpm_uart_request_port(port); 999 } 1000} 1001 1002#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE) 1003/* 1004 * Write a string to the serial port 1005 * Note that this is called with interrupts already disabled 1006 */ 1007static void cpm_uart_early_write(struct uart_cpm_port *pinfo, 1008 const char *string, u_int count, bool handle_linefeed) 1009{ 1010 unsigned int i; 1011 cbd_t __iomem *bdp, *bdbase; 1012 unsigned char *cpm_outp_addr; 1013 1014 /* Get the address of the host memory buffer. 1015 */ 1016 bdp = pinfo->tx_cur; 1017 bdbase = pinfo->tx_bd_base; 1018 1019 /* 1020 * Now, do each character. This is not as bad as it looks 1021 * since this is a holding FIFO and not a transmitting FIFO. 1022 * We could add the complexity of filling the entire transmit 1023 * buffer, but we would just wait longer between accesses...... 1024 */ 1025 for (i = 0; i < count; i++, string++) { 1026 /* Wait for transmitter fifo to empty. 1027 * Ready indicates output is ready, and xmt is doing 1028 * that, not that it is ready for us to send. 1029 */ 1030 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) 1031 ; 1032 1033 /* Send the character out. 1034 * If the buffer address is in the CPM DPRAM, don't 1035 * convert it. 1036 */ 1037 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), 1038 pinfo); 1039 *cpm_outp_addr = *string; 1040 1041 out_be16(&bdp->cbd_datlen, 1); 1042 setbits16(&bdp->cbd_sc, BD_SC_READY); 1043 1044 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 1045 bdp = bdbase; 1046 else 1047 bdp++; 1048 1049 /* if a LF, also do CR... */ 1050 if (handle_linefeed && *string == 10) { 1051 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) 1052 ; 1053 1054 cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), 1055 pinfo); 1056 *cpm_outp_addr = 13; 1057 1058 out_be16(&bdp->cbd_datlen, 1); 1059 setbits16(&bdp->cbd_sc, BD_SC_READY); 1060 1061 if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) 1062 bdp = bdbase; 1063 else 1064 bdp++; 1065 } 1066 } 1067 1068 /* 1069 * Finally, Wait for transmitter & holding register to empty 1070 * and restore the IER 1071 */ 1072 while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) 1073 ; 1074 1075 pinfo->tx_cur = bdp; 1076} 1077#endif 1078 1079#ifdef CONFIG_CONSOLE_POLL 1080/* Serial polling routines for writing and reading from the uart while 1081 * in an interrupt or debug context. 1082 */ 1083 1084#define GDB_BUF_SIZE 512 /* power of 2, please */ 1085 1086static char poll_buf[GDB_BUF_SIZE]; 1087static char *pollp; 1088static int poll_chars; 1089 1090static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo) 1091{ 1092 u_char c, *cp; 1093 volatile cbd_t *bdp; 1094 int i; 1095 1096 /* Get the address of the host memory buffer. 1097 */ 1098 bdp = pinfo->rx_cur; 1099 if (bdp->cbd_sc & BD_SC_EMPTY) 1100 return NO_POLL_CHAR; 1101 1102 /* If the buffer address is in the CPM DPRAM, don't 1103 * convert it. 1104 */ 1105 cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo); 1106 1107 if (obuf) { 1108 i = c = bdp->cbd_datlen; 1109 while (i-- > 0) 1110 *obuf++ = *cp++; 1111 } else 1112 c = *cp; 1113 bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID); 1114 bdp->cbd_sc |= BD_SC_EMPTY; 1115 1116 if (bdp->cbd_sc & BD_SC_WRAP) 1117 bdp = pinfo->rx_bd_base; 1118 else 1119 bdp++; 1120 pinfo->rx_cur = (cbd_t *)bdp; 1121 1122 return (int)c; 1123} 1124 1125static int cpm_get_poll_char(struct uart_port *port) 1126{ 1127 struct uart_cpm_port *pinfo = 1128 container_of(port, struct uart_cpm_port, port); 1129 1130 if (!serial_polled) { 1131 serial_polled = 1; 1132 poll_chars = 0; 1133 } 1134 if (poll_chars <= 0) { 1135 int ret = poll_wait_key(poll_buf, pinfo); 1136 1137 if (ret == NO_POLL_CHAR) 1138 return ret; 1139 poll_chars = ret; 1140 pollp = poll_buf; 1141 } 1142 poll_chars--; 1143 return *pollp++; 1144} 1145 1146static void cpm_put_poll_char(struct uart_port *port, 1147 unsigned char c) 1148{ 1149 struct uart_cpm_port *pinfo = 1150 container_of(port, struct uart_cpm_port, port); 1151 static char ch[2]; 1152 1153 ch[0] = (char)c; 1154 cpm_uart_early_write(pinfo, ch, 1, false); 1155} 1156 1157#ifdef CONFIG_SERIAL_CPM_CONSOLE 1158static struct uart_port *udbg_port; 1159 1160static void udbg_cpm_putc(char c) 1161{ 1162 if (c == '\n') 1163 cpm_put_poll_char(udbg_port, '\r'); 1164 cpm_put_poll_char(udbg_port, c); 1165} 1166 1167static int udbg_cpm_getc_poll(void) 1168{ 1169 int c = cpm_get_poll_char(udbg_port); 1170 1171 return c == NO_POLL_CHAR ? -1 : c; 1172} 1173 1174static int udbg_cpm_getc(void) 1175{ 1176 int c; 1177 1178 while ((c = udbg_cpm_getc_poll()) == -1) 1179 cpu_relax(); 1180 return c; 1181} 1182#endif /* CONFIG_SERIAL_CPM_CONSOLE */ 1183 1184#endif /* CONFIG_CONSOLE_POLL */ 1185 1186static const struct uart_ops cpm_uart_pops = { 1187 .tx_empty = cpm_uart_tx_empty, 1188 .set_mctrl = cpm_uart_set_mctrl, 1189 .get_mctrl = cpm_uart_get_mctrl, 1190 .stop_tx = cpm_uart_stop_tx, 1191 .start_tx = cpm_uart_start_tx, 1192 .stop_rx = cpm_uart_stop_rx, 1193 .break_ctl = cpm_uart_break_ctl, 1194 .startup = cpm_uart_startup, 1195 .shutdown = cpm_uart_shutdown, 1196 .set_termios = cpm_uart_set_termios, 1197 .type = cpm_uart_type, 1198 .release_port = cpm_uart_release_port, 1199 .request_port = cpm_uart_request_port, 1200 .config_port = cpm_uart_config_port, 1201 .verify_port = cpm_uart_verify_port, 1202#ifdef CONFIG_CONSOLE_POLL 1203 .poll_get_char = cpm_get_poll_char, 1204 .poll_put_char = cpm_put_poll_char, 1205#endif 1206}; 1207 1208static struct uart_cpm_port cpm_uart_ports[UART_NR]; 1209 1210static void __iomem *cpm_uart_map_pram(struct uart_cpm_port *port, 1211 struct device_node *np) 1212{ 1213 void __iomem *pram; 1214 unsigned long offset; 1215 struct resource res; 1216 resource_size_t len; 1217 1218 /* Don't remap parameter RAM if it has already been initialized 1219 * during console setup. 1220 */ 1221 if (IS_SMC(port) && port->smcup) 1222 return port->smcup; 1223 else if (!IS_SMC(port) && port->sccup) 1224 return port->sccup; 1225 1226 if (of_address_to_resource(np, 1, &res)) 1227 return NULL; 1228 1229 len = resource_size(&res); 1230 pram = ioremap(res.start, len); 1231 if (!pram) 1232 return NULL; 1233 1234 if (!IS_ENABLED(CONFIG_CPM2) || !IS_SMC(port)) 1235 return pram; 1236 1237 if (len != 2) { 1238 pr_warn("cpm_uart[%d]: device tree references " 1239 "SMC pram, using boot loader/wrapper pram mapping. " 1240 "Please fix your device tree to reference the pram " 1241 "base register instead.\n", 1242 port->port.line); 1243 return pram; 1244 } 1245 1246 offset = cpm_muram_alloc(64, 64); 1247 out_be16(pram, offset); 1248 iounmap(pram); 1249 return cpm_muram_addr(offset); 1250} 1251 1252static void cpm_uart_unmap_pram(struct uart_cpm_port *port, void __iomem *pram) 1253{ 1254 if (!IS_ENABLED(CONFIG_CPM2) || !IS_SMC(port)) 1255 iounmap(pram); 1256} 1257 1258static int cpm_uart_init_port(struct device_node *np, 1259 struct uart_cpm_port *pinfo) 1260{ 1261 const u32 *data; 1262 void __iomem *mem, *pram; 1263 struct device *dev = pinfo->port.dev; 1264 int len; 1265 int ret; 1266 int i; 1267 1268 data = of_get_property(np, "clock", NULL); 1269 if (data) { 1270 struct clk *clk = clk_get(NULL, (const char*)data); 1271 if (!IS_ERR(clk)) 1272 pinfo->clk = clk; 1273 } 1274 if (!pinfo->clk) { 1275 data = of_get_property(np, "fsl,cpm-brg", &len); 1276 if (!data || len != 4) { 1277 printk(KERN_ERR "CPM UART %pOFn has no/invalid " 1278 "fsl,cpm-brg property.\n", np); 1279 return -EINVAL; 1280 } 1281 pinfo->brg = *data; 1282 } 1283 1284 data = of_get_property(np, "fsl,cpm-command", &len); 1285 if (!data || len != 4) { 1286 printk(KERN_ERR "CPM UART %pOFn has no/invalid " 1287 "fsl,cpm-command property.\n", np); 1288 return -EINVAL; 1289 } 1290 pinfo->command = *data; 1291 1292 mem = of_iomap(np, 0); 1293 if (!mem) 1294 return -ENOMEM; 1295 1296 if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") || 1297 of_device_is_compatible(np, "fsl,cpm2-scc-uart")) { 1298 pinfo->sccp = mem; 1299 pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np); 1300 } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") || 1301 of_device_is_compatible(np, "fsl,cpm2-smc-uart")) { 1302 pinfo->flags |= FLAG_SMC; 1303 pinfo->smcp = mem; 1304 pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np); 1305 } else { 1306 ret = -ENODEV; 1307 goto out_mem; 1308 } 1309 1310 if (!pram) { 1311 ret = -ENOMEM; 1312 goto out_mem; 1313 } 1314 1315 pinfo->tx_nrfifos = TX_NUM_FIFO; 1316 pinfo->tx_fifosize = TX_BUF_SIZE; 1317 pinfo->rx_nrfifos = RX_NUM_FIFO; 1318 pinfo->rx_fifosize = RX_BUF_SIZE; 1319 1320 pinfo->port.uartclk = ppc_proc_freq; 1321 pinfo->port.mapbase = (unsigned long)mem; 1322 pinfo->port.type = PORT_CPM; 1323 pinfo->port.ops = &cpm_uart_pops; 1324 pinfo->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_CPM_CONSOLE); 1325 pinfo->port.iotype = UPIO_MEM; 1326 pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize; 1327 spin_lock_init(&pinfo->port.lock); 1328 1329 for (i = 0; i < NUM_GPIOS; i++) { 1330 struct gpio_desc *gpiod; 1331 1332 pinfo->gpios[i] = NULL; 1333 1334 gpiod = devm_gpiod_get_index_optional(dev, NULL, i, GPIOD_ASIS); 1335 1336 if (IS_ERR(gpiod)) { 1337 ret = PTR_ERR(gpiod); 1338 goto out_pram; 1339 } 1340 1341 if (gpiod) { 1342 if (i == GPIO_RTS || i == GPIO_DTR) 1343 ret = gpiod_direction_output(gpiod, 0); 1344 else 1345 ret = gpiod_direction_input(gpiod); 1346 if (ret) { 1347 pr_err("can't set direction for gpio #%d: %d\n", 1348 i, ret); 1349 continue; 1350 } 1351 pinfo->gpios[i] = gpiod; 1352 } 1353 } 1354 1355#ifdef CONFIG_PPC_EARLY_DEBUG_CPM 1356#if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_CPM_CONSOLE) 1357 if (!udbg_port) 1358#endif 1359 udbg_putc = NULL; 1360#endif 1361 1362 return cpm_uart_request_port(&pinfo->port); 1363 1364out_pram: 1365 cpm_uart_unmap_pram(pinfo, pram); 1366out_mem: 1367 iounmap(mem); 1368 return ret; 1369} 1370 1371#ifdef CONFIG_SERIAL_CPM_CONSOLE 1372/* 1373 * Print a string to the serial port trying not to disturb 1374 * any possible real use of the port... 1375 * 1376 * Note that this is called with interrupts already disabled 1377 */ 1378static void cpm_uart_console_write(struct console *co, const char *s, 1379 u_int count) 1380{ 1381 struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index]; 1382 unsigned long flags; 1383 1384 if (unlikely(oops_in_progress)) { 1385 local_irq_save(flags); 1386 cpm_uart_early_write(pinfo, s, count, true); 1387 local_irq_restore(flags); 1388 } else { 1389 spin_lock_irqsave(&pinfo->port.lock, flags); 1390 cpm_uart_early_write(pinfo, s, count, true); 1391 spin_unlock_irqrestore(&pinfo->port.lock, flags); 1392 } 1393} 1394 1395 1396static int __init cpm_uart_console_setup(struct console *co, char *options) 1397{ 1398 int baud = 38400; 1399 int bits = 8; 1400 int parity = 'n'; 1401 int flow = 'n'; 1402 int ret; 1403 struct uart_cpm_port *pinfo; 1404 struct uart_port *port; 1405 1406 struct device_node *np; 1407 int i = 0; 1408 1409 if (co->index >= UART_NR) { 1410 printk(KERN_ERR "cpm_uart: console index %d too high\n", 1411 co->index); 1412 return -ENODEV; 1413 } 1414 1415 for_each_node_by_type(np, "serial") { 1416 if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") && 1417 !of_device_is_compatible(np, "fsl,cpm1-scc-uart") && 1418 !of_device_is_compatible(np, "fsl,cpm2-smc-uart") && 1419 !of_device_is_compatible(np, "fsl,cpm2-scc-uart")) 1420 continue; 1421 1422 if (i++ == co->index) 1423 break; 1424 } 1425 1426 if (!np) 1427 return -ENODEV; 1428 1429 pinfo = &cpm_uart_ports[co->index]; 1430 1431 pinfo->flags |= FLAG_CONSOLE; 1432 port = &pinfo->port; 1433 1434 ret = cpm_uart_init_port(np, pinfo); 1435 of_node_put(np); 1436 if (ret) 1437 return ret; 1438 1439 if (options) { 1440 uart_parse_options(options, &baud, &parity, &bits, &flow); 1441 } else { 1442 baud = get_baudrate(); 1443 if (baud == -1) 1444 baud = 9600; 1445 } 1446 1447 if (IS_SMC(pinfo)) { 1448 out_be16(&pinfo->smcup->smc_brkcr, 0); 1449 cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); 1450 clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); 1451 clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); 1452 } else { 1453 out_be16(&pinfo->sccup->scc_brkcr, 0); 1454 cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); 1455 clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); 1456 clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); 1457 } 1458 1459 ret = cpm_uart_allocbuf(pinfo, 1); 1460 1461 if (ret) 1462 return ret; 1463 1464 cpm_uart_initbd(pinfo); 1465 1466 if (IS_SMC(pinfo)) 1467 cpm_uart_init_smc(pinfo); 1468 else 1469 cpm_uart_init_scc(pinfo); 1470 1471 uart_set_options(port, co, baud, parity, bits, flow); 1472 cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); 1473 1474#ifdef CONFIG_CONSOLE_POLL 1475 if (!udbg_port) { 1476 udbg_port = &pinfo->port; 1477 udbg_putc = udbg_cpm_putc; 1478 udbg_getc = udbg_cpm_getc; 1479 udbg_getc_poll = udbg_cpm_getc_poll; 1480 } 1481#endif 1482 1483 return 0; 1484} 1485 1486static struct uart_driver cpm_reg; 1487static struct console cpm_scc_uart_console = { 1488 .name = "ttyCPM", 1489 .write = cpm_uart_console_write, 1490 .device = uart_console_device, 1491 .setup = cpm_uart_console_setup, 1492 .flags = CON_PRINTBUFFER, 1493 .index = -1, 1494 .data = &cpm_reg, 1495}; 1496 1497static int __init cpm_uart_console_init(void) 1498{ 1499 cpm_muram_init(); 1500 register_console(&cpm_scc_uart_console); 1501 return 0; 1502} 1503 1504console_initcall(cpm_uart_console_init); 1505 1506#define CPM_UART_CONSOLE &cpm_scc_uart_console 1507#else 1508#define CPM_UART_CONSOLE NULL 1509#endif 1510 1511static struct uart_driver cpm_reg = { 1512 .owner = THIS_MODULE, 1513 .driver_name = "ttyCPM", 1514 .dev_name = "ttyCPM", 1515 .major = SERIAL_CPM_MAJOR, 1516 .minor = SERIAL_CPM_MINOR, 1517 .cons = CPM_UART_CONSOLE, 1518 .nr = UART_NR, 1519}; 1520 1521static int probe_index; 1522 1523static int cpm_uart_probe(struct platform_device *ofdev) 1524{ 1525 int index = probe_index++; 1526 struct uart_cpm_port *pinfo = &cpm_uart_ports[index]; 1527 int ret; 1528 1529 pinfo->port.line = index; 1530 1531 if (index >= UART_NR) 1532 return -ENODEV; 1533 1534 platform_set_drvdata(ofdev, pinfo); 1535 1536 /* initialize the device pointer for the port */ 1537 pinfo->port.dev = &ofdev->dev; 1538 1539 pinfo->port.irq = irq_of_parse_and_map(ofdev->dev.of_node, 0); 1540 if (!pinfo->port.irq) 1541 return -EINVAL; 1542 1543 ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo); 1544 if (!ret) 1545 return uart_add_one_port(&cpm_reg, &pinfo->port); 1546 1547 irq_dispose_mapping(pinfo->port.irq); 1548 1549 return ret; 1550} 1551 1552static int cpm_uart_remove(struct platform_device *ofdev) 1553{ 1554 struct uart_cpm_port *pinfo = platform_get_drvdata(ofdev); 1555 1556 uart_remove_one_port(&cpm_reg, &pinfo->port); 1557 1558 return 0; 1559} 1560 1561static const struct of_device_id cpm_uart_match[] = { 1562 { 1563 .compatible = "fsl,cpm1-smc-uart", 1564 }, 1565 { 1566 .compatible = "fsl,cpm1-scc-uart", 1567 }, 1568 { 1569 .compatible = "fsl,cpm2-smc-uart", 1570 }, 1571 { 1572 .compatible = "fsl,cpm2-scc-uart", 1573 }, 1574 {} 1575}; 1576MODULE_DEVICE_TABLE(of, cpm_uart_match); 1577 1578static struct platform_driver cpm_uart_driver = { 1579 .driver = { 1580 .name = "cpm_uart", 1581 .of_match_table = cpm_uart_match, 1582 }, 1583 .probe = cpm_uart_probe, 1584 .remove = cpm_uart_remove, 1585 }; 1586 1587static int __init cpm_uart_init(void) 1588{ 1589 int ret = uart_register_driver(&cpm_reg); 1590 if (ret) 1591 return ret; 1592 1593 ret = platform_driver_register(&cpm_uart_driver); 1594 if (ret) 1595 uart_unregister_driver(&cpm_reg); 1596 1597 return ret; 1598} 1599 1600static void __exit cpm_uart_exit(void) 1601{ 1602 platform_driver_unregister(&cpm_uart_driver); 1603 uart_unregister_driver(&cpm_reg); 1604} 1605 1606module_init(cpm_uart_init); 1607module_exit(cpm_uart_exit); 1608 1609MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis"); 1610MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $"); 1611MODULE_LICENSE("GPL"); 1612MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR); 1613