1// SPDX-License-Identifier: GPL-2.0 2/* 3 * 8250-core based driver for the OMAP internal UART 4 * 5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 6 * 7 * Copyright (C) 2014 Sebastian Andrzej Siewior 8 * 9 */ 10 11#include <linux/clk.h> 12#include <linux/device.h> 13#include <linux/io.h> 14#include <linux/module.h> 15#include <linux/serial_8250.h> 16#include <linux/serial_reg.h> 17#include <linux/tty_flip.h> 18#include <linux/platform_device.h> 19#include <linux/slab.h> 20#include <linux/of.h> 21#include <linux/of_gpio.h> 22#include <linux/of_irq.h> 23#include <linux/delay.h> 24#include <linux/pm_runtime.h> 25#include <linux/console.h> 26#include <linux/pm_qos.h> 27#include <linux/pm_wakeirq.h> 28#include <linux/dma-mapping.h> 29#include <linux/sys_soc.h> 30 31#include "8250.h" 32 33#define DEFAULT_CLK_SPEED 48000000 34#define OMAP_UART_REGSHIFT 2 35 36#define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 37#define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 38#define OMAP_DMA_TX_KICK (1 << 2) 39/* 40 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 41 * The same errata is applicable to AM335x and DRA7x processors too. 42 */ 43#define UART_ERRATA_CLOCK_DISABLE (1 << 3) 44#define UART_HAS_EFR2 BIT(4) 45#define UART_HAS_RHR_IT_DIS BIT(5) 46#define UART_RX_TIMEOUT_QUIRK BIT(6) 47#define UART_HAS_NATIVE_RS485 BIT(7) 48 49#define OMAP_UART_FCR_RX_TRIG 6 50#define OMAP_UART_FCR_TX_TRIG 4 51 52/* SCR register bitmasks */ 53#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 54#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 55#define OMAP_UART_SCR_TX_EMPTY (1 << 3) 56#define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 57#define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 58#define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 59 60/* MVR register bitmasks */ 61#define OMAP_UART_MVR_SCHEME_SHIFT 30 62#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 63#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 64#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 65#define OMAP_UART_MVR_MAJ_MASK 0x700 66#define OMAP_UART_MVR_MAJ_SHIFT 8 67#define OMAP_UART_MVR_MIN_MASK 0x3f 68 69/* SYSC register bitmasks */ 70#define OMAP_UART_SYSC_SOFTRESET (1 << 1) 71 72/* SYSS register bitmasks */ 73#define OMAP_UART_SYSS_RESETDONE (1 << 0) 74 75#define UART_TI752_TLR_TX 0 76#define UART_TI752_TLR_RX 4 77 78#define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 79#define TRIGGER_FCR_MASK(x) (x & 3) 80 81/* Enable XON/XOFF flow control on output */ 82#define OMAP_UART_SW_TX 0x08 83/* Enable XON/XOFF flow control on input */ 84#define OMAP_UART_SW_RX 0x02 85 86#define OMAP_UART_WER_MOD_WKUP 0x7f 87#define OMAP_UART_TX_WAKEUP_EN (1 << 7) 88 89#define TX_TRIGGER 1 90#define RX_TRIGGER 48 91 92#define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 93#define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 94 95#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 96 97#define OMAP_UART_REV_46 0x0406 98#define OMAP_UART_REV_52 0x0502 99#define OMAP_UART_REV_63 0x0603 100 101/* Interrupt Enable Register 2 */ 102#define UART_OMAP_IER2 0x1B 103#define UART_OMAP_IER2_RHR_IT_DIS BIT(2) 104 105/* Mode Definition Register 3 */ 106#define UART_OMAP_MDR3 0x20 107#define UART_OMAP_MDR3_DIR_POL BIT(3) 108#define UART_OMAP_MDR3_DIR_EN BIT(4) 109 110/* Enhanced features register 2 */ 111#define UART_OMAP_EFR2 0x23 112#define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6) 113 114/* RX FIFO occupancy indicator */ 115#define UART_OMAP_RX_LVL 0x19 116 117struct omap8250_priv { 118 void __iomem *membase; 119 int line; 120 u8 habit; 121 u8 mdr1; 122 u8 mdr3; 123 u8 efr; 124 u8 scr; 125 u8 wer; 126 u8 xon; 127 u8 xoff; 128 u8 delayed_restore; 129 u16 quot; 130 131 u8 tx_trigger; 132 u8 rx_trigger; 133 bool is_suspending; 134 int wakeirq; 135 int wakeups_enabled; 136 u32 latency; 137 u32 calc_latency; 138 struct pm_qos_request pm_qos_request; 139 struct work_struct qos_work; 140 struct uart_8250_dma omap8250_dma; 141 spinlock_t rx_dma_lock; 142 bool rx_dma_broken; 143 bool throttled; 144}; 145 146struct omap8250_dma_params { 147 u32 rx_size; 148 u8 rx_trigger; 149 u8 tx_trigger; 150}; 151 152struct omap8250_platdata { 153 struct omap8250_dma_params *dma_params; 154 u8 habit; 155}; 156 157#ifdef CONFIG_SERIAL_8250_DMA 158static void omap_8250_rx_dma_flush(struct uart_8250_port *p); 159#else 160static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 161#endif 162 163static u32 uart_read(struct omap8250_priv *priv, u32 reg) 164{ 165 return readl(priv->membase + (reg << OMAP_UART_REGSHIFT)); 166} 167 168/* 169 * Called on runtime PM resume path from omap8250_restore_regs(), and 170 * omap8250_set_mctrl(). 171 */ 172static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 173{ 174 struct uart_8250_port *up = up_to_u8250p(port); 175 struct omap8250_priv *priv = up->port.private_data; 176 u8 lcr; 177 178 serial8250_do_set_mctrl(port, mctrl); 179 180 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { 181 /* 182 * Turn off autoRTS if RTS is lowered and restore autoRTS 183 * setting if RTS is raised 184 */ 185 lcr = serial_in(up, UART_LCR); 186 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 187 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 188 priv->efr |= UART_EFR_RTS; 189 else 190 priv->efr &= ~UART_EFR_RTS; 191 serial_out(up, UART_EFR, priv->efr); 192 serial_out(up, UART_LCR, lcr); 193 } 194} 195 196static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 197{ 198 int err; 199 200 err = pm_runtime_resume_and_get(port->dev); 201 if (err) 202 return; 203 204 __omap8250_set_mctrl(port, mctrl); 205 206 pm_runtime_mark_last_busy(port->dev); 207 pm_runtime_put_autosuspend(port->dev); 208} 209 210/* 211 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 212 * The access to uart register after MDR1 Access 213 * causes UART to corrupt data. 214 * 215 * Need a delay = 216 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 217 * give 10 times as much 218 */ 219static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 220 struct omap8250_priv *priv) 221{ 222 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 223 udelay(2); 224 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 225 UART_FCR_CLEAR_RCVR); 226} 227 228static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 229 struct omap8250_priv *priv) 230{ 231 unsigned int uartclk = port->uartclk; 232 unsigned int div_13, div_16; 233 unsigned int abs_d13, abs_d16; 234 235 /* 236 * Old custom speed handling. 237 */ 238 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 239 priv->quot = port->custom_divisor & UART_DIV_MAX; 240 /* 241 * I assume that nobody is using this. But hey, if somebody 242 * would like to specify the divisor _and_ the mode then the 243 * driver is ready and waiting for it. 244 */ 245 if (port->custom_divisor & (1 << 16)) 246 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 247 else 248 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 249 return; 250 } 251 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 252 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 253 254 if (!div_13) 255 div_13 = 1; 256 if (!div_16) 257 div_16 = 1; 258 259 abs_d13 = abs(baud - uartclk / 13 / div_13); 260 abs_d16 = abs(baud - uartclk / 16 / div_16); 261 262 if (abs_d13 >= abs_d16) { 263 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 264 priv->quot = div_16; 265 } else { 266 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 267 priv->quot = div_13; 268 } 269} 270 271static void omap8250_update_scr(struct uart_8250_port *up, 272 struct omap8250_priv *priv) 273{ 274 u8 old_scr; 275 276 old_scr = serial_in(up, UART_OMAP_SCR); 277 if (old_scr == priv->scr) 278 return; 279 280 /* 281 * The manual recommends not to enable the DMA mode selector in the SCR 282 * (instead of the FCR) register _and_ selecting the DMA mode as one 283 * register write because this may lead to malfunction. 284 */ 285 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 286 serial_out(up, UART_OMAP_SCR, 287 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 288 serial_out(up, UART_OMAP_SCR, priv->scr); 289} 290 291static void omap8250_update_mdr1(struct uart_8250_port *up, 292 struct omap8250_priv *priv) 293{ 294 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 295 omap_8250_mdr1_errataset(up, priv); 296 else 297 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 298} 299 300static void omap8250_restore_regs(struct uart_8250_port *up) 301{ 302 struct omap8250_priv *priv = up->port.private_data; 303 struct uart_8250_dma *dma = up->dma; 304 u8 mcr = serial8250_in_MCR(up); 305 306 /* Port locked to synchronize UART_IER access against the console. */ 307 lockdep_assert_held_once(&up->port.lock); 308 309 if (dma && dma->tx_running) { 310 /* 311 * TCSANOW requests the change to occur immediately however if 312 * we have a TX-DMA operation in progress then it has been 313 * observed that it might stall and never complete. Therefore we 314 * delay DMA completes to prevent this hang from happen. 315 */ 316 priv->delayed_restore = 1; 317 return; 318 } 319 320 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 321 serial_out(up, UART_EFR, UART_EFR_ECB); 322 323 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 324 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR); 325 serial_out(up, UART_FCR, up->fcr); 326 327 omap8250_update_scr(up, priv); 328 329 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 330 331 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 332 OMAP_UART_TCR_HALT(52)); 333 serial_out(up, UART_TI752_TLR, 334 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX | 335 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX); 336 337 serial_out(up, UART_LCR, 0); 338 339 /* drop TCR + TLR access, we setup XON/XOFF later */ 340 serial8250_out_MCR(up, mcr); 341 342 serial_out(up, UART_IER, up->ier); 343 344 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 345 serial_dl_write(up, priv->quot); 346 347 serial_out(up, UART_EFR, priv->efr); 348 349 /* Configure flow control */ 350 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 351 serial_out(up, UART_XON1, priv->xon); 352 serial_out(up, UART_XOFF1, priv->xoff); 353 354 serial_out(up, UART_LCR, up->lcr); 355 356 omap8250_update_mdr1(up, priv); 357 358 __omap8250_set_mctrl(&up->port, up->port.mctrl); 359 360 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 361 362 if (up->port.rs485.flags & SER_RS485_ENABLED && 363 up->port.rs485_config == serial8250_em485_config) 364 serial8250_em485_stop_tx(up); 365} 366 367/* 368 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 369 * some differences in how we want to handle flow control. 370 */ 371static void omap_8250_set_termios(struct uart_port *port, 372 struct ktermios *termios, 373 const struct ktermios *old) 374{ 375 struct uart_8250_port *up = up_to_u8250p(port); 376 struct omap8250_priv *priv = up->port.private_data; 377 unsigned char cval = 0; 378 unsigned int baud; 379 380 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); 381 382 if (termios->c_cflag & CSTOPB) 383 cval |= UART_LCR_STOP; 384 if (termios->c_cflag & PARENB) 385 cval |= UART_LCR_PARITY; 386 if (!(termios->c_cflag & PARODD)) 387 cval |= UART_LCR_EPAR; 388 if (termios->c_cflag & CMSPAR) 389 cval |= UART_LCR_SPAR; 390 391 /* 392 * Ask the core to calculate the divisor for us. 393 */ 394 baud = uart_get_baud_rate(port, termios, old, 395 port->uartclk / 16 / UART_DIV_MAX, 396 port->uartclk / 13); 397 omap_8250_get_divisor(port, baud, priv); 398 399 /* 400 * Ok, we're now changing the port state. Do it with 401 * interrupts disabled. 402 */ 403 pm_runtime_get_sync(port->dev); 404 spin_lock_irq(&port->lock); 405 406 /* 407 * Update the per-port timeout. 408 */ 409 uart_update_timeout(port, termios->c_cflag, baud); 410 411 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 412 if (termios->c_iflag & INPCK) 413 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 414 if (termios->c_iflag & (IGNBRK | PARMRK)) 415 up->port.read_status_mask |= UART_LSR_BI; 416 417 /* 418 * Characters to ignore 419 */ 420 up->port.ignore_status_mask = 0; 421 if (termios->c_iflag & IGNPAR) 422 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 423 if (termios->c_iflag & IGNBRK) { 424 up->port.ignore_status_mask |= UART_LSR_BI; 425 /* 426 * If we're ignoring parity and break indicators, 427 * ignore overruns too (for real raw support). 428 */ 429 if (termios->c_iflag & IGNPAR) 430 up->port.ignore_status_mask |= UART_LSR_OE; 431 } 432 433 /* 434 * ignore all characters if CREAD is not set 435 */ 436 if ((termios->c_cflag & CREAD) == 0) 437 up->port.ignore_status_mask |= UART_LSR_DR; 438 439 /* 440 * Modem status interrupts 441 */ 442 up->ier &= ~UART_IER_MSI; 443 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 444 up->ier |= UART_IER_MSI; 445 446 up->lcr = cval; 447 /* Up to here it was mostly serial8250_do_set_termios() */ 448 449 /* 450 * We enable TRIG_GRANU for RX and TX and additionally we set 451 * SCR_TX_EMPTY bit. The result is the following: 452 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 453 * - less than RX_TRIGGER number of bytes will also cause an interrupt 454 * once the UART decides that there no new bytes arriving. 455 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 456 * empty - the trigger level is ignored here. 457 * 458 * Once DMA is enabled: 459 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 460 * bytes in the TX FIFO. On each assert the DMA engine will move 461 * TX_TRIGGER bytes into the FIFO. 462 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 463 * the FIFO and move RX_TRIGGER bytes. 464 * This is because threshold and trigger values are the same. 465 */ 466 up->fcr = UART_FCR_ENABLE_FIFO; 467 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG; 468 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG; 469 470 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 471 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 472 473 if (up->dma) 474 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 475 OMAP_UART_SCR_DMAMODE_CTL; 476 477 priv->xon = termios->c_cc[VSTART]; 478 priv->xoff = termios->c_cc[VSTOP]; 479 480 priv->efr = 0; 481 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 482 483 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW && 484 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) && 485 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) { 486 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 487 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 488 priv->efr |= UART_EFR_CTS; 489 } else if (up->port.flags & UPF_SOFT_FLOW) { 490 /* 491 * OMAP rx s/w flow control is borked; the transmitter remains 492 * stuck off even if rx flow control is subsequently disabled 493 */ 494 495 /* 496 * IXOFF Flag: 497 * Enable XON/XOFF flow control on output. 498 * Transmit XON1, XOFF1 499 */ 500 if (termios->c_iflag & IXOFF) { 501 up->port.status |= UPSTAT_AUTOXOFF; 502 priv->efr |= OMAP_UART_SW_TX; 503 } 504 } 505 omap8250_restore_regs(up); 506 507 spin_unlock_irq(&up->port.lock); 508 pm_runtime_mark_last_busy(port->dev); 509 pm_runtime_put_autosuspend(port->dev); 510 511 /* calculate wakeup latency constraint */ 512 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 513 priv->latency = priv->calc_latency; 514 515 schedule_work(&priv->qos_work); 516 517 /* Don't rewrite B0 */ 518 if (tty_termios_baud_rate(termios)) 519 tty_termios_encode_baud_rate(termios, baud, baud); 520} 521 522/* same as 8250 except that we may have extra flow bits set in EFR */ 523static void omap_8250_pm(struct uart_port *port, unsigned int state, 524 unsigned int oldstate) 525{ 526 struct uart_8250_port *up = up_to_u8250p(port); 527 u8 efr; 528 529 pm_runtime_get_sync(port->dev); 530 531 /* Synchronize UART_IER access against the console. */ 532 spin_lock_irq(&port->lock); 533 534 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 535 efr = serial_in(up, UART_EFR); 536 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 537 serial_out(up, UART_LCR, 0); 538 539 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 540 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 541 serial_out(up, UART_EFR, efr); 542 serial_out(up, UART_LCR, 0); 543 544 spin_unlock_irq(&port->lock); 545 546 pm_runtime_mark_last_busy(port->dev); 547 pm_runtime_put_autosuspend(port->dev); 548} 549 550static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 551 struct omap8250_priv *priv) 552{ 553 static const struct soc_device_attribute k3_soc_devices[] = { 554 { .family = "AM65X", }, 555 { .family = "J721E", .revision = "SR1.0" }, 556 { /* sentinel */ } 557 }; 558 u32 mvr, scheme; 559 u16 revision, major, minor; 560 561 mvr = uart_read(priv, UART_OMAP_MVER); 562 563 /* Check revision register scheme */ 564 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 565 566 switch (scheme) { 567 case 0: /* Legacy Scheme: OMAP2/3 */ 568 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 569 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 570 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 571 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 572 break; 573 case 1: 574 /* New Scheme: OMAP4+ */ 575 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 576 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 577 OMAP_UART_MVR_MAJ_SHIFT; 578 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 579 break; 580 default: 581 dev_warn(up->port.dev, 582 "Unknown revision, defaulting to highest\n"); 583 /* highest possible revision */ 584 major = 0xff; 585 minor = 0xff; 586 } 587 /* normalize revision for the driver */ 588 revision = UART_BUILD_REVISION(major, minor); 589 590 switch (revision) { 591 case OMAP_UART_REV_46: 592 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 593 break; 594 case OMAP_UART_REV_52: 595 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 596 OMAP_UART_WER_HAS_TX_WAKEUP; 597 break; 598 case OMAP_UART_REV_63: 599 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 600 OMAP_UART_WER_HAS_TX_WAKEUP; 601 break; 602 default: 603 break; 604 } 605 606 /* 607 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't 608 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag 609 * to enable errata workaround. 610 */ 611 if (soc_device_match(k3_soc_devices)) 612 priv->habit &= ~UART_HAS_RHR_IT_DIS; 613} 614 615static void omap8250_uart_qos_work(struct work_struct *work) 616{ 617 struct omap8250_priv *priv; 618 619 priv = container_of(work, struct omap8250_priv, qos_work); 620 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency); 621} 622 623#ifdef CONFIG_SERIAL_8250_DMA 624static int omap_8250_dma_handle_irq(struct uart_port *port); 625#endif 626 627static irqreturn_t omap8250_irq(int irq, void *dev_id) 628{ 629 struct omap8250_priv *priv = dev_id; 630 struct uart_8250_port *up = serial8250_get_port(priv->line); 631 struct uart_port *port = &up->port; 632 unsigned int iir, lsr; 633 int ret; 634 635#ifdef CONFIG_SERIAL_8250_DMA 636 if (up->dma) { 637 ret = omap_8250_dma_handle_irq(port); 638 return IRQ_RETVAL(ret); 639 } 640#endif 641 642 serial8250_rpm_get(up); 643 lsr = serial_port_in(port, UART_LSR); 644 iir = serial_port_in(port, UART_IIR); 645 ret = serial8250_handle_irq(port, iir); 646 647 /* 648 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after 649 * FIFO has been drained, in which case a dummy read of RX FIFO 650 * is required to clear RX TIMEOUT condition. 651 */ 652 if (priv->habit & UART_RX_TIMEOUT_QUIRK && 653 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT && 654 serial_port_in(port, UART_OMAP_RX_LVL) == 0) { 655 serial_port_in(port, UART_RX); 656 } 657 658 /* Stop processing interrupts on input overrun */ 659 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) { 660 unsigned long delay; 661 662 /* Synchronize UART_IER access against the console. */ 663 spin_lock(&port->lock); 664 up->ier = port->serial_in(port, UART_IER); 665 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { 666 port->ops->stop_rx(port); 667 } else { 668 /* Keep restarting the timer until 669 * the input overrun subsides. 670 */ 671 cancel_delayed_work(&up->overrun_backoff); 672 } 673 spin_unlock(&port->lock); 674 675 delay = msecs_to_jiffies(up->overrun_backoff_time_ms); 676 schedule_delayed_work(&up->overrun_backoff, delay); 677 } 678 679 serial8250_rpm_put(up); 680 681 return IRQ_RETVAL(ret); 682} 683 684static int omap_8250_startup(struct uart_port *port) 685{ 686 struct uart_8250_port *up = up_to_u8250p(port); 687 struct omap8250_priv *priv = port->private_data; 688 struct uart_8250_dma *dma = &priv->omap8250_dma; 689 int ret; 690 691 if (priv->wakeirq) { 692 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 693 if (ret) 694 return ret; 695 } 696 697 pm_runtime_get_sync(port->dev); 698 699 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 700 701 serial_out(up, UART_LCR, UART_LCR_WLEN8); 702 703 up->lsr_saved_flags = 0; 704 up->msr_saved_flags = 0; 705 706 /* Disable DMA for console UART */ 707 if (dma->fn && !uart_console(port)) { 708 up->dma = &priv->omap8250_dma; 709 ret = serial8250_request_dma(up); 710 if (ret) { 711 dev_warn_ratelimited(port->dev, 712 "failed to request DMA\n"); 713 up->dma = NULL; 714 } 715 } else { 716 up->dma = NULL; 717 } 718 719 /* Synchronize UART_IER access against the console. */ 720 spin_lock_irq(&port->lock); 721 up->ier = UART_IER_RLSI | UART_IER_RDI; 722 serial_out(up, UART_IER, up->ier); 723 spin_unlock_irq(&port->lock); 724 725#ifdef CONFIG_PM 726 up->capabilities |= UART_CAP_RPM; 727#endif 728 729 /* Enable module level wake up */ 730 priv->wer = OMAP_UART_WER_MOD_WKUP; 731 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 732 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 733 serial_out(up, UART_OMAP_WER, priv->wer); 734 735 if (up->dma && !(priv->habit & UART_HAS_EFR2)) { 736 spin_lock_irq(&port->lock); 737 up->dma->rx_dma(up); 738 spin_unlock_irq(&port->lock); 739 } 740 741 enable_irq(up->port.irq); 742 743 pm_runtime_mark_last_busy(port->dev); 744 pm_runtime_put_autosuspend(port->dev); 745 return 0; 746} 747 748static void omap_8250_shutdown(struct uart_port *port) 749{ 750 struct uart_8250_port *up = up_to_u8250p(port); 751 struct omap8250_priv *priv = port->private_data; 752 753 flush_work(&priv->qos_work); 754 if (up->dma) 755 omap_8250_rx_dma_flush(up); 756 757 pm_runtime_get_sync(port->dev); 758 759 serial_out(up, UART_OMAP_WER, 0); 760 if (priv->habit & UART_HAS_EFR2) 761 serial_out(up, UART_OMAP_EFR2, 0x0); 762 763 /* Synchronize UART_IER access against the console. */ 764 spin_lock_irq(&port->lock); 765 up->ier = 0; 766 serial_out(up, UART_IER, 0); 767 spin_unlock_irq(&port->lock); 768 disable_irq_nosync(up->port.irq); 769 dev_pm_clear_wake_irq(port->dev); 770 771 serial8250_release_dma(up); 772 up->dma = NULL; 773 774 /* 775 * Disable break condition and FIFOs 776 */ 777 if (up->lcr & UART_LCR_SBC) 778 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 779 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 780 781 pm_runtime_mark_last_busy(port->dev); 782 pm_runtime_put_autosuspend(port->dev); 783} 784 785static void omap_8250_throttle(struct uart_port *port) 786{ 787 struct omap8250_priv *priv = port->private_data; 788 unsigned long flags; 789 790 pm_runtime_get_sync(port->dev); 791 792 spin_lock_irqsave(&port->lock, flags); 793 port->ops->stop_rx(port); 794 priv->throttled = true; 795 spin_unlock_irqrestore(&port->lock, flags); 796 797 pm_runtime_mark_last_busy(port->dev); 798 pm_runtime_put_autosuspend(port->dev); 799} 800 801static void omap_8250_unthrottle(struct uart_port *port) 802{ 803 struct omap8250_priv *priv = port->private_data; 804 struct uart_8250_port *up = up_to_u8250p(port); 805 unsigned long flags; 806 807 pm_runtime_get_sync(port->dev); 808 809 /* Synchronize UART_IER access against the console. */ 810 spin_lock_irqsave(&port->lock, flags); 811 priv->throttled = false; 812 if (up->dma) 813 up->dma->rx_dma(up); 814 up->ier |= UART_IER_RLSI | UART_IER_RDI; 815 port->read_status_mask |= UART_LSR_DR; 816 serial_out(up, UART_IER, up->ier); 817 spin_unlock_irqrestore(&port->lock, flags); 818 819 pm_runtime_mark_last_busy(port->dev); 820 pm_runtime_put_autosuspend(port->dev); 821} 822 823static int omap8250_rs485_config(struct uart_port *port, 824 struct ktermios *termios, 825 struct serial_rs485 *rs485) 826{ 827 struct omap8250_priv *priv = port->private_data; 828 struct uart_8250_port *up = up_to_u8250p(port); 829 u32 fixed_delay_rts_before_send = 0; 830 u32 fixed_delay_rts_after_send = 0; 831 unsigned int baud; 832 833 /* 834 * There is a fixed delay of 3 bit clock cycles after the TX shift 835 * register is going empty to allow time for the stop bit to transition 836 * through the transceiver before direction is changed to receive. 837 * 838 * Additionally there appears to be a 1 bit clock delay between writing 839 * to the THR register and transmission of the start bit, per page 8783 840 * of the AM65 TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf 841 */ 842 if (priv->quot) { 843 if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE) 844 baud = port->uartclk / (16 * priv->quot); 845 else 846 baud = port->uartclk / (13 * priv->quot); 847 848 fixed_delay_rts_after_send = 3 * MSEC_PER_SEC / baud; 849 fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud; 850 } 851 852 /* 853 * Fall back to RS485 software emulation if the UART is missing 854 * hardware support, if the device tree specifies an mctrl_gpio 855 * (indicates that RTS is unavailable due to a pinmux conflict) 856 * or if the requested delays exceed the fixed hardware delays. 857 */ 858 if (!(priv->habit & UART_HAS_NATIVE_RS485) || 859 mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) || 860 rs485->delay_rts_after_send > fixed_delay_rts_after_send || 861 rs485->delay_rts_before_send > fixed_delay_rts_before_send) { 862 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 863 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 864 865 port->rs485_config = serial8250_em485_config; 866 return serial8250_em485_config(port, termios, rs485); 867 } 868 869 rs485->delay_rts_after_send = fixed_delay_rts_after_send; 870 rs485->delay_rts_before_send = fixed_delay_rts_before_send; 871 872 if (rs485->flags & SER_RS485_ENABLED) 873 priv->mdr3 |= UART_OMAP_MDR3_DIR_EN; 874 else 875 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 876 877 /* 878 * Retain same polarity semantics as RS485 software emulation, 879 * i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send. 880 */ 881 if (rs485->flags & SER_RS485_RTS_ON_SEND) 882 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL; 883 else 884 priv->mdr3 |= UART_OMAP_MDR3_DIR_POL; 885 886 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 887 888 return 0; 889} 890 891#ifdef CONFIG_SERIAL_8250_DMA 892static int omap_8250_rx_dma(struct uart_8250_port *p); 893 894/* Must be called while priv->rx_dma_lock is held */ 895static void __dma_rx_do_complete(struct uart_8250_port *p) 896{ 897 struct uart_8250_dma *dma = p->dma; 898 struct tty_port *tty_port = &p->port.state->port; 899 struct omap8250_priv *priv = p->port.private_data; 900 struct dma_chan *rxchan = dma->rxchan; 901 dma_cookie_t cookie; 902 struct dma_tx_state state; 903 int count; 904 int ret; 905 u32 reg; 906 907 if (!dma->rx_running) 908 goto out; 909 910 cookie = dma->rx_cookie; 911 dma->rx_running = 0; 912 913 /* Re-enable RX FIFO interrupt now that transfer is complete */ 914 if (priv->habit & UART_HAS_RHR_IT_DIS) { 915 reg = serial_in(p, UART_OMAP_IER2); 916 reg &= ~UART_OMAP_IER2_RHR_IT_DIS; 917 serial_out(p, UART_OMAP_IER2, reg); 918 } 919 920 dmaengine_tx_status(rxchan, cookie, &state); 921 922 count = dma->rx_size - state.residue + state.in_flight_bytes; 923 if (count < dma->rx_size) { 924 dmaengine_terminate_async(rxchan); 925 926 /* 927 * Poll for teardown to complete which guarantees in 928 * flight data is drained. 929 */ 930 if (state.in_flight_bytes) { 931 int poll_count = 25; 932 933 while (dmaengine_tx_status(rxchan, cookie, NULL) && 934 poll_count--) 935 cpu_relax(); 936 937 if (poll_count == -1) 938 dev_err(p->port.dev, "teardown incomplete\n"); 939 } 940 } 941 if (!count) 942 goto out; 943 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 944 945 p->port.icount.rx += ret; 946 p->port.icount.buf_overrun += count - ret; 947out: 948 949 tty_flip_buffer_push(tty_port); 950} 951 952static void __dma_rx_complete(void *param) 953{ 954 struct uart_8250_port *p = param; 955 struct omap8250_priv *priv = p->port.private_data; 956 struct uart_8250_dma *dma = p->dma; 957 struct dma_tx_state state; 958 unsigned long flags; 959 960 /* Synchronize UART_IER access against the console. */ 961 spin_lock_irqsave(&p->port.lock, flags); 962 963 /* 964 * If the tx status is not DMA_COMPLETE, then this is a delayed 965 * completion callback. A previous RX timeout flush would have 966 * already pushed the data, so exit. 967 */ 968 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != 969 DMA_COMPLETE) { 970 spin_unlock_irqrestore(&p->port.lock, flags); 971 return; 972 } 973 __dma_rx_do_complete(p); 974 if (!priv->throttled) { 975 p->ier |= UART_IER_RLSI | UART_IER_RDI; 976 serial_out(p, UART_IER, p->ier); 977 if (!(priv->habit & UART_HAS_EFR2)) 978 omap_8250_rx_dma(p); 979 } 980 981 spin_unlock_irqrestore(&p->port.lock, flags); 982} 983 984static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 985{ 986 struct omap8250_priv *priv = p->port.private_data; 987 struct uart_8250_dma *dma = p->dma; 988 struct dma_tx_state state; 989 unsigned long flags; 990 int ret; 991 992 spin_lock_irqsave(&priv->rx_dma_lock, flags); 993 994 if (!dma->rx_running) { 995 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 996 return; 997 } 998 999 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 1000 if (ret == DMA_IN_PROGRESS) { 1001 ret = dmaengine_pause(dma->rxchan); 1002 if (WARN_ON_ONCE(ret)) 1003 priv->rx_dma_broken = true; 1004 } 1005 __dma_rx_do_complete(p); 1006 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1007} 1008 1009static int omap_8250_rx_dma(struct uart_8250_port *p) 1010{ 1011 struct omap8250_priv *priv = p->port.private_data; 1012 struct uart_8250_dma *dma = p->dma; 1013 int err = 0; 1014 struct dma_async_tx_descriptor *desc; 1015 unsigned long flags; 1016 u32 reg; 1017 1018 /* Port locked to synchronize UART_IER access against the console. */ 1019 lockdep_assert_held_once(&p->port.lock); 1020 1021 if (priv->rx_dma_broken) 1022 return -EINVAL; 1023 1024 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1025 1026 if (dma->rx_running) { 1027 enum dma_status state; 1028 1029 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL); 1030 if (state == DMA_COMPLETE) { 1031 /* 1032 * Disable RX interrupts to allow RX DMA completion 1033 * callback to run. 1034 */ 1035 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1036 serial_out(p, UART_IER, p->ier); 1037 } 1038 goto out; 1039 } 1040 1041 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 1042 dma->rx_size, DMA_DEV_TO_MEM, 1043 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1044 if (!desc) { 1045 err = -EBUSY; 1046 goto out; 1047 } 1048 1049 dma->rx_running = 1; 1050 desc->callback = __dma_rx_complete; 1051 desc->callback_param = p; 1052 1053 dma->rx_cookie = dmaengine_submit(desc); 1054 1055 /* 1056 * Disable RX FIFO interrupt while RX DMA is enabled, else 1057 * spurious interrupt may be raised when data is in the RX FIFO 1058 * but is yet to be drained by DMA. 1059 */ 1060 if (priv->habit & UART_HAS_RHR_IT_DIS) { 1061 reg = serial_in(p, UART_OMAP_IER2); 1062 reg |= UART_OMAP_IER2_RHR_IT_DIS; 1063 serial_out(p, UART_OMAP_IER2, reg); 1064 } 1065 1066 dma_async_issue_pending(dma->rxchan); 1067out: 1068 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1069 return err; 1070} 1071 1072static int omap_8250_tx_dma(struct uart_8250_port *p); 1073 1074static void omap_8250_dma_tx_complete(void *param) 1075{ 1076 struct uart_8250_port *p = param; 1077 struct uart_8250_dma *dma = p->dma; 1078 struct circ_buf *xmit = &p->port.state->xmit; 1079 unsigned long flags; 1080 bool en_thri = false; 1081 struct omap8250_priv *priv = p->port.private_data; 1082 1083 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 1084 UART_XMIT_SIZE, DMA_TO_DEVICE); 1085 1086 spin_lock_irqsave(&p->port.lock, flags); 1087 1088 dma->tx_running = 0; 1089 1090 uart_xmit_advance(&p->port, dma->tx_size); 1091 1092 if (priv->delayed_restore) { 1093 priv->delayed_restore = 0; 1094 omap8250_restore_regs(p); 1095 } 1096 1097 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1098 uart_write_wakeup(&p->port); 1099 1100 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) { 1101 int ret; 1102 1103 ret = omap_8250_tx_dma(p); 1104 if (ret) 1105 en_thri = true; 1106 } else if (p->capabilities & UART_CAP_RPM) { 1107 en_thri = true; 1108 } 1109 1110 if (en_thri) { 1111 dma->tx_err = 1; 1112 serial8250_set_THRI(p); 1113 } 1114 1115 spin_unlock_irqrestore(&p->port.lock, flags); 1116} 1117 1118static int omap_8250_tx_dma(struct uart_8250_port *p) 1119{ 1120 struct uart_8250_dma *dma = p->dma; 1121 struct omap8250_priv *priv = p->port.private_data; 1122 struct circ_buf *xmit = &p->port.state->xmit; 1123 struct dma_async_tx_descriptor *desc; 1124 unsigned int skip_byte = 0; 1125 int ret; 1126 1127 if (dma->tx_running) 1128 return 0; 1129 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) { 1130 1131 /* 1132 * Even if no data, we need to return an error for the two cases 1133 * below so serial8250_tx_chars() is invoked and properly clears 1134 * THRI and/or runtime suspend. 1135 */ 1136 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 1137 ret = -EBUSY; 1138 goto err; 1139 } 1140 serial8250_clear_THRI(p); 1141 return 0; 1142 } 1143 1144 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 1145 if (priv->habit & OMAP_DMA_TX_KICK) { 1146 u8 tx_lvl; 1147 1148 /* 1149 * We need to put the first byte into the FIFO in order to start 1150 * the DMA transfer. For transfers smaller than four bytes we 1151 * don't bother doing DMA at all. It seem not matter if there 1152 * are still bytes in the FIFO from the last transfer (in case 1153 * we got here directly from omap_8250_dma_tx_complete()). Bytes 1154 * leaving the FIFO seem not to trigger the DMA transfer. It is 1155 * really the byte that we put into the FIFO. 1156 * If the FIFO is already full then we most likely got here from 1157 * omap_8250_dma_tx_complete(). And this means the DMA engine 1158 * just completed its work. We don't have to wait the complete 1159 * 86us at 115200,8n1 but around 60us (not to mention lower 1160 * baudrates). So in that case we take the interrupt and try 1161 * again with an empty FIFO. 1162 */ 1163 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 1164 if (tx_lvl == p->tx_loadsz) { 1165 ret = -EBUSY; 1166 goto err; 1167 } 1168 if (dma->tx_size < 4) { 1169 ret = -EINVAL; 1170 goto err; 1171 } 1172 skip_byte = 1; 1173 } 1174 1175 desc = dmaengine_prep_slave_single(dma->txchan, 1176 dma->tx_addr + xmit->tail + skip_byte, 1177 dma->tx_size - skip_byte, DMA_MEM_TO_DEV, 1178 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1179 if (!desc) { 1180 ret = -EBUSY; 1181 goto err; 1182 } 1183 1184 dma->tx_running = 1; 1185 1186 desc->callback = omap_8250_dma_tx_complete; 1187 desc->callback_param = p; 1188 1189 dma->tx_cookie = dmaengine_submit(desc); 1190 1191 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 1192 UART_XMIT_SIZE, DMA_TO_DEVICE); 1193 1194 dma_async_issue_pending(dma->txchan); 1195 if (dma->tx_err) 1196 dma->tx_err = 0; 1197 1198 serial8250_clear_THRI(p); 1199 if (skip_byte) 1200 serial_out(p, UART_TX, xmit->buf[xmit->tail]); 1201 return 0; 1202err: 1203 dma->tx_err = 1; 1204 return ret; 1205} 1206 1207static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1208{ 1209 switch (iir & 0x3f) { 1210 case UART_IIR_RLSI: 1211 case UART_IIR_RX_TIMEOUT: 1212 case UART_IIR_RDI: 1213 omap_8250_rx_dma_flush(up); 1214 return true; 1215 } 1216 return omap_8250_rx_dma(up); 1217} 1218 1219static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status) 1220{ 1221 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1222 (iir & UART_IIR_RDI)) { 1223 if (handle_rx_dma(up, iir)) { 1224 status = serial8250_rx_chars(up, status); 1225 omap_8250_rx_dma(up); 1226 } 1227 } 1228 1229 return status; 1230} 1231 1232static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, 1233 u16 status) 1234{ 1235 /* Port locked to synchronize UART_IER access against the console. */ 1236 lockdep_assert_held_once(&up->port.lock); 1237 1238 /* 1239 * Queue a new transfer if FIFO has data. 1240 */ 1241 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1242 (up->ier & UART_IER_RDI)) { 1243 omap_8250_rx_dma(up); 1244 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 1245 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) { 1246 /* 1247 * Disable RX timeout, read IIR to clear 1248 * current timeout condition, clear EFR2 to 1249 * periodic timeouts, re-enable interrupts. 1250 */ 1251 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1252 serial_out(up, UART_IER, up->ier); 1253 omap_8250_rx_dma_flush(up); 1254 serial_in(up, UART_IIR); 1255 serial_out(up, UART_OMAP_EFR2, 0x0); 1256 up->ier |= UART_IER_RLSI | UART_IER_RDI; 1257 serial_out(up, UART_IER, up->ier); 1258 } 1259} 1260 1261/* 1262 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1263 * hoook for RX/TX and need different logic for them in the ISR. Therefore we 1264 * use the default routine in the non-DMA case and this one for with DMA. 1265 */ 1266static int omap_8250_dma_handle_irq(struct uart_port *port) 1267{ 1268 struct uart_8250_port *up = up_to_u8250p(port); 1269 struct omap8250_priv *priv = up->port.private_data; 1270 u16 status; 1271 u8 iir; 1272 1273 serial8250_rpm_get(up); 1274 1275 iir = serial_port_in(port, UART_IIR); 1276 if (iir & UART_IIR_NO_INT) { 1277 serial8250_rpm_put(up); 1278 return IRQ_HANDLED; 1279 } 1280 1281 spin_lock(&port->lock); 1282 1283 status = serial_port_in(port, UART_LSR); 1284 1285 if ((iir & 0x3f) != UART_IIR_THRI) { 1286 if (priv->habit & UART_HAS_EFR2) 1287 am654_8250_handle_rx_dma(up, iir, status); 1288 else 1289 status = omap_8250_handle_rx_dma(up, iir, status); 1290 } 1291 1292 serial8250_modem_status(up); 1293 if (status & UART_LSR_THRE && up->dma->tx_err) { 1294 if (uart_tx_stopped(&up->port) || 1295 uart_circ_empty(&up->port.state->xmit)) { 1296 up->dma->tx_err = 0; 1297 serial8250_tx_chars(up); 1298 } else { 1299 /* 1300 * try again due to an earlier failer which 1301 * might have been resolved by now. 1302 */ 1303 if (omap_8250_tx_dma(up)) 1304 serial8250_tx_chars(up); 1305 } 1306 } 1307 1308 uart_unlock_and_check_sysrq(port); 1309 1310 serial8250_rpm_put(up); 1311 return 1; 1312} 1313 1314static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1315{ 1316 return false; 1317} 1318 1319#else 1320 1321static inline int omap_8250_rx_dma(struct uart_8250_port *p) 1322{ 1323 return -EINVAL; 1324} 1325#endif 1326 1327static int omap8250_no_handle_irq(struct uart_port *port) 1328{ 1329 /* IRQ has not been requested but handling irq? */ 1330 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1331 return 0; 1332} 1333 1334static struct omap8250_dma_params am654_dma = { 1335 .rx_size = SZ_2K, 1336 .rx_trigger = 1, 1337 .tx_trigger = TX_TRIGGER, 1338}; 1339 1340static struct omap8250_dma_params am33xx_dma = { 1341 .rx_size = RX_TRIGGER, 1342 .rx_trigger = RX_TRIGGER, 1343 .tx_trigger = TX_TRIGGER, 1344}; 1345 1346static struct omap8250_platdata am654_platdata = { 1347 .dma_params = &am654_dma, 1348 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS | 1349 UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485, 1350}; 1351 1352static struct omap8250_platdata am33xx_platdata = { 1353 .dma_params = &am33xx_dma, 1354 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE, 1355}; 1356 1357static struct omap8250_platdata omap4_platdata = { 1358 .dma_params = &am33xx_dma, 1359 .habit = UART_ERRATA_CLOCK_DISABLE, 1360}; 1361 1362static const struct of_device_id omap8250_dt_ids[] = { 1363 { .compatible = "ti,am654-uart", .data = &am654_platdata, }, 1364 { .compatible = "ti,omap2-uart" }, 1365 { .compatible = "ti,omap3-uart" }, 1366 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, }, 1367 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, }, 1368 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, }, 1369 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, }, 1370 {}, 1371}; 1372MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1373 1374static int omap8250_probe(struct platform_device *pdev) 1375{ 1376 struct device_node *np = pdev->dev.of_node; 1377 struct omap8250_priv *priv; 1378 const struct omap8250_platdata *pdata; 1379 struct uart_8250_port up; 1380 struct resource *regs; 1381 void __iomem *membase; 1382 int irq, ret; 1383 1384 irq = platform_get_irq(pdev, 0); 1385 if (irq < 0) 1386 return irq; 1387 1388 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1389 if (!regs) { 1390 dev_err(&pdev->dev, "missing registers\n"); 1391 return -EINVAL; 1392 } 1393 1394 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1395 if (!priv) 1396 return -ENOMEM; 1397 1398 membase = devm_ioremap(&pdev->dev, regs->start, 1399 resource_size(regs)); 1400 if (!membase) 1401 return -ENODEV; 1402 1403 memset(&up, 0, sizeof(up)); 1404 up.port.dev = &pdev->dev; 1405 up.port.mapbase = regs->start; 1406 up.port.membase = membase; 1407 up.port.irq = irq; 1408 /* 1409 * It claims to be 16C750 compatible however it is a little different. 1410 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1411 * have) is enabled via EFR instead of MCR. The type is set here 8250 1412 * just to get things going. UNKNOWN does not work for a few reasons and 1413 * we don't need our own type since we don't use 8250's set_termios() 1414 * or pm callback. 1415 */ 1416 up.port.type = PORT_8250; 1417 up.port.iotype = UPIO_MEM; 1418 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | 1419 UPF_HARD_FLOW; 1420 up.port.private_data = priv; 1421 1422 up.port.regshift = OMAP_UART_REGSHIFT; 1423 up.port.fifosize = 64; 1424 up.tx_loadsz = 64; 1425 up.capabilities = UART_CAP_FIFO; 1426#ifdef CONFIG_PM 1427 /* 1428 * Runtime PM is mostly transparent. However to do it right we need to a 1429 * TX empty interrupt before we can put the device to auto idle. So if 1430 * PM is not enabled we don't add that flag and can spare that one extra 1431 * interrupt in the TX path. 1432 */ 1433 up.capabilities |= UART_CAP_RPM; 1434#endif 1435 up.port.set_termios = omap_8250_set_termios; 1436 up.port.set_mctrl = omap8250_set_mctrl; 1437 up.port.pm = omap_8250_pm; 1438 up.port.startup = omap_8250_startup; 1439 up.port.shutdown = omap_8250_shutdown; 1440 up.port.throttle = omap_8250_throttle; 1441 up.port.unthrottle = omap_8250_unthrottle; 1442 up.port.rs485_config = omap8250_rs485_config; 1443 /* same rs485_supported for software emulation and native RS485 */ 1444 up.port.rs485_supported = serial8250_em485_supported; 1445 up.rs485_start_tx = serial8250_em485_start_tx; 1446 up.rs485_stop_tx = serial8250_em485_stop_tx; 1447 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 1448 1449 ret = of_alias_get_id(np, "serial"); 1450 if (ret < 0) { 1451 dev_err(&pdev->dev, "failed to get alias\n"); 1452 return ret; 1453 } 1454 up.port.line = ret; 1455 1456 if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) { 1457 struct clk *clk; 1458 1459 clk = devm_clk_get(&pdev->dev, NULL); 1460 if (IS_ERR(clk)) { 1461 if (PTR_ERR(clk) == -EPROBE_DEFER) 1462 return -EPROBE_DEFER; 1463 } else { 1464 up.port.uartclk = clk_get_rate(clk); 1465 } 1466 } 1467 1468 if (of_property_read_u32(np, "overrun-throttle-ms", 1469 &up.overrun_backoff_time_ms) != 0) 1470 up.overrun_backoff_time_ms = 0; 1471 1472 pdata = of_device_get_match_data(&pdev->dev); 1473 if (pdata) 1474 priv->habit |= pdata->habit; 1475 1476 if (!up.port.uartclk) { 1477 up.port.uartclk = DEFAULT_CLK_SPEED; 1478 dev_warn(&pdev->dev, 1479 "No clock speed specified: using default: %d\n", 1480 DEFAULT_CLK_SPEED); 1481 } 1482 1483 priv->membase = membase; 1484 priv->line = -ENODEV; 1485 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1486 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1487 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency); 1488 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1489 1490 spin_lock_init(&priv->rx_dma_lock); 1491 1492 platform_set_drvdata(pdev, priv); 1493 1494 device_init_wakeup(&pdev->dev, true); 1495 pm_runtime_enable(&pdev->dev); 1496 pm_runtime_use_autosuspend(&pdev->dev); 1497 1498 /* 1499 * Disable runtime PM until autosuspend delay unless specifically 1500 * enabled by the user via sysfs. This is the historic way to 1501 * prevent an unsafe default policy with lossy characters on wake-up. 1502 * For serdev devices this is not needed, the policy can be managed by 1503 * the serdev driver. 1504 */ 1505 if (!of_get_available_child_count(pdev->dev.of_node)) 1506 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1507 1508 pm_runtime_irq_safe(&pdev->dev); 1509 1510 pm_runtime_get_sync(&pdev->dev); 1511 1512 omap_serial_fill_features_erratas(&up, priv); 1513 up.port.handle_irq = omap8250_no_handle_irq; 1514 priv->rx_trigger = RX_TRIGGER; 1515 priv->tx_trigger = TX_TRIGGER; 1516#ifdef CONFIG_SERIAL_8250_DMA 1517 /* 1518 * Oh DMA support. If there are no DMA properties in the DT then 1519 * we will fall back to a generic DMA channel which does not 1520 * really work here. To ensure that we do not get a generic DMA 1521 * channel assigned, we have the the_no_dma_filter_fn() here. 1522 * To avoid "failed to request DMA" messages we check for DMA 1523 * properties in DT. 1524 */ 1525 ret = of_property_count_strings(np, "dma-names"); 1526 if (ret == 2) { 1527 struct omap8250_dma_params *dma_params = NULL; 1528 struct uart_8250_dma *dma = &priv->omap8250_dma; 1529 1530 dma->fn = the_no_dma_filter_fn; 1531 dma->tx_dma = omap_8250_tx_dma; 1532 dma->rx_dma = omap_8250_rx_dma; 1533 if (pdata) 1534 dma_params = pdata->dma_params; 1535 1536 if (dma_params) { 1537 dma->rx_size = dma_params->rx_size; 1538 dma->rxconf.src_maxburst = dma_params->rx_trigger; 1539 dma->txconf.dst_maxburst = dma_params->tx_trigger; 1540 priv->rx_trigger = dma_params->rx_trigger; 1541 priv->tx_trigger = dma_params->tx_trigger; 1542 } else { 1543 dma->rx_size = RX_TRIGGER; 1544 dma->rxconf.src_maxburst = RX_TRIGGER; 1545 dma->txconf.dst_maxburst = TX_TRIGGER; 1546 } 1547 } 1548#endif 1549 1550 irq_set_status_flags(irq, IRQ_NOAUTOEN); 1551 ret = devm_request_irq(&pdev->dev, irq, omap8250_irq, 0, 1552 dev_name(&pdev->dev), priv); 1553 if (ret < 0) 1554 return ret; 1555 1556 priv->wakeirq = irq_of_parse_and_map(np, 1); 1557 1558 ret = serial8250_register_8250_port(&up); 1559 if (ret < 0) { 1560 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1561 goto err; 1562 } 1563 priv->line = ret; 1564 pm_runtime_mark_last_busy(&pdev->dev); 1565 pm_runtime_put_autosuspend(&pdev->dev); 1566 return 0; 1567err: 1568 pm_runtime_dont_use_autosuspend(&pdev->dev); 1569 pm_runtime_put_sync(&pdev->dev); 1570 flush_work(&priv->qos_work); 1571 pm_runtime_disable(&pdev->dev); 1572 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1573 return ret; 1574} 1575 1576static int omap8250_remove(struct platform_device *pdev) 1577{ 1578 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1579 struct uart_8250_port *up; 1580 int err; 1581 1582 err = pm_runtime_resume_and_get(&pdev->dev); 1583 if (err) 1584 dev_err(&pdev->dev, "Failed to resume hardware\n"); 1585 1586 up = serial8250_get_port(priv->line); 1587 omap_8250_shutdown(&up->port); 1588 serial8250_unregister_port(priv->line); 1589 priv->line = -ENODEV; 1590 pm_runtime_dont_use_autosuspend(&pdev->dev); 1591 pm_runtime_put_sync(&pdev->dev); 1592 flush_work(&priv->qos_work); 1593 pm_runtime_disable(&pdev->dev); 1594 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1595 device_init_wakeup(&pdev->dev, false); 1596 return 0; 1597} 1598 1599static int omap8250_prepare(struct device *dev) 1600{ 1601 struct omap8250_priv *priv = dev_get_drvdata(dev); 1602 1603 if (!priv) 1604 return 0; 1605 priv->is_suspending = true; 1606 return 0; 1607} 1608 1609static void omap8250_complete(struct device *dev) 1610{ 1611 struct omap8250_priv *priv = dev_get_drvdata(dev); 1612 1613 if (!priv) 1614 return; 1615 priv->is_suspending = false; 1616} 1617 1618static int omap8250_suspend(struct device *dev) 1619{ 1620 struct omap8250_priv *priv = dev_get_drvdata(dev); 1621 struct uart_8250_port *up = serial8250_get_port(priv->line); 1622 int err = 0; 1623 1624 serial8250_suspend_port(priv->line); 1625 1626 err = pm_runtime_resume_and_get(dev); 1627 if (err) 1628 return err; 1629 if (!device_may_wakeup(dev)) 1630 priv->wer = 0; 1631 serial_out(up, UART_OMAP_WER, priv->wer); 1632 if (uart_console(&up->port) && console_suspend_enabled) 1633 err = pm_runtime_force_suspend(dev); 1634 flush_work(&priv->qos_work); 1635 1636 return err; 1637} 1638 1639static int omap8250_resume(struct device *dev) 1640{ 1641 struct omap8250_priv *priv = dev_get_drvdata(dev); 1642 struct uart_8250_port *up = serial8250_get_port(priv->line); 1643 int err; 1644 1645 if (uart_console(&up->port) && console_suspend_enabled) { 1646 err = pm_runtime_force_resume(dev); 1647 if (err) 1648 return err; 1649 } 1650 1651 serial8250_resume_port(priv->line); 1652 /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */ 1653 pm_runtime_mark_last_busy(dev); 1654 pm_runtime_put_autosuspend(dev); 1655 1656 return 0; 1657} 1658 1659static int omap8250_lost_context(struct uart_8250_port *up) 1660{ 1661 u32 val; 1662 1663 val = serial_in(up, UART_OMAP_SCR); 1664 /* 1665 * If we lose context, then SCR is set to its reset value of zero. 1666 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1667 * among other bits, to never set the register back to zero again. 1668 */ 1669 if (!val) 1670 return 1; 1671 return 0; 1672} 1673 1674static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val) 1675{ 1676 writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT)); 1677} 1678 1679/* TODO: in future, this should happen via API in drivers/reset/ */ 1680static int omap8250_soft_reset(struct device *dev) 1681{ 1682 struct omap8250_priv *priv = dev_get_drvdata(dev); 1683 int timeout = 100; 1684 int sysc; 1685 int syss; 1686 1687 /* 1688 * At least on omap4, unused uarts may not idle after reset without 1689 * a basic scr dma configuration even with no dma in use. The 1690 * module clkctrl status bits will be 1 instead of 3 blocking idle 1691 * for the whole clockdomain. The softreset below will clear scr, 1692 * and we restore it on resume so this is safe to do on all SoCs 1693 * needing omap8250_soft_reset() quirk. Do it in two writes as 1694 * recommended in the comment for omap8250_update_scr(). 1695 */ 1696 uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1697 uart_write(priv, UART_OMAP_SCR, 1698 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); 1699 1700 sysc = uart_read(priv, UART_OMAP_SYSC); 1701 1702 /* softreset the UART */ 1703 sysc |= OMAP_UART_SYSC_SOFTRESET; 1704 uart_write(priv, UART_OMAP_SYSC, sysc); 1705 1706 /* By experiments, 1us enough for reset complete on AM335x */ 1707 do { 1708 udelay(1); 1709 syss = uart_read(priv, UART_OMAP_SYSS); 1710 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1711 1712 if (!timeout) { 1713 dev_err(dev, "timed out waiting for reset done\n"); 1714 return -ETIMEDOUT; 1715 } 1716 1717 return 0; 1718} 1719 1720static int omap8250_runtime_suspend(struct device *dev) 1721{ 1722 struct omap8250_priv *priv = dev_get_drvdata(dev); 1723 struct uart_8250_port *up = NULL; 1724 1725 if (priv->line >= 0) 1726 up = serial8250_get_port(priv->line); 1727 1728 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1729 int ret; 1730 1731 ret = omap8250_soft_reset(dev); 1732 if (ret) 1733 return ret; 1734 1735 if (up) { 1736 /* Restore to UART mode after reset (for wakeup) */ 1737 omap8250_update_mdr1(up, priv); 1738 /* Restore wakeup enable register */ 1739 serial_out(up, UART_OMAP_WER, priv->wer); 1740 } 1741 } 1742 1743 if (up && up->dma && up->dma->rxchan) 1744 omap_8250_rx_dma_flush(up); 1745 1746 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1747 schedule_work(&priv->qos_work); 1748 1749 return 0; 1750} 1751 1752static int omap8250_runtime_resume(struct device *dev) 1753{ 1754 struct omap8250_priv *priv = dev_get_drvdata(dev); 1755 struct uart_8250_port *up = NULL; 1756 1757 if (priv->line >= 0) 1758 up = serial8250_get_port(priv->line); 1759 1760 if (up && omap8250_lost_context(up)) { 1761 spin_lock_irq(&up->port.lock); 1762 omap8250_restore_regs(up); 1763 spin_unlock_irq(&up->port.lock); 1764 } 1765 1766 if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) { 1767 spin_lock_irq(&up->port.lock); 1768 omap_8250_rx_dma(up); 1769 spin_unlock_irq(&up->port.lock); 1770 } 1771 1772 priv->latency = priv->calc_latency; 1773 schedule_work(&priv->qos_work); 1774 return 0; 1775} 1776 1777#ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1778static int __init omap8250_console_fixup(void) 1779{ 1780 char *omap_str; 1781 char *options; 1782 u8 idx; 1783 1784 if (strstr(boot_command_line, "console=ttyS")) 1785 /* user set a ttyS based name for the console */ 1786 return 0; 1787 1788 omap_str = strstr(boot_command_line, "console=ttyO"); 1789 if (!omap_str) 1790 /* user did not set ttyO based console, so we don't care */ 1791 return 0; 1792 1793 omap_str += 12; 1794 if ('0' <= *omap_str && *omap_str <= '9') 1795 idx = *omap_str - '0'; 1796 else 1797 return 0; 1798 1799 omap_str++; 1800 if (omap_str[0] == ',') { 1801 omap_str++; 1802 options = omap_str; 1803 } else { 1804 options = NULL; 1805 } 1806 1807 add_preferred_console("ttyS", idx, options); 1808 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1809 idx, idx); 1810 pr_err("This ensures that you still see kernel messages. Please\n"); 1811 pr_err("update your kernel commandline.\n"); 1812 return 0; 1813} 1814console_initcall(omap8250_console_fixup); 1815#endif 1816 1817static const struct dev_pm_ops omap8250_dev_pm_ops = { 1818 SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1819 RUNTIME_PM_OPS(omap8250_runtime_suspend, 1820 omap8250_runtime_resume, NULL) 1821 .prepare = pm_sleep_ptr(omap8250_prepare), 1822 .complete = pm_sleep_ptr(omap8250_complete), 1823}; 1824 1825static struct platform_driver omap8250_platform_driver = { 1826 .driver = { 1827 .name = "omap8250", 1828 .pm = pm_ptr(&omap8250_dev_pm_ops), 1829 .of_match_table = omap8250_dt_ids, 1830 }, 1831 .probe = omap8250_probe, 1832 .remove = omap8250_remove, 1833}; 1834module_platform_driver(omap8250_platform_driver); 1835 1836MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1837MODULE_DESCRIPTION("OMAP 8250 Driver"); 1838MODULE_LICENSE("GPL v2"); 1839