162306a36Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0
262306a36Sopenharmony_ci/*
362306a36Sopenharmony_ci * Copyright (c) 2015, The Linux Foundation. All rights reserved.
462306a36Sopenharmony_ci */
562306a36Sopenharmony_ci
662306a36Sopenharmony_ci#include <linux/platform_device.h>
762306a36Sopenharmony_ci#include <linux/delay.h>
862306a36Sopenharmony_ci#include <linux/bitops.h>
962306a36Sopenharmony_ci#include <linux/regmap.h>
1062306a36Sopenharmony_ci#include <linux/thermal.h>
1162306a36Sopenharmony_ci#include "tsens.h"
1262306a36Sopenharmony_ci
1362306a36Sopenharmony_ci#define CONFIG_ADDR		0x3640
1462306a36Sopenharmony_ci#define CONFIG_ADDR_8660	0x3620
1562306a36Sopenharmony_ci/* CONFIG_ADDR bitmasks */
1662306a36Sopenharmony_ci#define CONFIG			0x9b
1762306a36Sopenharmony_ci#define CONFIG_MASK		0xf
1862306a36Sopenharmony_ci#define CONFIG_8660		1
1962306a36Sopenharmony_ci#define CONFIG_SHIFT_8660	28
2062306a36Sopenharmony_ci#define CONFIG_MASK_8660	(3 << CONFIG_SHIFT_8660)
2162306a36Sopenharmony_ci
2262306a36Sopenharmony_ci#define CNTL_ADDR		0x3620
2362306a36Sopenharmony_ci/* CNTL_ADDR bitmasks */
2462306a36Sopenharmony_ci#define EN			BIT(0)
2562306a36Sopenharmony_ci#define SW_RST			BIT(1)
2662306a36Sopenharmony_ci
2762306a36Sopenharmony_ci#define MEASURE_PERIOD		BIT(18)
2862306a36Sopenharmony_ci#define SLP_CLK_ENA		BIT(26)
2962306a36Sopenharmony_ci#define SLP_CLK_ENA_8660	BIT(24)
3062306a36Sopenharmony_ci#define SENSOR0_SHIFT		3
3162306a36Sopenharmony_ci
3262306a36Sopenharmony_ci#define THRESHOLD_ADDR		0x3624
3362306a36Sopenharmony_ci
3462306a36Sopenharmony_ci#define INT_STATUS_ADDR		0x363c
3562306a36Sopenharmony_ci
3662306a36Sopenharmony_ci#define S0_STATUS_OFF		0x3628
3762306a36Sopenharmony_ci#define S1_STATUS_OFF		0x362c
3862306a36Sopenharmony_ci#define S2_STATUS_OFF		0x3630
3962306a36Sopenharmony_ci#define S3_STATUS_OFF		0x3634
4062306a36Sopenharmony_ci#define S4_STATUS_OFF		0x3638
4162306a36Sopenharmony_ci#define S5_STATUS_OFF		0x3664  /* Sensors 5-10 found on apq8064/msm8960 */
4262306a36Sopenharmony_ci#define S6_STATUS_OFF		0x3668
4362306a36Sopenharmony_ci#define S7_STATUS_OFF		0x366c
4462306a36Sopenharmony_ci#define S8_STATUS_OFF		0x3670
4562306a36Sopenharmony_ci#define S9_STATUS_OFF		0x3674
4662306a36Sopenharmony_ci#define S10_STATUS_OFF		0x3678
4762306a36Sopenharmony_ci
4862306a36Sopenharmony_ci/* Original slope - 350 to compensate mC to C inaccuracy */
4962306a36Sopenharmony_cistatic u32 tsens_msm8960_slope[] = {
5062306a36Sopenharmony_ci			826, 826, 804, 826,
5162306a36Sopenharmony_ci			761, 782, 782, 849,
5262306a36Sopenharmony_ci			782, 849, 782
5362306a36Sopenharmony_ci			};
5462306a36Sopenharmony_ci
5562306a36Sopenharmony_cistatic int suspend_8960(struct tsens_priv *priv)
5662306a36Sopenharmony_ci{
5762306a36Sopenharmony_ci	int ret;
5862306a36Sopenharmony_ci	unsigned int mask;
5962306a36Sopenharmony_ci	struct regmap *map = priv->tm_map;
6062306a36Sopenharmony_ci
6162306a36Sopenharmony_ci	ret = regmap_read(map, THRESHOLD_ADDR, &priv->ctx.threshold);
6262306a36Sopenharmony_ci	if (ret)
6362306a36Sopenharmony_ci		return ret;
6462306a36Sopenharmony_ci
6562306a36Sopenharmony_ci	ret = regmap_read(map, CNTL_ADDR, &priv->ctx.control);
6662306a36Sopenharmony_ci	if (ret)
6762306a36Sopenharmony_ci		return ret;
6862306a36Sopenharmony_ci
6962306a36Sopenharmony_ci	if (priv->num_sensors > 1)
7062306a36Sopenharmony_ci		mask = SLP_CLK_ENA | EN;
7162306a36Sopenharmony_ci	else
7262306a36Sopenharmony_ci		mask = SLP_CLK_ENA_8660 | EN;
7362306a36Sopenharmony_ci
7462306a36Sopenharmony_ci	ret = regmap_update_bits(map, CNTL_ADDR, mask, 0);
7562306a36Sopenharmony_ci	if (ret)
7662306a36Sopenharmony_ci		return ret;
7762306a36Sopenharmony_ci
7862306a36Sopenharmony_ci	return 0;
7962306a36Sopenharmony_ci}
8062306a36Sopenharmony_ci
8162306a36Sopenharmony_cistatic int resume_8960(struct tsens_priv *priv)
8262306a36Sopenharmony_ci{
8362306a36Sopenharmony_ci	int ret;
8462306a36Sopenharmony_ci	struct regmap *map = priv->tm_map;
8562306a36Sopenharmony_ci
8662306a36Sopenharmony_ci	ret = regmap_update_bits(map, CNTL_ADDR, SW_RST, SW_RST);
8762306a36Sopenharmony_ci	if (ret)
8862306a36Sopenharmony_ci		return ret;
8962306a36Sopenharmony_ci
9062306a36Sopenharmony_ci	/*
9162306a36Sopenharmony_ci	 * Separate CONFIG restore is not needed only for 8660 as
9262306a36Sopenharmony_ci	 * config is part of CTRL Addr and its restored as such
9362306a36Sopenharmony_ci	 */
9462306a36Sopenharmony_ci	if (priv->num_sensors > 1) {
9562306a36Sopenharmony_ci		ret = regmap_update_bits(map, CONFIG_ADDR, CONFIG_MASK, CONFIG);
9662306a36Sopenharmony_ci		if (ret)
9762306a36Sopenharmony_ci			return ret;
9862306a36Sopenharmony_ci	}
9962306a36Sopenharmony_ci
10062306a36Sopenharmony_ci	ret = regmap_write(map, THRESHOLD_ADDR, priv->ctx.threshold);
10162306a36Sopenharmony_ci	if (ret)
10262306a36Sopenharmony_ci		return ret;
10362306a36Sopenharmony_ci
10462306a36Sopenharmony_ci	ret = regmap_write(map, CNTL_ADDR, priv->ctx.control);
10562306a36Sopenharmony_ci	if (ret)
10662306a36Sopenharmony_ci		return ret;
10762306a36Sopenharmony_ci
10862306a36Sopenharmony_ci	return 0;
10962306a36Sopenharmony_ci}
11062306a36Sopenharmony_ci
11162306a36Sopenharmony_cistatic int enable_8960(struct tsens_priv *priv, int id)
11262306a36Sopenharmony_ci{
11362306a36Sopenharmony_ci	int ret;
11462306a36Sopenharmony_ci	u32 reg, mask = BIT(id);
11562306a36Sopenharmony_ci
11662306a36Sopenharmony_ci	ret = regmap_read(priv->tm_map, CNTL_ADDR, &reg);
11762306a36Sopenharmony_ci	if (ret)
11862306a36Sopenharmony_ci		return ret;
11962306a36Sopenharmony_ci
12062306a36Sopenharmony_ci	/* HARDWARE BUG:
12162306a36Sopenharmony_ci	 * On platforms with more than 6 sensors, all remaining sensors
12262306a36Sopenharmony_ci	 * must be enabled together, otherwise undefined results are expected.
12362306a36Sopenharmony_ci	 * (Sensor 6-7 disabled, Sensor 3 disabled...) In the original driver,
12462306a36Sopenharmony_ci	 * all the sensors are enabled in one step hence this bug is not
12562306a36Sopenharmony_ci	 * triggered.
12662306a36Sopenharmony_ci	 */
12762306a36Sopenharmony_ci	if (id > 5)
12862306a36Sopenharmony_ci		mask = GENMASK(10, 6);
12962306a36Sopenharmony_ci
13062306a36Sopenharmony_ci	mask <<= SENSOR0_SHIFT;
13162306a36Sopenharmony_ci
13262306a36Sopenharmony_ci	/* Sensors already enabled. Skip. */
13362306a36Sopenharmony_ci	if ((reg & mask) == mask)
13462306a36Sopenharmony_ci		return 0;
13562306a36Sopenharmony_ci
13662306a36Sopenharmony_ci	ret = regmap_write(priv->tm_map, CNTL_ADDR, reg | SW_RST);
13762306a36Sopenharmony_ci	if (ret)
13862306a36Sopenharmony_ci		return ret;
13962306a36Sopenharmony_ci
14062306a36Sopenharmony_ci	reg |= MEASURE_PERIOD;
14162306a36Sopenharmony_ci
14262306a36Sopenharmony_ci	if (priv->num_sensors > 1)
14362306a36Sopenharmony_ci		reg |= mask | SLP_CLK_ENA | EN;
14462306a36Sopenharmony_ci	else
14562306a36Sopenharmony_ci		reg |= mask | SLP_CLK_ENA_8660 | EN;
14662306a36Sopenharmony_ci
14762306a36Sopenharmony_ci	ret = regmap_write(priv->tm_map, CNTL_ADDR, reg);
14862306a36Sopenharmony_ci	if (ret)
14962306a36Sopenharmony_ci		return ret;
15062306a36Sopenharmony_ci
15162306a36Sopenharmony_ci	return 0;
15262306a36Sopenharmony_ci}
15362306a36Sopenharmony_ci
15462306a36Sopenharmony_cistatic void disable_8960(struct tsens_priv *priv)
15562306a36Sopenharmony_ci{
15662306a36Sopenharmony_ci	int ret;
15762306a36Sopenharmony_ci	u32 reg_cntl;
15862306a36Sopenharmony_ci	u32 mask;
15962306a36Sopenharmony_ci
16062306a36Sopenharmony_ci	mask = GENMASK(priv->num_sensors - 1, 0);
16162306a36Sopenharmony_ci	mask <<= SENSOR0_SHIFT;
16262306a36Sopenharmony_ci	mask |= EN;
16362306a36Sopenharmony_ci
16462306a36Sopenharmony_ci	ret = regmap_read(priv->tm_map, CNTL_ADDR, &reg_cntl);
16562306a36Sopenharmony_ci	if (ret)
16662306a36Sopenharmony_ci		return;
16762306a36Sopenharmony_ci
16862306a36Sopenharmony_ci	reg_cntl &= ~mask;
16962306a36Sopenharmony_ci
17062306a36Sopenharmony_ci	if (priv->num_sensors > 1)
17162306a36Sopenharmony_ci		reg_cntl &= ~SLP_CLK_ENA;
17262306a36Sopenharmony_ci	else
17362306a36Sopenharmony_ci		reg_cntl &= ~SLP_CLK_ENA_8660;
17462306a36Sopenharmony_ci
17562306a36Sopenharmony_ci	regmap_write(priv->tm_map, CNTL_ADDR, reg_cntl);
17662306a36Sopenharmony_ci}
17762306a36Sopenharmony_ci
17862306a36Sopenharmony_cistatic int calibrate_8960(struct tsens_priv *priv)
17962306a36Sopenharmony_ci{
18062306a36Sopenharmony_ci	int i;
18162306a36Sopenharmony_ci	char *data;
18262306a36Sopenharmony_ci	u32 p1[11];
18362306a36Sopenharmony_ci
18462306a36Sopenharmony_ci	data = qfprom_read(priv->dev, "calib");
18562306a36Sopenharmony_ci	if (IS_ERR(data))
18662306a36Sopenharmony_ci		data = qfprom_read(priv->dev, "calib_backup");
18762306a36Sopenharmony_ci	if (IS_ERR(data))
18862306a36Sopenharmony_ci		return PTR_ERR(data);
18962306a36Sopenharmony_ci
19062306a36Sopenharmony_ci	for (i = 0; i < priv->num_sensors; i++) {
19162306a36Sopenharmony_ci		p1[i] = data[i];
19262306a36Sopenharmony_ci		priv->sensor[i].slope = tsens_msm8960_slope[i];
19362306a36Sopenharmony_ci	}
19462306a36Sopenharmony_ci
19562306a36Sopenharmony_ci	compute_intercept_slope(priv, p1, NULL, ONE_PT_CALIB);
19662306a36Sopenharmony_ci
19762306a36Sopenharmony_ci	kfree(data);
19862306a36Sopenharmony_ci
19962306a36Sopenharmony_ci	return 0;
20062306a36Sopenharmony_ci}
20162306a36Sopenharmony_ci
20262306a36Sopenharmony_cistatic const struct reg_field tsens_8960_regfields[MAX_REGFIELDS] = {
20362306a36Sopenharmony_ci	/* ----- SROT ------ */
20462306a36Sopenharmony_ci	/* No VERSION information */
20562306a36Sopenharmony_ci
20662306a36Sopenharmony_ci	/* CNTL */
20762306a36Sopenharmony_ci	[TSENS_EN]     = REG_FIELD(CNTL_ADDR,  0, 0),
20862306a36Sopenharmony_ci	[TSENS_SW_RST] = REG_FIELD(CNTL_ADDR,  1, 1),
20962306a36Sopenharmony_ci	/* 8960 has 5 sensors, 8660 has 11, we only handle 5 */
21062306a36Sopenharmony_ci	[SENSOR_EN]    = REG_FIELD(CNTL_ADDR,  3, 7),
21162306a36Sopenharmony_ci
21262306a36Sopenharmony_ci	/* ----- TM ------ */
21362306a36Sopenharmony_ci	/* INTERRUPT ENABLE */
21462306a36Sopenharmony_ci	/* NO INTERRUPT ENABLE */
21562306a36Sopenharmony_ci
21662306a36Sopenharmony_ci	/* Single UPPER/LOWER TEMPERATURE THRESHOLD for all sensors */
21762306a36Sopenharmony_ci	[LOW_THRESH_0]   = REG_FIELD(THRESHOLD_ADDR,  0,  7),
21862306a36Sopenharmony_ci	[UP_THRESH_0]    = REG_FIELD(THRESHOLD_ADDR,  8, 15),
21962306a36Sopenharmony_ci	/* MIN_THRESH_0 and MAX_THRESH_0 are not present in the regfield
22062306a36Sopenharmony_ci	 * Recycle CRIT_THRESH_0 and 1 to set the required regs to hardcoded temp
22162306a36Sopenharmony_ci	 * MIN_THRESH_0 -> CRIT_THRESH_1
22262306a36Sopenharmony_ci	 * MAX_THRESH_0 -> CRIT_THRESH_0
22362306a36Sopenharmony_ci	 */
22462306a36Sopenharmony_ci	[CRIT_THRESH_1]   = REG_FIELD(THRESHOLD_ADDR, 16, 23),
22562306a36Sopenharmony_ci	[CRIT_THRESH_0]   = REG_FIELD(THRESHOLD_ADDR, 24, 31),
22662306a36Sopenharmony_ci
22762306a36Sopenharmony_ci	/* UPPER/LOWER INTERRUPT [CLEAR/STATUS] */
22862306a36Sopenharmony_ci	/* 1 == clear, 0 == normal operation */
22962306a36Sopenharmony_ci	[LOW_INT_CLEAR_0]   = REG_FIELD(CNTL_ADDR,  9,  9),
23062306a36Sopenharmony_ci	[UP_INT_CLEAR_0]    = REG_FIELD(CNTL_ADDR, 10, 10),
23162306a36Sopenharmony_ci
23262306a36Sopenharmony_ci	/* NO CRITICAL INTERRUPT SUPPORT on 8960 */
23362306a36Sopenharmony_ci
23462306a36Sopenharmony_ci	/* Sn_STATUS */
23562306a36Sopenharmony_ci	[LAST_TEMP_0]  = REG_FIELD(S0_STATUS_OFF,  0,  7),
23662306a36Sopenharmony_ci	[LAST_TEMP_1]  = REG_FIELD(S1_STATUS_OFF,  0,  7),
23762306a36Sopenharmony_ci	[LAST_TEMP_2]  = REG_FIELD(S2_STATUS_OFF,  0,  7),
23862306a36Sopenharmony_ci	[LAST_TEMP_3]  = REG_FIELD(S3_STATUS_OFF,  0,  7),
23962306a36Sopenharmony_ci	[LAST_TEMP_4]  = REG_FIELD(S4_STATUS_OFF,  0,  7),
24062306a36Sopenharmony_ci	[LAST_TEMP_5]  = REG_FIELD(S5_STATUS_OFF,  0,  7),
24162306a36Sopenharmony_ci	[LAST_TEMP_6]  = REG_FIELD(S6_STATUS_OFF,  0,  7),
24262306a36Sopenharmony_ci	[LAST_TEMP_7]  = REG_FIELD(S7_STATUS_OFF,  0,  7),
24362306a36Sopenharmony_ci	[LAST_TEMP_8]  = REG_FIELD(S8_STATUS_OFF,  0,  7),
24462306a36Sopenharmony_ci	[LAST_TEMP_9]  = REG_FIELD(S9_STATUS_OFF,  0,  7),
24562306a36Sopenharmony_ci	[LAST_TEMP_10] = REG_FIELD(S10_STATUS_OFF, 0,  7),
24662306a36Sopenharmony_ci
24762306a36Sopenharmony_ci	/* No VALID field on 8960 */
24862306a36Sopenharmony_ci	/* TSENS_INT_STATUS bits: 1 == threshold violated */
24962306a36Sopenharmony_ci	[MIN_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 0, 0),
25062306a36Sopenharmony_ci	[LOWER_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 1, 1),
25162306a36Sopenharmony_ci	[UPPER_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 2, 2),
25262306a36Sopenharmony_ci	/* No CRITICAL field on 8960 */
25362306a36Sopenharmony_ci	[MAX_STATUS_0] = REG_FIELD(INT_STATUS_ADDR, 3, 3),
25462306a36Sopenharmony_ci
25562306a36Sopenharmony_ci	/* TRDY: 1=ready, 0=in progress */
25662306a36Sopenharmony_ci	[TRDY] = REG_FIELD(INT_STATUS_ADDR, 7, 7),
25762306a36Sopenharmony_ci};
25862306a36Sopenharmony_ci
25962306a36Sopenharmony_cistatic const struct tsens_ops ops_8960 = {
26062306a36Sopenharmony_ci	.init		= init_common,
26162306a36Sopenharmony_ci	.calibrate	= calibrate_8960,
26262306a36Sopenharmony_ci	.get_temp	= get_temp_common,
26362306a36Sopenharmony_ci	.enable		= enable_8960,
26462306a36Sopenharmony_ci	.disable	= disable_8960,
26562306a36Sopenharmony_ci	.suspend	= suspend_8960,
26662306a36Sopenharmony_ci	.resume		= resume_8960,
26762306a36Sopenharmony_ci};
26862306a36Sopenharmony_ci
26962306a36Sopenharmony_cistatic struct tsens_features tsens_8960_feat = {
27062306a36Sopenharmony_ci	.ver_major	= VER_0,
27162306a36Sopenharmony_ci	.crit_int	= 0,
27262306a36Sopenharmony_ci	.combo_int	= 0,
27362306a36Sopenharmony_ci	.adc		= 1,
27462306a36Sopenharmony_ci	.srot_split	= 0,
27562306a36Sopenharmony_ci	.max_sensors	= 11,
27662306a36Sopenharmony_ci	.trip_min_temp	= -40000,
27762306a36Sopenharmony_ci	.trip_max_temp	= 120000,
27862306a36Sopenharmony_ci};
27962306a36Sopenharmony_ci
28062306a36Sopenharmony_cistruct tsens_plat_data data_8960 = {
28162306a36Sopenharmony_ci	.num_sensors	= 11,
28262306a36Sopenharmony_ci	.ops		= &ops_8960,
28362306a36Sopenharmony_ci	.feat		= &tsens_8960_feat,
28462306a36Sopenharmony_ci	.fields		= tsens_8960_regfields,
28562306a36Sopenharmony_ci};
286