1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * MPC52xx SPI bus driver.
4 *
5 * Copyright (C) 2008 Secret Lab Technologies Ltd.
6 *
7 * This is the driver for the MPC5200's dedicated SPI controller.
8 *
9 * Note: this driver does not support the MPC5200 PSC in SPI mode.  For
10 * that driver see drivers/spi/mpc52xx_psc_spi.c
11 */
12
13#include <linux/module.h>
14#include <linux/err.h>
15#include <linux/errno.h>
16#include <linux/of_platform.h>
17#include <linux/interrupt.h>
18#include <linux/delay.h>
19#include <linux/gpio/consumer.h>
20#include <linux/spi/spi.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23#include <linux/of_address.h>
24#include <linux/of_irq.h>
25
26#include <asm/time.h>
27#include <asm/mpc52xx.h>
28
29MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
30MODULE_DESCRIPTION("MPC52xx SPI (non-PSC) Driver");
31MODULE_LICENSE("GPL");
32
33/* Register offsets */
34#define SPI_CTRL1	0x00
35#define SPI_CTRL1_SPIE		(1 << 7)
36#define SPI_CTRL1_SPE		(1 << 6)
37#define SPI_CTRL1_MSTR		(1 << 4)
38#define SPI_CTRL1_CPOL		(1 << 3)
39#define SPI_CTRL1_CPHA		(1 << 2)
40#define SPI_CTRL1_SSOE		(1 << 1)
41#define SPI_CTRL1_LSBFE		(1 << 0)
42
43#define SPI_CTRL2	0x01
44#define SPI_BRR		0x04
45
46#define SPI_STATUS	0x05
47#define SPI_STATUS_SPIF		(1 << 7)
48#define SPI_STATUS_WCOL		(1 << 6)
49#define SPI_STATUS_MODF		(1 << 4)
50
51#define SPI_DATA	0x09
52#define SPI_PORTDATA	0x0d
53#define SPI_DATADIR	0x10
54
55/* FSM state return values */
56#define FSM_STOP	0	/* Nothing more for the state machine to */
57				/* do.  If something interesting happens */
58				/* then an IRQ will be received */
59#define FSM_POLL	1	/* need to poll for completion, an IRQ is */
60				/* not expected */
61#define FSM_CONTINUE	2	/* Keep iterating the state machine */
62
63/* Driver internal data */
64struct mpc52xx_spi {
65	struct spi_master *master;
66	void __iomem *regs;
67	int irq0;	/* MODF irq */
68	int irq1;	/* SPIF irq */
69	unsigned int ipb_freq;
70
71	/* Statistics; not used now, but will be reintroduced for debugfs */
72	int msg_count;
73	int wcol_count;
74	int wcol_ticks;
75	u32 wcol_tx_timestamp;
76	int modf_count;
77	int byte_count;
78
79	struct list_head queue;		/* queue of pending messages */
80	spinlock_t lock;
81	struct work_struct work;
82
83	/* Details of current transfer (length, and buffer pointers) */
84	struct spi_message *message;	/* current message */
85	struct spi_transfer *transfer;	/* current transfer */
86	int (*state)(int irq, struct mpc52xx_spi *ms, u8 status, u8 data);
87	int len;
88	int timestamp;
89	u8 *rx_buf;
90	const u8 *tx_buf;
91	int cs_change;
92	int gpio_cs_count;
93	struct gpio_desc **gpio_cs;
94};
95
96/*
97 * CS control function
98 */
99static void mpc52xx_spi_chipsel(struct mpc52xx_spi *ms, int value)
100{
101	int cs;
102
103	if (ms->gpio_cs_count > 0) {
104		cs = spi_get_chipselect(ms->message->spi, 0);
105		gpiod_set_value(ms->gpio_cs[cs], value);
106	} else {
107		out_8(ms->regs + SPI_PORTDATA, value ? 0 : 0x08);
108	}
109}
110
111/*
112 * Start a new transfer.  This is called both by the idle state
113 * for the first transfer in a message, and by the wait state when the
114 * previous transfer in a message is complete.
115 */
116static void mpc52xx_spi_start_transfer(struct mpc52xx_spi *ms)
117{
118	ms->rx_buf = ms->transfer->rx_buf;
119	ms->tx_buf = ms->transfer->tx_buf;
120	ms->len = ms->transfer->len;
121
122	/* Activate the chip select */
123	if (ms->cs_change)
124		mpc52xx_spi_chipsel(ms, 1);
125	ms->cs_change = ms->transfer->cs_change;
126
127	/* Write out the first byte */
128	ms->wcol_tx_timestamp = mftb();
129	if (ms->tx_buf)
130		out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
131	else
132		out_8(ms->regs + SPI_DATA, 0);
133}
134
135/* Forward declaration of state handlers */
136static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
137					 u8 status, u8 data);
138static int mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms,
139				     u8 status, u8 data);
140
141/*
142 * IDLE state
143 *
144 * No transfers are in progress; if another transfer is pending then retrieve
145 * it and kick it off.  Otherwise, stop processing the state machine
146 */
147static int
148mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
149{
150	struct spi_device *spi;
151	int spr, sppr;
152	u8 ctrl1;
153
154	if (status && irq)
155		dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
156			status);
157
158	/* Check if there is another transfer waiting. */
159	if (list_empty(&ms->queue))
160		return FSM_STOP;
161
162	/* get the head of the queue */
163	ms->message = list_first_entry(&ms->queue, struct spi_message, queue);
164	list_del_init(&ms->message->queue);
165
166	/* Setup the controller parameters */
167	ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
168	spi = ms->message->spi;
169	if (spi->mode & SPI_CPHA)
170		ctrl1 |= SPI_CTRL1_CPHA;
171	if (spi->mode & SPI_CPOL)
172		ctrl1 |= SPI_CTRL1_CPOL;
173	if (spi->mode & SPI_LSB_FIRST)
174		ctrl1 |= SPI_CTRL1_LSBFE;
175	out_8(ms->regs + SPI_CTRL1, ctrl1);
176
177	/* Setup the controller speed */
178	/* minimum divider is '2'.  Also, add '1' to force rounding the
179	 * divider up. */
180	sppr = ((ms->ipb_freq / ms->message->spi->max_speed_hz) + 1) >> 1;
181	spr = 0;
182	if (sppr < 1)
183		sppr = 1;
184	while (((sppr - 1) & ~0x7) != 0) {
185		sppr = (sppr + 1) >> 1; /* add '1' to force rounding up */
186		spr++;
187	}
188	sppr--;		/* sppr quantity in register is offset by 1 */
189	if (spr > 7) {
190		/* Don't overrun limits of SPI baudrate register */
191		spr = 7;
192		sppr = 7;
193	}
194	out_8(ms->regs + SPI_BRR, sppr << 4 | spr); /* Set speed */
195
196	ms->cs_change = 1;
197	ms->transfer = container_of(ms->message->transfers.next,
198				    struct spi_transfer, transfer_list);
199
200	mpc52xx_spi_start_transfer(ms);
201	ms->state = mpc52xx_spi_fsmstate_transfer;
202
203	return FSM_CONTINUE;
204}
205
206/*
207 * TRANSFER state
208 *
209 * In the middle of a transfer.  If the SPI core has completed processing
210 * a byte, then read out the received data and write out the next byte
211 * (unless this transfer is finished; in which case go on to the wait
212 * state)
213 */
214static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
215					 u8 status, u8 data)
216{
217	if (!status)
218		return ms->irq0 ? FSM_STOP : FSM_POLL;
219
220	if (status & SPI_STATUS_WCOL) {
221		/* The SPI controller is stoopid.  At slower speeds, it may
222		 * raise the SPIF flag before the state machine is actually
223		 * finished, which causes a collision (internal to the state
224		 * machine only).  The manual recommends inserting a delay
225		 * between receiving the interrupt and sending the next byte,
226		 * but it can also be worked around simply by retrying the
227		 * transfer which is what we do here. */
228		ms->wcol_count++;
229		ms->wcol_ticks += mftb() - ms->wcol_tx_timestamp;
230		ms->wcol_tx_timestamp = mftb();
231		data = 0;
232		if (ms->tx_buf)
233			data = *(ms->tx_buf - 1);
234		out_8(ms->regs + SPI_DATA, data); /* try again */
235		return FSM_CONTINUE;
236	} else if (status & SPI_STATUS_MODF) {
237		ms->modf_count++;
238		dev_err(&ms->master->dev, "mode fault\n");
239		mpc52xx_spi_chipsel(ms, 0);
240		ms->message->status = -EIO;
241		if (ms->message->complete)
242			ms->message->complete(ms->message->context);
243		ms->state = mpc52xx_spi_fsmstate_idle;
244		return FSM_CONTINUE;
245	}
246
247	/* Read data out of the spi device */
248	ms->byte_count++;
249	if (ms->rx_buf)
250		*ms->rx_buf++ = data;
251
252	/* Is the transfer complete? */
253	ms->len--;
254	if (ms->len == 0) {
255		ms->timestamp = mftb();
256		if (ms->transfer->delay.unit == SPI_DELAY_UNIT_USECS)
257			ms->timestamp += ms->transfer->delay.value *
258					 tb_ticks_per_usec;
259		ms->state = mpc52xx_spi_fsmstate_wait;
260		return FSM_CONTINUE;
261	}
262
263	/* Write out the next byte */
264	ms->wcol_tx_timestamp = mftb();
265	if (ms->tx_buf)
266		out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
267	else
268		out_8(ms->regs + SPI_DATA, 0);
269
270	return FSM_CONTINUE;
271}
272
273/*
274 * WAIT state
275 *
276 * A transfer has completed; need to wait for the delay period to complete
277 * before starting the next transfer
278 */
279static int
280mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
281{
282	if (status && irq)
283		dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
284			status);
285
286	if (((int)mftb()) - ms->timestamp < 0)
287		return FSM_POLL;
288
289	ms->message->actual_length += ms->transfer->len;
290
291	/* Check if there is another transfer in this message.  If there
292	 * aren't then deactivate CS, notify sender, and drop back to idle
293	 * to start the next message. */
294	if (ms->transfer->transfer_list.next == &ms->message->transfers) {
295		ms->msg_count++;
296		mpc52xx_spi_chipsel(ms, 0);
297		ms->message->status = 0;
298		if (ms->message->complete)
299			ms->message->complete(ms->message->context);
300		ms->state = mpc52xx_spi_fsmstate_idle;
301		return FSM_CONTINUE;
302	}
303
304	/* There is another transfer; kick it off */
305
306	if (ms->cs_change)
307		mpc52xx_spi_chipsel(ms, 0);
308
309	ms->transfer = container_of(ms->transfer->transfer_list.next,
310				    struct spi_transfer, transfer_list);
311	mpc52xx_spi_start_transfer(ms);
312	ms->state = mpc52xx_spi_fsmstate_transfer;
313	return FSM_CONTINUE;
314}
315
316/**
317 * mpc52xx_spi_fsm_process - Finite State Machine iteration function
318 * @irq: irq number that triggered the FSM or 0 for polling
319 * @ms: pointer to mpc52xx_spi driver data
320 */
321static void mpc52xx_spi_fsm_process(int irq, struct mpc52xx_spi *ms)
322{
323	int rc = FSM_CONTINUE;
324	u8 status, data;
325
326	while (rc == FSM_CONTINUE) {
327		/* Interrupt cleared by read of STATUS followed by
328		 * read of DATA registers */
329		status = in_8(ms->regs + SPI_STATUS);
330		data = in_8(ms->regs + SPI_DATA);
331		rc = ms->state(irq, ms, status, data);
332	}
333
334	if (rc == FSM_POLL)
335		schedule_work(&ms->work);
336}
337
338/**
339 * mpc52xx_spi_irq - IRQ handler
340 */
341static irqreturn_t mpc52xx_spi_irq(int irq, void *_ms)
342{
343	struct mpc52xx_spi *ms = _ms;
344	spin_lock(&ms->lock);
345	mpc52xx_spi_fsm_process(irq, ms);
346	spin_unlock(&ms->lock);
347	return IRQ_HANDLED;
348}
349
350/**
351 * mpc52xx_spi_wq - Workqueue function for polling the state machine
352 */
353static void mpc52xx_spi_wq(struct work_struct *work)
354{
355	struct mpc52xx_spi *ms = container_of(work, struct mpc52xx_spi, work);
356	unsigned long flags;
357
358	spin_lock_irqsave(&ms->lock, flags);
359	mpc52xx_spi_fsm_process(0, ms);
360	spin_unlock_irqrestore(&ms->lock, flags);
361}
362
363/*
364 * spi_master ops
365 */
366
367static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m)
368{
369	struct mpc52xx_spi *ms = spi_master_get_devdata(spi->master);
370	unsigned long flags;
371
372	m->actual_length = 0;
373	m->status = -EINPROGRESS;
374
375	spin_lock_irqsave(&ms->lock, flags);
376	list_add_tail(&m->queue, &ms->queue);
377	spin_unlock_irqrestore(&ms->lock, flags);
378	schedule_work(&ms->work);
379
380	return 0;
381}
382
383/*
384 * OF Platform Bus Binding
385 */
386static int mpc52xx_spi_probe(struct platform_device *op)
387{
388	struct spi_master *master;
389	struct mpc52xx_spi *ms;
390	struct gpio_desc *gpio_cs;
391	void __iomem *regs;
392	u8 ctrl1;
393	int rc, i = 0;
394
395	/* MMIO registers */
396	dev_dbg(&op->dev, "probing mpc5200 SPI device\n");
397	regs = of_iomap(op->dev.of_node, 0);
398	if (!regs)
399		return -ENODEV;
400
401	/* initialize the device */
402	ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
403	out_8(regs + SPI_CTRL1, ctrl1);
404	out_8(regs + SPI_CTRL2, 0x0);
405	out_8(regs + SPI_DATADIR, 0xe);	/* Set output pins */
406	out_8(regs + SPI_PORTDATA, 0x8);	/* Deassert /SS signal */
407
408	/* Clear the status register and re-read it to check for a MODF
409	 * failure.  This driver cannot currently handle multiple masters
410	 * on the SPI bus.  This fault will also occur if the SPI signals
411	 * are not connected to any pins (port_config setting) */
412	in_8(regs + SPI_STATUS);
413	out_8(regs + SPI_CTRL1, ctrl1);
414
415	in_8(regs + SPI_DATA);
416	if (in_8(regs + SPI_STATUS) & SPI_STATUS_MODF) {
417		dev_err(&op->dev, "mode fault; is port_config correct?\n");
418		rc = -EIO;
419		goto err_init;
420	}
421
422	dev_dbg(&op->dev, "allocating spi_master struct\n");
423	master = spi_alloc_master(&op->dev, sizeof(*ms));
424	if (!master) {
425		rc = -ENOMEM;
426		goto err_alloc;
427	}
428
429	master->transfer = mpc52xx_spi_transfer;
430	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
431	master->bits_per_word_mask = SPI_BPW_MASK(8);
432	master->dev.of_node = op->dev.of_node;
433
434	platform_set_drvdata(op, master);
435
436	ms = spi_master_get_devdata(master);
437	ms->master = master;
438	ms->regs = regs;
439	ms->irq0 = irq_of_parse_and_map(op->dev.of_node, 0);
440	ms->irq1 = irq_of_parse_and_map(op->dev.of_node, 1);
441	ms->state = mpc52xx_spi_fsmstate_idle;
442	ms->ipb_freq = mpc5xxx_get_bus_frequency(&op->dev);
443	ms->gpio_cs_count = gpiod_count(&op->dev, NULL);
444	if (ms->gpio_cs_count > 0) {
445		master->num_chipselect = ms->gpio_cs_count;
446		ms->gpio_cs = kmalloc_array(ms->gpio_cs_count,
447					    sizeof(*ms->gpio_cs),
448					    GFP_KERNEL);
449		if (!ms->gpio_cs) {
450			rc = -ENOMEM;
451			goto err_alloc_gpio;
452		}
453
454		for (i = 0; i < ms->gpio_cs_count; i++) {
455			gpio_cs = gpiod_get_index(&op->dev,
456						  NULL, i, GPIOD_OUT_LOW);
457			rc = PTR_ERR_OR_ZERO(gpio_cs);
458			if (rc) {
459				dev_err(&op->dev,
460					"failed to get spi cs gpio #%d: %d\n",
461					i, rc);
462				goto err_gpio;
463			}
464
465			ms->gpio_cs[i] = gpio_cs;
466		}
467	}
468
469	spin_lock_init(&ms->lock);
470	INIT_LIST_HEAD(&ms->queue);
471	INIT_WORK(&ms->work, mpc52xx_spi_wq);
472
473	/* Decide if interrupts can be used */
474	if (ms->irq0 && ms->irq1) {
475		rc = request_irq(ms->irq0, mpc52xx_spi_irq, 0,
476				  "mpc5200-spi-modf", ms);
477		rc |= request_irq(ms->irq1, mpc52xx_spi_irq, 0,
478				  "mpc5200-spi-spif", ms);
479		if (rc) {
480			free_irq(ms->irq0, ms);
481			free_irq(ms->irq1, ms);
482			ms->irq0 = ms->irq1 = 0;
483		}
484	} else {
485		/* operate in polled mode */
486		ms->irq0 = ms->irq1 = 0;
487	}
488
489	if (!ms->irq0)
490		dev_info(&op->dev, "using polled mode\n");
491
492	dev_dbg(&op->dev, "registering spi_master struct\n");
493	rc = spi_register_master(master);
494	if (rc)
495		goto err_register;
496
497	dev_info(&ms->master->dev, "registered MPC5200 SPI bus\n");
498
499	return rc;
500
501 err_register:
502	dev_err(&ms->master->dev, "initialization failed\n");
503 err_gpio:
504	while (i-- > 0)
505		gpiod_put(ms->gpio_cs[i]);
506
507	kfree(ms->gpio_cs);
508 err_alloc_gpio:
509	spi_master_put(master);
510 err_alloc:
511 err_init:
512	iounmap(regs);
513	return rc;
514}
515
516static void mpc52xx_spi_remove(struct platform_device *op)
517{
518	struct spi_master *master = spi_master_get(platform_get_drvdata(op));
519	struct mpc52xx_spi *ms = spi_master_get_devdata(master);
520	int i;
521
522	free_irq(ms->irq0, ms);
523	free_irq(ms->irq1, ms);
524
525	for (i = 0; i < ms->gpio_cs_count; i++)
526		gpiod_put(ms->gpio_cs[i]);
527
528	kfree(ms->gpio_cs);
529	spi_unregister_master(master);
530	iounmap(ms->regs);
531	spi_master_put(master);
532}
533
534static const struct of_device_id mpc52xx_spi_match[] = {
535	{ .compatible = "fsl,mpc5200-spi", },
536	{}
537};
538MODULE_DEVICE_TABLE(of, mpc52xx_spi_match);
539
540static struct platform_driver mpc52xx_spi_of_driver = {
541	.driver = {
542		.name = "mpc52xx-spi",
543		.of_match_table = mpc52xx_spi_match,
544	},
545	.probe = mpc52xx_spi_probe,
546	.remove_new = mpc52xx_spi_remove,
547};
548module_platform_driver(mpc52xx_spi_of_driver);
549