1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2013 Freescale Semiconductor, Inc.
4// Copyright 2020 NXP
5//
6// Freescale DSPI driver
7// This file contains a driver for the Freescale DSPI
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/dmaengine.h>
12#include <linux/dma-mapping.h>
13#include <linux/interrupt.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/pinctrl/consumer.h>
19#include <linux/regmap.h>
20#include <linux/spi/spi.h>
21#include <linux/spi/spi-fsl-dspi.h>
22
23#define DRIVER_NAME			"fsl-dspi"
24
25#define SPI_MCR				0x00
26#define SPI_MCR_HOST			BIT(31)
27#define SPI_MCR_PCSIS(x)		((x) << 16)
28#define SPI_MCR_CLR_TXF			BIT(11)
29#define SPI_MCR_CLR_RXF			BIT(10)
30#define SPI_MCR_XSPI			BIT(3)
31#define SPI_MCR_DIS_TXF			BIT(13)
32#define SPI_MCR_DIS_RXF			BIT(12)
33#define SPI_MCR_HALT			BIT(0)
34
35#define SPI_TCR				0x08
36#define SPI_TCR_GET_TCNT(x)		(((x) & GENMASK(31, 16)) >> 16)
37
38#define SPI_CTAR(x)			(0x0c + (((x) & GENMASK(1, 0)) * 4))
39#define SPI_CTAR_FMSZ(x)		(((x) << 27) & GENMASK(30, 27))
40#define SPI_CTAR_CPOL			BIT(26)
41#define SPI_CTAR_CPHA			BIT(25)
42#define SPI_CTAR_LSBFE			BIT(24)
43#define SPI_CTAR_PCSSCK(x)		(((x) << 22) & GENMASK(23, 22))
44#define SPI_CTAR_PASC(x)		(((x) << 20) & GENMASK(21, 20))
45#define SPI_CTAR_PDT(x)			(((x) << 18) & GENMASK(19, 18))
46#define SPI_CTAR_PBR(x)			(((x) << 16) & GENMASK(17, 16))
47#define SPI_CTAR_CSSCK(x)		(((x) << 12) & GENMASK(15, 12))
48#define SPI_CTAR_ASC(x)			(((x) << 8) & GENMASK(11, 8))
49#define SPI_CTAR_DT(x)			(((x) << 4) & GENMASK(7, 4))
50#define SPI_CTAR_BR(x)			((x) & GENMASK(3, 0))
51#define SPI_CTAR_SCALE_BITS		0xf
52
53#define SPI_CTAR0_SLAVE			0x0c
54
55#define SPI_SR				0x2c
56#define SPI_SR_TCFQF			BIT(31)
57#define SPI_SR_TFUF			BIT(27)
58#define SPI_SR_TFFF			BIT(25)
59#define SPI_SR_CMDTCF			BIT(23)
60#define SPI_SR_SPEF			BIT(21)
61#define SPI_SR_RFOF			BIT(19)
62#define SPI_SR_TFIWF			BIT(18)
63#define SPI_SR_RFDF			BIT(17)
64#define SPI_SR_CMDFFF			BIT(16)
65#define SPI_SR_CLEAR			(SPI_SR_TCFQF | \
66					SPI_SR_TFUF | SPI_SR_TFFF | \
67					SPI_SR_CMDTCF | SPI_SR_SPEF | \
68					SPI_SR_RFOF | SPI_SR_TFIWF | \
69					SPI_SR_RFDF | SPI_SR_CMDFFF)
70
71#define SPI_RSER_TFFFE			BIT(25)
72#define SPI_RSER_TFFFD			BIT(24)
73#define SPI_RSER_RFDFE			BIT(17)
74#define SPI_RSER_RFDFD			BIT(16)
75
76#define SPI_RSER			0x30
77#define SPI_RSER_TCFQE			BIT(31)
78#define SPI_RSER_CMDTCFE		BIT(23)
79
80#define SPI_PUSHR			0x34
81#define SPI_PUSHR_CMD_CONT		BIT(15)
82#define SPI_PUSHR_CMD_CTAS(x)		(((x) << 12 & GENMASK(14, 12)))
83#define SPI_PUSHR_CMD_EOQ		BIT(11)
84#define SPI_PUSHR_CMD_CTCNT		BIT(10)
85#define SPI_PUSHR_CMD_PCS(x)		(BIT(x) & GENMASK(5, 0))
86
87#define SPI_PUSHR_SLAVE			0x34
88
89#define SPI_POPR			0x38
90
91#define SPI_TXFR0			0x3c
92#define SPI_TXFR1			0x40
93#define SPI_TXFR2			0x44
94#define SPI_TXFR3			0x48
95#define SPI_RXFR0			0x7c
96#define SPI_RXFR1			0x80
97#define SPI_RXFR2			0x84
98#define SPI_RXFR3			0x88
99
100#define SPI_CTARE(x)			(0x11c + (((x) & GENMASK(1, 0)) * 4))
101#define SPI_CTARE_FMSZE(x)		(((x) & 0x1) << 16)
102#define SPI_CTARE_DTCP(x)		((x) & 0x7ff)
103
104#define SPI_SREX			0x13c
105
106#define SPI_FRAME_BITS(bits)		SPI_CTAR_FMSZ((bits) - 1)
107#define SPI_FRAME_EBITS(bits)		SPI_CTARE_FMSZE(((bits) - 1) >> 4)
108
109#define DMA_COMPLETION_TIMEOUT		msecs_to_jiffies(3000)
110
111struct chip_data {
112	u32			ctar_val;
113};
114
115enum dspi_trans_mode {
116	DSPI_XSPI_MODE,
117	DSPI_DMA_MODE,
118};
119
120struct fsl_dspi_devtype_data {
121	enum dspi_trans_mode	trans_mode;
122	u8			max_clock_factor;
123	int			fifo_size;
124};
125
126enum {
127	LS1021A,
128	LS1012A,
129	LS1028A,
130	LS1043A,
131	LS1046A,
132	LS2080A,
133	LS2085A,
134	LX2160A,
135	MCF5441X,
136	VF610,
137};
138
139static const struct fsl_dspi_devtype_data devtype_data[] = {
140	[VF610] = {
141		.trans_mode		= DSPI_DMA_MODE,
142		.max_clock_factor	= 2,
143		.fifo_size		= 4,
144	},
145	[LS1021A] = {
146		/* Has A-011218 DMA erratum */
147		.trans_mode		= DSPI_XSPI_MODE,
148		.max_clock_factor	= 8,
149		.fifo_size		= 4,
150	},
151	[LS1012A] = {
152		/* Has A-011218 DMA erratum */
153		.trans_mode		= DSPI_XSPI_MODE,
154		.max_clock_factor	= 8,
155		.fifo_size		= 16,
156	},
157	[LS1028A] = {
158		.trans_mode		= DSPI_XSPI_MODE,
159		.max_clock_factor	= 8,
160		.fifo_size		= 4,
161	},
162	[LS1043A] = {
163		/* Has A-011218 DMA erratum */
164		.trans_mode		= DSPI_XSPI_MODE,
165		.max_clock_factor	= 8,
166		.fifo_size		= 16,
167	},
168	[LS1046A] = {
169		/* Has A-011218 DMA erratum */
170		.trans_mode		= DSPI_XSPI_MODE,
171		.max_clock_factor	= 8,
172		.fifo_size		= 16,
173	},
174	[LS2080A] = {
175		.trans_mode		= DSPI_XSPI_MODE,
176		.max_clock_factor	= 8,
177		.fifo_size		= 4,
178	},
179	[LS2085A] = {
180		.trans_mode		= DSPI_XSPI_MODE,
181		.max_clock_factor	= 8,
182		.fifo_size		= 4,
183	},
184	[LX2160A] = {
185		.trans_mode		= DSPI_XSPI_MODE,
186		.max_clock_factor	= 8,
187		.fifo_size		= 4,
188	},
189	[MCF5441X] = {
190		.trans_mode		= DSPI_DMA_MODE,
191		.max_clock_factor	= 8,
192		.fifo_size		= 16,
193	},
194};
195
196struct fsl_dspi_dma {
197	u32					*tx_dma_buf;
198	struct dma_chan				*chan_tx;
199	dma_addr_t				tx_dma_phys;
200	struct completion			cmd_tx_complete;
201	struct dma_async_tx_descriptor		*tx_desc;
202
203	u32					*rx_dma_buf;
204	struct dma_chan				*chan_rx;
205	dma_addr_t				rx_dma_phys;
206	struct completion			cmd_rx_complete;
207	struct dma_async_tx_descriptor		*rx_desc;
208};
209
210struct fsl_dspi {
211	struct spi_controller			*ctlr;
212	struct platform_device			*pdev;
213
214	struct regmap				*regmap;
215	struct regmap				*regmap_pushr;
216	int					irq;
217	struct clk				*clk;
218
219	struct spi_transfer			*cur_transfer;
220	struct spi_message			*cur_msg;
221	struct chip_data			*cur_chip;
222	size_t					progress;
223	size_t					len;
224	const void				*tx;
225	void					*rx;
226	u16					tx_cmd;
227	const struct fsl_dspi_devtype_data	*devtype_data;
228
229	struct completion			xfer_done;
230
231	struct fsl_dspi_dma			*dma;
232
233	int					oper_word_size;
234	int					oper_bits_per_word;
235
236	int					words_in_flight;
237
238	/*
239	 * Offsets for CMD and TXDATA within SPI_PUSHR when accessed
240	 * individually (in XSPI mode)
241	 */
242	int					pushr_cmd;
243	int					pushr_tx;
244
245	void (*host_to_dev)(struct fsl_dspi *dspi, u32 *txdata);
246	void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata);
247};
248
249static void dspi_native_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
250{
251	switch (dspi->oper_word_size) {
252	case 1:
253		*txdata = *(u8 *)dspi->tx;
254		break;
255	case 2:
256		*txdata = *(u16 *)dspi->tx;
257		break;
258	case 4:
259		*txdata = *(u32 *)dspi->tx;
260		break;
261	}
262	dspi->tx += dspi->oper_word_size;
263}
264
265static void dspi_native_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
266{
267	switch (dspi->oper_word_size) {
268	case 1:
269		*(u8 *)dspi->rx = rxdata;
270		break;
271	case 2:
272		*(u16 *)dspi->rx = rxdata;
273		break;
274	case 4:
275		*(u32 *)dspi->rx = rxdata;
276		break;
277	}
278	dspi->rx += dspi->oper_word_size;
279}
280
281static void dspi_8on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
282{
283	*txdata = cpu_to_be32(*(u32 *)dspi->tx);
284	dspi->tx += sizeof(u32);
285}
286
287static void dspi_8on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
288{
289	*(u32 *)dspi->rx = be32_to_cpu(rxdata);
290	dspi->rx += sizeof(u32);
291}
292
293static void dspi_8on16_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
294{
295	*txdata = cpu_to_be16(*(u16 *)dspi->tx);
296	dspi->tx += sizeof(u16);
297}
298
299static void dspi_8on16_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
300{
301	*(u16 *)dspi->rx = be16_to_cpu(rxdata);
302	dspi->rx += sizeof(u16);
303}
304
305static void dspi_16on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
306{
307	u16 hi = *(u16 *)dspi->tx;
308	u16 lo = *(u16 *)(dspi->tx + 2);
309
310	*txdata = (u32)hi << 16 | lo;
311	dspi->tx += sizeof(u32);
312}
313
314static void dspi_16on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
315{
316	u16 hi = rxdata & 0xffff;
317	u16 lo = rxdata >> 16;
318
319	*(u16 *)dspi->rx = lo;
320	*(u16 *)(dspi->rx + 2) = hi;
321	dspi->rx += sizeof(u32);
322}
323
324/*
325 * Pop one word from the TX buffer for pushing into the
326 * PUSHR register (TX FIFO)
327 */
328static u32 dspi_pop_tx(struct fsl_dspi *dspi)
329{
330	u32 txdata = 0;
331
332	if (dspi->tx)
333		dspi->host_to_dev(dspi, &txdata);
334	dspi->len -= dspi->oper_word_size;
335	return txdata;
336}
337
338/* Prepare one TX FIFO entry (txdata plus cmd) */
339static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi)
340{
341	u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi);
342
343	if (spi_controller_is_target(dspi->ctlr))
344		return data;
345
346	if (dspi->len > 0)
347		cmd |= SPI_PUSHR_CMD_CONT;
348	return cmd << 16 | data;
349}
350
351/* Push one word to the RX buffer from the POPR register (RX FIFO) */
352static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata)
353{
354	if (!dspi->rx)
355		return;
356	dspi->dev_to_host(dspi, rxdata);
357}
358
359static void dspi_tx_dma_callback(void *arg)
360{
361	struct fsl_dspi *dspi = arg;
362	struct fsl_dspi_dma *dma = dspi->dma;
363
364	complete(&dma->cmd_tx_complete);
365}
366
367static void dspi_rx_dma_callback(void *arg)
368{
369	struct fsl_dspi *dspi = arg;
370	struct fsl_dspi_dma *dma = dspi->dma;
371	int i;
372
373	if (dspi->rx) {
374		for (i = 0; i < dspi->words_in_flight; i++)
375			dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]);
376	}
377
378	complete(&dma->cmd_rx_complete);
379}
380
381static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
382{
383	struct device *dev = &dspi->pdev->dev;
384	struct fsl_dspi_dma *dma = dspi->dma;
385	int time_left;
386	int i;
387
388	for (i = 0; i < dspi->words_in_flight; i++)
389		dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi);
390
391	dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
392					dma->tx_dma_phys,
393					dspi->words_in_flight *
394					DMA_SLAVE_BUSWIDTH_4_BYTES,
395					DMA_MEM_TO_DEV,
396					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
397	if (!dma->tx_desc) {
398		dev_err(dev, "Not able to get desc for DMA xfer\n");
399		return -EIO;
400	}
401
402	dma->tx_desc->callback = dspi_tx_dma_callback;
403	dma->tx_desc->callback_param = dspi;
404	if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
405		dev_err(dev, "DMA submit failed\n");
406		return -EINVAL;
407	}
408
409	dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
410					dma->rx_dma_phys,
411					dspi->words_in_flight *
412					DMA_SLAVE_BUSWIDTH_4_BYTES,
413					DMA_DEV_TO_MEM,
414					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
415	if (!dma->rx_desc) {
416		dev_err(dev, "Not able to get desc for DMA xfer\n");
417		return -EIO;
418	}
419
420	dma->rx_desc->callback = dspi_rx_dma_callback;
421	dma->rx_desc->callback_param = dspi;
422	if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
423		dev_err(dev, "DMA submit failed\n");
424		return -EINVAL;
425	}
426
427	reinit_completion(&dspi->dma->cmd_rx_complete);
428	reinit_completion(&dspi->dma->cmd_tx_complete);
429
430	dma_async_issue_pending(dma->chan_rx);
431	dma_async_issue_pending(dma->chan_tx);
432
433	if (spi_controller_is_target(dspi->ctlr)) {
434		wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete);
435		return 0;
436	}
437
438	time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
439						DMA_COMPLETION_TIMEOUT);
440	if (time_left == 0) {
441		dev_err(dev, "DMA tx timeout\n");
442		dmaengine_terminate_all(dma->chan_tx);
443		dmaengine_terminate_all(dma->chan_rx);
444		return -ETIMEDOUT;
445	}
446
447	time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
448						DMA_COMPLETION_TIMEOUT);
449	if (time_left == 0) {
450		dev_err(dev, "DMA rx timeout\n");
451		dmaengine_terminate_all(dma->chan_tx);
452		dmaengine_terminate_all(dma->chan_rx);
453		return -ETIMEDOUT;
454	}
455
456	return 0;
457}
458
459static void dspi_setup_accel(struct fsl_dspi *dspi);
460
461static int dspi_dma_xfer(struct fsl_dspi *dspi)
462{
463	struct spi_message *message = dspi->cur_msg;
464	struct device *dev = &dspi->pdev->dev;
465	int ret = 0;
466
467	/*
468	 * dspi->len gets decremented by dspi_pop_tx_pushr in
469	 * dspi_next_xfer_dma_submit
470	 */
471	while (dspi->len) {
472		/* Figure out operational bits-per-word for this chunk */
473		dspi_setup_accel(dspi);
474
475		dspi->words_in_flight = dspi->len / dspi->oper_word_size;
476		if (dspi->words_in_flight > dspi->devtype_data->fifo_size)
477			dspi->words_in_flight = dspi->devtype_data->fifo_size;
478
479		message->actual_length += dspi->words_in_flight *
480					  dspi->oper_word_size;
481
482		ret = dspi_next_xfer_dma_submit(dspi);
483		if (ret) {
484			dev_err(dev, "DMA transfer failed\n");
485			break;
486		}
487	}
488
489	return ret;
490}
491
492static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
493{
494	int dma_bufsize = dspi->devtype_data->fifo_size * 2;
495	struct device *dev = &dspi->pdev->dev;
496	struct dma_slave_config cfg;
497	struct fsl_dspi_dma *dma;
498	int ret;
499
500	dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
501	if (!dma)
502		return -ENOMEM;
503
504	dma->chan_rx = dma_request_chan(dev, "rx");
505	if (IS_ERR(dma->chan_rx)) {
506		return dev_err_probe(dev, PTR_ERR(dma->chan_rx),
507			"rx dma channel not available\n");
508	}
509
510	dma->chan_tx = dma_request_chan(dev, "tx");
511	if (IS_ERR(dma->chan_tx)) {
512		ret = PTR_ERR(dma->chan_tx);
513		dev_err_probe(dev, ret, "tx dma channel not available\n");
514		goto err_tx_channel;
515	}
516
517	dma->tx_dma_buf = dma_alloc_coherent(dma->chan_tx->device->dev,
518					     dma_bufsize, &dma->tx_dma_phys,
519					     GFP_KERNEL);
520	if (!dma->tx_dma_buf) {
521		ret = -ENOMEM;
522		goto err_tx_dma_buf;
523	}
524
525	dma->rx_dma_buf = dma_alloc_coherent(dma->chan_rx->device->dev,
526					     dma_bufsize, &dma->rx_dma_phys,
527					     GFP_KERNEL);
528	if (!dma->rx_dma_buf) {
529		ret = -ENOMEM;
530		goto err_rx_dma_buf;
531	}
532
533	memset(&cfg, 0, sizeof(cfg));
534	cfg.src_addr = phy_addr + SPI_POPR;
535	cfg.dst_addr = phy_addr + SPI_PUSHR;
536	cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
537	cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
538	cfg.src_maxburst = 1;
539	cfg.dst_maxburst = 1;
540
541	cfg.direction = DMA_DEV_TO_MEM;
542	ret = dmaengine_slave_config(dma->chan_rx, &cfg);
543	if (ret) {
544		dev_err(dev, "can't configure rx dma channel\n");
545		ret = -EINVAL;
546		goto err_slave_config;
547	}
548
549	cfg.direction = DMA_MEM_TO_DEV;
550	ret = dmaengine_slave_config(dma->chan_tx, &cfg);
551	if (ret) {
552		dev_err(dev, "can't configure tx dma channel\n");
553		ret = -EINVAL;
554		goto err_slave_config;
555	}
556
557	dspi->dma = dma;
558	init_completion(&dma->cmd_tx_complete);
559	init_completion(&dma->cmd_rx_complete);
560
561	return 0;
562
563err_slave_config:
564	dma_free_coherent(dma->chan_rx->device->dev,
565			  dma_bufsize, dma->rx_dma_buf, dma->rx_dma_phys);
566err_rx_dma_buf:
567	dma_free_coherent(dma->chan_tx->device->dev,
568			  dma_bufsize, dma->tx_dma_buf, dma->tx_dma_phys);
569err_tx_dma_buf:
570	dma_release_channel(dma->chan_tx);
571err_tx_channel:
572	dma_release_channel(dma->chan_rx);
573
574	devm_kfree(dev, dma);
575	dspi->dma = NULL;
576
577	return ret;
578}
579
580static void dspi_release_dma(struct fsl_dspi *dspi)
581{
582	int dma_bufsize = dspi->devtype_data->fifo_size * 2;
583	struct fsl_dspi_dma *dma = dspi->dma;
584
585	if (!dma)
586		return;
587
588	if (dma->chan_tx) {
589		dma_free_coherent(dma->chan_tx->device->dev, dma_bufsize,
590				  dma->tx_dma_buf, dma->tx_dma_phys);
591		dma_release_channel(dma->chan_tx);
592	}
593
594	if (dma->chan_rx) {
595		dma_free_coherent(dma->chan_rx->device->dev, dma_bufsize,
596				  dma->rx_dma_buf, dma->rx_dma_phys);
597		dma_release_channel(dma->chan_rx);
598	}
599}
600
601static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
602			   unsigned long clkrate)
603{
604	/* Valid baud rate pre-scaler values */
605	int pbr_tbl[4] = {2, 3, 5, 7};
606	int brs[16] = {	2,	4,	6,	8,
607			16,	32,	64,	128,
608			256,	512,	1024,	2048,
609			4096,	8192,	16384,	32768 };
610	int scale_needed, scale, minscale = INT_MAX;
611	int i, j;
612
613	scale_needed = clkrate / speed_hz;
614	if (clkrate % speed_hz)
615		scale_needed++;
616
617	for (i = 0; i < ARRAY_SIZE(brs); i++)
618		for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
619			scale = brs[i] * pbr_tbl[j];
620			if (scale >= scale_needed) {
621				if (scale < minscale) {
622					minscale = scale;
623					*br = i;
624					*pbr = j;
625				}
626				break;
627			}
628		}
629
630	if (minscale == INT_MAX) {
631		pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
632			speed_hz, clkrate);
633		*pbr = ARRAY_SIZE(pbr_tbl) - 1;
634		*br =  ARRAY_SIZE(brs) - 1;
635	}
636}
637
638static void ns_delay_scale(char *psc, char *sc, int delay_ns,
639			   unsigned long clkrate)
640{
641	int scale_needed, scale, minscale = INT_MAX;
642	int pscale_tbl[4] = {1, 3, 5, 7};
643	u32 remainder;
644	int i, j;
645
646	scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
647				   &remainder);
648	if (remainder)
649		scale_needed++;
650
651	for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
652		for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
653			scale = pscale_tbl[i] * (2 << j);
654			if (scale >= scale_needed) {
655				if (scale < minscale) {
656					minscale = scale;
657					*psc = i;
658					*sc = j;
659				}
660				break;
661			}
662		}
663
664	if (minscale == INT_MAX) {
665		pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
666			delay_ns, clkrate);
667		*psc = ARRAY_SIZE(pscale_tbl) - 1;
668		*sc = SPI_CTAR_SCALE_BITS;
669	}
670}
671
672static void dspi_pushr_cmd_write(struct fsl_dspi *dspi, u16 cmd)
673{
674	/*
675	 * The only time when the PCS doesn't need continuation after this word
676	 * is when it's last. We need to look ahead, because we actually call
677	 * dspi_pop_tx (the function that decrements dspi->len) _after_
678	 * dspi_pushr_cmd_write with XSPI mode. As for how much in advance? One
679	 * word is enough. If there's more to transmit than that,
680	 * dspi_xspi_write will know to split the FIFO writes in 2, and
681	 * generate a new PUSHR command with the final word that will have PCS
682	 * deasserted (not continued) here.
683	 */
684	if (dspi->len > dspi->oper_word_size)
685		cmd |= SPI_PUSHR_CMD_CONT;
686	regmap_write(dspi->regmap_pushr, dspi->pushr_cmd, cmd);
687}
688
689static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata)
690{
691	regmap_write(dspi->regmap_pushr, dspi->pushr_tx, txdata);
692}
693
694static void dspi_xspi_fifo_write(struct fsl_dspi *dspi, int num_words)
695{
696	int num_bytes = num_words * dspi->oper_word_size;
697	u16 tx_cmd = dspi->tx_cmd;
698
699	/*
700	 * If the PCS needs to de-assert (i.e. we're at the end of the buffer
701	 * and cs_change does not want the PCS to stay on), then we need a new
702	 * PUSHR command, since this one (for the body of the buffer)
703	 * necessarily has the CONT bit set.
704	 * So send one word less during this go, to force a split and a command
705	 * with a single word next time, when CONT will be unset.
706	 */
707	if (!(dspi->tx_cmd & SPI_PUSHR_CMD_CONT) && num_bytes == dspi->len)
708		tx_cmd |= SPI_PUSHR_CMD_EOQ;
709
710	/* Update CTARE */
711	regmap_write(dspi->regmap, SPI_CTARE(0),
712		     SPI_FRAME_EBITS(dspi->oper_bits_per_word) |
713		     SPI_CTARE_DTCP(num_words));
714
715	/*
716	 * Write the CMD FIFO entry first, and then the two
717	 * corresponding TX FIFO entries (or one...).
718	 */
719	dspi_pushr_cmd_write(dspi, tx_cmd);
720
721	/* Fill TX FIFO with as many transfers as possible */
722	while (num_words--) {
723		u32 data = dspi_pop_tx(dspi);
724
725		dspi_pushr_txdata_write(dspi, data & 0xFFFF);
726		if (dspi->oper_bits_per_word > 16)
727			dspi_pushr_txdata_write(dspi, data >> 16);
728	}
729}
730
731static u32 dspi_popr_read(struct fsl_dspi *dspi)
732{
733	u32 rxdata = 0;
734
735	regmap_read(dspi->regmap, SPI_POPR, &rxdata);
736	return rxdata;
737}
738
739static void dspi_fifo_read(struct fsl_dspi *dspi)
740{
741	int num_fifo_entries = dspi->words_in_flight;
742
743	/* Read one FIFO entry and push to rx buffer */
744	while (num_fifo_entries--)
745		dspi_push_rx(dspi, dspi_popr_read(dspi));
746}
747
748static void dspi_setup_accel(struct fsl_dspi *dspi)
749{
750	struct spi_transfer *xfer = dspi->cur_transfer;
751	bool odd = !!(dspi->len & 1);
752
753	/* No accel for frames not multiple of 8 bits at the moment */
754	if (xfer->bits_per_word % 8)
755		goto no_accel;
756
757	if (!odd && dspi->len <= dspi->devtype_data->fifo_size * 2) {
758		dspi->oper_bits_per_word = 16;
759	} else if (odd && dspi->len <= dspi->devtype_data->fifo_size) {
760		dspi->oper_bits_per_word = 8;
761	} else {
762		/* Start off with maximum supported by hardware */
763		if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
764			dspi->oper_bits_per_word = 32;
765		else
766			dspi->oper_bits_per_word = 16;
767
768		/*
769		 * And go down only if the buffer can't be sent with
770		 * words this big
771		 */
772		do {
773			if (dspi->len >= DIV_ROUND_UP(dspi->oper_bits_per_word, 8))
774				break;
775
776			dspi->oper_bits_per_word /= 2;
777		} while (dspi->oper_bits_per_word > 8);
778	}
779
780	if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 32) {
781		dspi->dev_to_host = dspi_8on32_dev_to_host;
782		dspi->host_to_dev = dspi_8on32_host_to_dev;
783	} else if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 16) {
784		dspi->dev_to_host = dspi_8on16_dev_to_host;
785		dspi->host_to_dev = dspi_8on16_host_to_dev;
786	} else if (xfer->bits_per_word == 16 && dspi->oper_bits_per_word == 32) {
787		dspi->dev_to_host = dspi_16on32_dev_to_host;
788		dspi->host_to_dev = dspi_16on32_host_to_dev;
789	} else {
790no_accel:
791		dspi->dev_to_host = dspi_native_dev_to_host;
792		dspi->host_to_dev = dspi_native_host_to_dev;
793		dspi->oper_bits_per_word = xfer->bits_per_word;
794	}
795
796	dspi->oper_word_size = DIV_ROUND_UP(dspi->oper_bits_per_word, 8);
797
798	/*
799	 * Update CTAR here (code is common for XSPI and DMA modes).
800	 * We will update CTARE in the portion specific to XSPI, when we
801	 * also know the preload value (DTCP).
802	 */
803	regmap_write(dspi->regmap, SPI_CTAR(0),
804		     dspi->cur_chip->ctar_val |
805		     SPI_FRAME_BITS(dspi->oper_bits_per_word));
806}
807
808static void dspi_fifo_write(struct fsl_dspi *dspi)
809{
810	int num_fifo_entries = dspi->devtype_data->fifo_size;
811	struct spi_transfer *xfer = dspi->cur_transfer;
812	struct spi_message *msg = dspi->cur_msg;
813	int num_words, num_bytes;
814
815	dspi_setup_accel(dspi);
816
817	/* In XSPI mode each 32-bit word occupies 2 TX FIFO entries */
818	if (dspi->oper_word_size == 4)
819		num_fifo_entries /= 2;
820
821	/*
822	 * Integer division intentionally trims off odd (or non-multiple of 4)
823	 * numbers of bytes at the end of the buffer, which will be sent next
824	 * time using a smaller oper_word_size.
825	 */
826	num_words = dspi->len / dspi->oper_word_size;
827	if (num_words > num_fifo_entries)
828		num_words = num_fifo_entries;
829
830	/* Update total number of bytes that were transferred */
831	num_bytes = num_words * dspi->oper_word_size;
832	msg->actual_length += num_bytes;
833	dspi->progress += num_bytes / DIV_ROUND_UP(xfer->bits_per_word, 8);
834
835	/*
836	 * Update shared variable for use in the next interrupt (both in
837	 * dspi_fifo_read and in dspi_fifo_write).
838	 */
839	dspi->words_in_flight = num_words;
840
841	spi_take_timestamp_pre(dspi->ctlr, xfer, dspi->progress, !dspi->irq);
842
843	dspi_xspi_fifo_write(dspi, num_words);
844	/*
845	 * Everything after this point is in a potential race with the next
846	 * interrupt, so we must never use dspi->words_in_flight again since it
847	 * might already be modified by the next dspi_fifo_write.
848	 */
849
850	spi_take_timestamp_post(dspi->ctlr, dspi->cur_transfer,
851				dspi->progress, !dspi->irq);
852}
853
854static int dspi_rxtx(struct fsl_dspi *dspi)
855{
856	dspi_fifo_read(dspi);
857
858	if (!dspi->len)
859		/* Success! */
860		return 0;
861
862	dspi_fifo_write(dspi);
863
864	return -EINPROGRESS;
865}
866
867static int dspi_poll(struct fsl_dspi *dspi)
868{
869	int tries = 1000;
870	u32 spi_sr;
871
872	do {
873		regmap_read(dspi->regmap, SPI_SR, &spi_sr);
874		regmap_write(dspi->regmap, SPI_SR, spi_sr);
875
876		if (spi_sr & SPI_SR_CMDTCF)
877			break;
878	} while (--tries);
879
880	if (!tries)
881		return -ETIMEDOUT;
882
883	return dspi_rxtx(dspi);
884}
885
886static irqreturn_t dspi_interrupt(int irq, void *dev_id)
887{
888	struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
889	u32 spi_sr;
890
891	regmap_read(dspi->regmap, SPI_SR, &spi_sr);
892	regmap_write(dspi->regmap, SPI_SR, spi_sr);
893
894	if (!(spi_sr & SPI_SR_CMDTCF))
895		return IRQ_NONE;
896
897	if (dspi_rxtx(dspi) == 0)
898		complete(&dspi->xfer_done);
899
900	return IRQ_HANDLED;
901}
902
903static void dspi_assert_cs(struct spi_device *spi, bool *cs)
904{
905	if (!spi_get_csgpiod(spi, 0) || *cs)
906		return;
907
908	gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), true);
909	*cs = true;
910}
911
912static void dspi_deassert_cs(struct spi_device *spi, bool *cs)
913{
914	if (!spi_get_csgpiod(spi, 0) || !*cs)
915		return;
916
917	gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), false);
918	*cs = false;
919}
920
921static int dspi_transfer_one_message(struct spi_controller *ctlr,
922				     struct spi_message *message)
923{
924	struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
925	struct spi_device *spi = message->spi;
926	struct spi_transfer *transfer;
927	bool cs = false;
928	int status = 0;
929
930	message->actual_length = 0;
931
932	list_for_each_entry(transfer, &message->transfers, transfer_list) {
933		dspi->cur_transfer = transfer;
934		dspi->cur_msg = message;
935		dspi->cur_chip = spi_get_ctldata(spi);
936
937		dspi_assert_cs(spi, &cs);
938
939		/* Prepare command word for CMD FIFO */
940		dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0);
941		if (!spi_get_csgpiod(spi, 0))
942			dspi->tx_cmd |= SPI_PUSHR_CMD_PCS(spi_get_chipselect(spi, 0));
943
944		if (list_is_last(&dspi->cur_transfer->transfer_list,
945				 &dspi->cur_msg->transfers)) {
946			/* Leave PCS activated after last transfer when
947			 * cs_change is set.
948			 */
949			if (transfer->cs_change)
950				dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
951		} else {
952			/* Keep PCS active between transfers in same message
953			 * when cs_change is not set, and de-activate PCS
954			 * between transfers in the same message when
955			 * cs_change is set.
956			 */
957			if (!transfer->cs_change)
958				dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
959		}
960
961		dspi->tx = transfer->tx_buf;
962		dspi->rx = transfer->rx_buf;
963		dspi->len = transfer->len;
964		dspi->progress = 0;
965
966		regmap_update_bits(dspi->regmap, SPI_MCR,
967				   SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
968				   SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
969
970		spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer,
971				       dspi->progress, !dspi->irq);
972
973		if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
974			status = dspi_dma_xfer(dspi);
975		} else {
976			dspi_fifo_write(dspi);
977
978			if (dspi->irq) {
979				wait_for_completion(&dspi->xfer_done);
980				reinit_completion(&dspi->xfer_done);
981			} else {
982				do {
983					status = dspi_poll(dspi);
984				} while (status == -EINPROGRESS);
985			}
986		}
987		if (status)
988			break;
989
990		spi_transfer_delay_exec(transfer);
991
992		if (!(dspi->tx_cmd & SPI_PUSHR_CMD_CONT))
993			dspi_deassert_cs(spi, &cs);
994	}
995
996	message->status = status;
997	spi_finalize_current_message(ctlr);
998
999	return status;
1000}
1001
1002static int dspi_setup(struct spi_device *spi)
1003{
1004	struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
1005	u32 period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->max_speed_hz);
1006	unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
1007	u32 quarter_period_ns = DIV_ROUND_UP(period_ns, 4);
1008	u32 cs_sck_delay = 0, sck_cs_delay = 0;
1009	struct fsl_dspi_platform_data *pdata;
1010	unsigned char pasc = 0, asc = 0;
1011	struct chip_data *chip;
1012	unsigned long clkrate;
1013	bool cs = true;
1014
1015	/* Only alloc on first setup */
1016	chip = spi_get_ctldata(spi);
1017	if (chip == NULL) {
1018		chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1019		if (!chip)
1020			return -ENOMEM;
1021	}
1022
1023	pdata = dev_get_platdata(&dspi->pdev->dev);
1024
1025	if (!pdata) {
1026		of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
1027				     &cs_sck_delay);
1028
1029		of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
1030				     &sck_cs_delay);
1031	} else {
1032		cs_sck_delay = pdata->cs_sck_delay;
1033		sck_cs_delay = pdata->sck_cs_delay;
1034	}
1035
1036	/* Since tCSC and tASC apply to continuous transfers too, avoid SCK
1037	 * glitches of half a cycle by never allowing tCSC + tASC to go below
1038	 * half a SCK period.
1039	 */
1040	if (cs_sck_delay < quarter_period_ns)
1041		cs_sck_delay = quarter_period_ns;
1042	if (sck_cs_delay < quarter_period_ns)
1043		sck_cs_delay = quarter_period_ns;
1044
1045	dev_dbg(&spi->dev,
1046		"DSPI controller timing params: CS-to-SCK delay %u ns, SCK-to-CS delay %u ns\n",
1047		cs_sck_delay, sck_cs_delay);
1048
1049	clkrate = clk_get_rate(dspi->clk);
1050	hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
1051
1052	/* Set PCS to SCK delay scale values */
1053	ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
1054
1055	/* Set After SCK delay scale values */
1056	ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
1057
1058	chip->ctar_val = 0;
1059	if (spi->mode & SPI_CPOL)
1060		chip->ctar_val |= SPI_CTAR_CPOL;
1061	if (spi->mode & SPI_CPHA)
1062		chip->ctar_val |= SPI_CTAR_CPHA;
1063
1064	if (!spi_controller_is_target(dspi->ctlr)) {
1065		chip->ctar_val |= SPI_CTAR_PCSSCK(pcssck) |
1066				  SPI_CTAR_CSSCK(cssck) |
1067				  SPI_CTAR_PASC(pasc) |
1068				  SPI_CTAR_ASC(asc) |
1069				  SPI_CTAR_PBR(pbr) |
1070				  SPI_CTAR_BR(br);
1071
1072		if (spi->mode & SPI_LSB_FIRST)
1073			chip->ctar_val |= SPI_CTAR_LSBFE;
1074	}
1075
1076	gpiod_direction_output(spi_get_csgpiod(spi, 0), false);
1077	dspi_deassert_cs(spi, &cs);
1078
1079	spi_set_ctldata(spi, chip);
1080
1081	return 0;
1082}
1083
1084static void dspi_cleanup(struct spi_device *spi)
1085{
1086	struct chip_data *chip = spi_get_ctldata(spi);
1087
1088	dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
1089		spi->controller->bus_num, spi_get_chipselect(spi, 0));
1090
1091	kfree(chip);
1092}
1093
1094static const struct of_device_id fsl_dspi_dt_ids[] = {
1095	{
1096		.compatible = "fsl,vf610-dspi",
1097		.data = &devtype_data[VF610],
1098	}, {
1099		.compatible = "fsl,ls1021a-v1.0-dspi",
1100		.data = &devtype_data[LS1021A],
1101	}, {
1102		.compatible = "fsl,ls1012a-dspi",
1103		.data = &devtype_data[LS1012A],
1104	}, {
1105		.compatible = "fsl,ls1028a-dspi",
1106		.data = &devtype_data[LS1028A],
1107	}, {
1108		.compatible = "fsl,ls1043a-dspi",
1109		.data = &devtype_data[LS1043A],
1110	}, {
1111		.compatible = "fsl,ls1046a-dspi",
1112		.data = &devtype_data[LS1046A],
1113	}, {
1114		.compatible = "fsl,ls2080a-dspi",
1115		.data = &devtype_data[LS2080A],
1116	}, {
1117		.compatible = "fsl,ls2085a-dspi",
1118		.data = &devtype_data[LS2085A],
1119	}, {
1120		.compatible = "fsl,lx2160a-dspi",
1121		.data = &devtype_data[LX2160A],
1122	},
1123	{ /* sentinel */ }
1124};
1125MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
1126
1127#ifdef CONFIG_PM_SLEEP
1128static int dspi_suspend(struct device *dev)
1129{
1130	struct fsl_dspi *dspi = dev_get_drvdata(dev);
1131
1132	if (dspi->irq)
1133		disable_irq(dspi->irq);
1134	spi_controller_suspend(dspi->ctlr);
1135	clk_disable_unprepare(dspi->clk);
1136
1137	pinctrl_pm_select_sleep_state(dev);
1138
1139	return 0;
1140}
1141
1142static int dspi_resume(struct device *dev)
1143{
1144	struct fsl_dspi *dspi = dev_get_drvdata(dev);
1145	int ret;
1146
1147	pinctrl_pm_select_default_state(dev);
1148
1149	ret = clk_prepare_enable(dspi->clk);
1150	if (ret)
1151		return ret;
1152	spi_controller_resume(dspi->ctlr);
1153	if (dspi->irq)
1154		enable_irq(dspi->irq);
1155
1156	return 0;
1157}
1158#endif /* CONFIG_PM_SLEEP */
1159
1160static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
1161
1162static const struct regmap_range dspi_volatile_ranges[] = {
1163	regmap_reg_range(SPI_MCR, SPI_TCR),
1164	regmap_reg_range(SPI_SR, SPI_SR),
1165	regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
1166};
1167
1168static const struct regmap_access_table dspi_volatile_table = {
1169	.yes_ranges	= dspi_volatile_ranges,
1170	.n_yes_ranges	= ARRAY_SIZE(dspi_volatile_ranges),
1171};
1172
1173static const struct regmap_config dspi_regmap_config = {
1174	.reg_bits	= 32,
1175	.val_bits	= 32,
1176	.reg_stride	= 4,
1177	.max_register	= 0x88,
1178	.volatile_table	= &dspi_volatile_table,
1179};
1180
1181static const struct regmap_range dspi_xspi_volatile_ranges[] = {
1182	regmap_reg_range(SPI_MCR, SPI_TCR),
1183	regmap_reg_range(SPI_SR, SPI_SR),
1184	regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
1185	regmap_reg_range(SPI_SREX, SPI_SREX),
1186};
1187
1188static const struct regmap_access_table dspi_xspi_volatile_table = {
1189	.yes_ranges	= dspi_xspi_volatile_ranges,
1190	.n_yes_ranges	= ARRAY_SIZE(dspi_xspi_volatile_ranges),
1191};
1192
1193static const struct regmap_config dspi_xspi_regmap_config[] = {
1194	{
1195		.reg_bits	= 32,
1196		.val_bits	= 32,
1197		.reg_stride	= 4,
1198		.max_register	= 0x13c,
1199		.volatile_table	= &dspi_xspi_volatile_table,
1200	},
1201	{
1202		.name		= "pushr",
1203		.reg_bits	= 16,
1204		.val_bits	= 16,
1205		.reg_stride	= 2,
1206		.max_register	= 0x2,
1207	},
1208};
1209
1210static int dspi_init(struct fsl_dspi *dspi)
1211{
1212	unsigned int mcr;
1213
1214	/* Set idle states for all chip select signals to high */
1215	mcr = SPI_MCR_PCSIS(GENMASK(dspi->ctlr->max_native_cs - 1, 0));
1216
1217	if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1218		mcr |= SPI_MCR_XSPI;
1219	if (!spi_controller_is_target(dspi->ctlr))
1220		mcr |= SPI_MCR_HOST;
1221
1222	regmap_write(dspi->regmap, SPI_MCR, mcr);
1223	regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
1224
1225	switch (dspi->devtype_data->trans_mode) {
1226	case DSPI_XSPI_MODE:
1227		regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE);
1228		break;
1229	case DSPI_DMA_MODE:
1230		regmap_write(dspi->regmap, SPI_RSER,
1231			     SPI_RSER_TFFFE | SPI_RSER_TFFFD |
1232			     SPI_RSER_RFDFE | SPI_RSER_RFDFD);
1233		break;
1234	default:
1235		dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
1236			dspi->devtype_data->trans_mode);
1237		return -EINVAL;
1238	}
1239
1240	return 0;
1241}
1242
1243static int dspi_target_abort(struct spi_controller *host)
1244{
1245	struct fsl_dspi *dspi = spi_controller_get_devdata(host);
1246
1247	/*
1248	 * Terminate all pending DMA transactions for the SPI working
1249	 * in TARGET mode.
1250	 */
1251	if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1252		dmaengine_terminate_sync(dspi->dma->chan_rx);
1253		dmaengine_terminate_sync(dspi->dma->chan_tx);
1254	}
1255
1256	/* Clear the internal DSPI RX and TX FIFO buffers */
1257	regmap_update_bits(dspi->regmap, SPI_MCR,
1258			   SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
1259			   SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
1260
1261	return 0;
1262}
1263
1264static int dspi_probe(struct platform_device *pdev)
1265{
1266	struct device_node *np = pdev->dev.of_node;
1267	const struct regmap_config *regmap_config;
1268	struct fsl_dspi_platform_data *pdata;
1269	struct spi_controller *ctlr;
1270	int ret, cs_num, bus_num = -1;
1271	struct fsl_dspi *dspi;
1272	struct resource *res;
1273	void __iomem *base;
1274	bool big_endian;
1275
1276	dspi = devm_kzalloc(&pdev->dev, sizeof(*dspi), GFP_KERNEL);
1277	if (!dspi)
1278		return -ENOMEM;
1279
1280	ctlr = spi_alloc_host(&pdev->dev, 0);
1281	if (!ctlr)
1282		return -ENOMEM;
1283
1284	spi_controller_set_devdata(ctlr, dspi);
1285	platform_set_drvdata(pdev, dspi);
1286
1287	dspi->pdev = pdev;
1288	dspi->ctlr = ctlr;
1289
1290	ctlr->setup = dspi_setup;
1291	ctlr->transfer_one_message = dspi_transfer_one_message;
1292	ctlr->dev.of_node = pdev->dev.of_node;
1293
1294	ctlr->cleanup = dspi_cleanup;
1295	ctlr->target_abort = dspi_target_abort;
1296	ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1297	ctlr->use_gpio_descriptors = true;
1298
1299	pdata = dev_get_platdata(&pdev->dev);
1300	if (pdata) {
1301		ctlr->num_chipselect = ctlr->max_native_cs = pdata->cs_num;
1302		ctlr->bus_num = pdata->bus_num;
1303
1304		/* Only Coldfire uses platform data */
1305		dspi->devtype_data = &devtype_data[MCF5441X];
1306		big_endian = true;
1307	} else {
1308
1309		ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
1310		if (ret < 0) {
1311			dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
1312			goto out_ctlr_put;
1313		}
1314		ctlr->num_chipselect = ctlr->max_native_cs = cs_num;
1315
1316		of_property_read_u32(np, "bus-num", &bus_num);
1317		ctlr->bus_num = bus_num;
1318
1319		if (of_property_read_bool(np, "spi-slave"))
1320			ctlr->target = true;
1321
1322		dspi->devtype_data = of_device_get_match_data(&pdev->dev);
1323		if (!dspi->devtype_data) {
1324			dev_err(&pdev->dev, "can't get devtype_data\n");
1325			ret = -EFAULT;
1326			goto out_ctlr_put;
1327		}
1328
1329		big_endian = of_device_is_big_endian(np);
1330	}
1331	if (big_endian) {
1332		dspi->pushr_cmd = 0;
1333		dspi->pushr_tx = 2;
1334	} else {
1335		dspi->pushr_cmd = 2;
1336		dspi->pushr_tx = 0;
1337	}
1338
1339	if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1340		ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1341	else
1342		ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1343
1344	base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1345	if (IS_ERR(base)) {
1346		ret = PTR_ERR(base);
1347		goto out_ctlr_put;
1348	}
1349
1350	if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1351		regmap_config = &dspi_xspi_regmap_config[0];
1352	else
1353		regmap_config = &dspi_regmap_config;
1354	dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config);
1355	if (IS_ERR(dspi->regmap)) {
1356		dev_err(&pdev->dev, "failed to init regmap: %ld\n",
1357				PTR_ERR(dspi->regmap));
1358		ret = PTR_ERR(dspi->regmap);
1359		goto out_ctlr_put;
1360	}
1361
1362	if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) {
1363		dspi->regmap_pushr = devm_regmap_init_mmio(
1364			&pdev->dev, base + SPI_PUSHR,
1365			&dspi_xspi_regmap_config[1]);
1366		if (IS_ERR(dspi->regmap_pushr)) {
1367			dev_err(&pdev->dev,
1368				"failed to init pushr regmap: %ld\n",
1369				PTR_ERR(dspi->regmap_pushr));
1370			ret = PTR_ERR(dspi->regmap_pushr);
1371			goto out_ctlr_put;
1372		}
1373	}
1374
1375	dspi->clk = devm_clk_get(&pdev->dev, "dspi");
1376	if (IS_ERR(dspi->clk)) {
1377		ret = PTR_ERR(dspi->clk);
1378		dev_err(&pdev->dev, "unable to get clock\n");
1379		goto out_ctlr_put;
1380	}
1381	ret = clk_prepare_enable(dspi->clk);
1382	if (ret)
1383		goto out_ctlr_put;
1384
1385	ret = dspi_init(dspi);
1386	if (ret)
1387		goto out_clk_put;
1388
1389	dspi->irq = platform_get_irq(pdev, 0);
1390	if (dspi->irq <= 0) {
1391		dev_info(&pdev->dev,
1392			 "can't get platform irq, using poll mode\n");
1393		dspi->irq = 0;
1394		goto poll_mode;
1395	}
1396
1397	init_completion(&dspi->xfer_done);
1398
1399	ret = request_threaded_irq(dspi->irq, dspi_interrupt, NULL,
1400				   IRQF_SHARED, pdev->name, dspi);
1401	if (ret < 0) {
1402		dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
1403		goto out_clk_put;
1404	}
1405
1406poll_mode:
1407
1408	if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1409		ret = dspi_request_dma(dspi, res->start);
1410		if (ret < 0) {
1411			dev_err(&pdev->dev, "can't get dma channels\n");
1412			goto out_free_irq;
1413		}
1414	}
1415
1416	ctlr->max_speed_hz =
1417		clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
1418
1419	if (dspi->devtype_data->trans_mode != DSPI_DMA_MODE)
1420		ctlr->ptp_sts_supported = true;
1421
1422	ret = spi_register_controller(ctlr);
1423	if (ret != 0) {
1424		dev_err(&pdev->dev, "Problem registering DSPI ctlr\n");
1425		goto out_release_dma;
1426	}
1427
1428	return ret;
1429
1430out_release_dma:
1431	dspi_release_dma(dspi);
1432out_free_irq:
1433	if (dspi->irq)
1434		free_irq(dspi->irq, dspi);
1435out_clk_put:
1436	clk_disable_unprepare(dspi->clk);
1437out_ctlr_put:
1438	spi_controller_put(ctlr);
1439
1440	return ret;
1441}
1442
1443static void dspi_remove(struct platform_device *pdev)
1444{
1445	struct fsl_dspi *dspi = platform_get_drvdata(pdev);
1446
1447	/* Disconnect from the SPI framework */
1448	spi_unregister_controller(dspi->ctlr);
1449
1450	/* Disable RX and TX */
1451	regmap_update_bits(dspi->regmap, SPI_MCR,
1452			   SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF,
1453			   SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF);
1454
1455	/* Stop Running */
1456	regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_HALT, SPI_MCR_HALT);
1457
1458	dspi_release_dma(dspi);
1459	if (dspi->irq)
1460		free_irq(dspi->irq, dspi);
1461	clk_disable_unprepare(dspi->clk);
1462}
1463
1464static void dspi_shutdown(struct platform_device *pdev)
1465{
1466	dspi_remove(pdev);
1467}
1468
1469static struct platform_driver fsl_dspi_driver = {
1470	.driver.name		= DRIVER_NAME,
1471	.driver.of_match_table	= fsl_dspi_dt_ids,
1472	.driver.owner		= THIS_MODULE,
1473	.driver.pm		= &dspi_pm,
1474	.probe			= dspi_probe,
1475	.remove_new		= dspi_remove,
1476	.shutdown		= dspi_shutdown,
1477};
1478module_platform_driver(fsl_dspi_driver);
1479
1480MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
1481MODULE_LICENSE("GPL");
1482MODULE_ALIAS("platform:" DRIVER_NAME);
1483