1/*
2 * Allwinner SoCs SRAM Controller Driver
3 *
4 * Copyright (C) 2015 Maxime Ripard
5 *
6 * Author: Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2.  This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/debugfs.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_platform.h>
19#include <linux/platform_device.h>
20#include <linux/regmap.h>
21
22#include <linux/soc/sunxi/sunxi_sram.h>
23
24struct sunxi_sram_func {
25	char	*func;
26	u8	val;
27	u32	reg_val;
28};
29
30struct sunxi_sram_data {
31	char			*name;
32	u8			reg;
33	u8			offset;
34	u8			width;
35	struct sunxi_sram_func	*func;
36	struct list_head	list;
37};
38
39struct sunxi_sram_desc {
40	struct sunxi_sram_data	data;
41	bool			claimed;
42};
43
44#define SUNXI_SRAM_MAP(_reg_val, _val, _func)			\
45	{							\
46		.func = _func,					\
47		.val = _val,					\
48		.reg_val = _reg_val,				\
49	}
50
51#define SUNXI_SRAM_DATA(_name, _reg, _off, _width, ...)		\
52	{							\
53		.name = _name,					\
54		.reg = _reg,					\
55		.offset = _off,					\
56		.width = _width,				\
57		.func = (struct sunxi_sram_func[]){		\
58			__VA_ARGS__, { } },			\
59	}
60
61static struct sunxi_sram_desc sun4i_a10_sram_a3_a4 = {
62	.data	= SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2,
63				  SUNXI_SRAM_MAP(0, 0, "cpu"),
64				  SUNXI_SRAM_MAP(1, 1, "emac")),
65};
66
67static struct sunxi_sram_desc sun4i_a10_sram_c1 = {
68	.data	= SUNXI_SRAM_DATA("C1", 0x0, 0x0, 31,
69				  SUNXI_SRAM_MAP(0, 0, "cpu"),
70				  SUNXI_SRAM_MAP(0x7fffffff, 1, "ve")),
71};
72
73static struct sunxi_sram_desc sun4i_a10_sram_d = {
74	.data	= SUNXI_SRAM_DATA("D", 0x4, 0x0, 1,
75				  SUNXI_SRAM_MAP(0, 0, "cpu"),
76				  SUNXI_SRAM_MAP(1, 1, "usb-otg")),
77};
78
79static struct sunxi_sram_desc sun50i_a64_sram_c = {
80	.data	= SUNXI_SRAM_DATA("C", 0x4, 24, 1,
81				  SUNXI_SRAM_MAP(1, 0, "cpu"),
82				  SUNXI_SRAM_MAP(0, 1, "de2")),
83};
84
85static const struct of_device_id sunxi_sram_dt_ids[] = {
86	{
87		.compatible	= "allwinner,sun4i-a10-sram-a3-a4",
88		.data		= &sun4i_a10_sram_a3_a4.data,
89	},
90	{
91		.compatible	= "allwinner,sun4i-a10-sram-c1",
92		.data		= &sun4i_a10_sram_c1.data,
93	},
94	{
95		.compatible	= "allwinner,sun4i-a10-sram-d",
96		.data		= &sun4i_a10_sram_d.data,
97	},
98	{
99		.compatible	= "allwinner,sun50i-a64-sram-c",
100		.data		= &sun50i_a64_sram_c.data,
101	},
102	{}
103};
104
105static struct device *sram_dev;
106static LIST_HEAD(claimed_sram);
107static DEFINE_SPINLOCK(sram_lock);
108static void __iomem *base;
109
110static int sunxi_sram_show(struct seq_file *s, void *data)
111{
112	struct device_node *sram_node, *section_node;
113	const struct sunxi_sram_data *sram_data;
114	const struct of_device_id *match;
115	struct sunxi_sram_func *func;
116	const __be32 *sram_addr_p, *section_addr_p;
117	u32 val;
118
119	seq_puts(s, "Allwinner sunXi SRAM\n");
120	seq_puts(s, "--------------------\n\n");
121
122	for_each_child_of_node(sram_dev->of_node, sram_node) {
123		if (!of_device_is_compatible(sram_node, "mmio-sram"))
124			continue;
125
126		sram_addr_p = of_get_address(sram_node, 0, NULL, NULL);
127
128		seq_printf(s, "sram@%08x\n",
129			   be32_to_cpu(*sram_addr_p));
130
131		for_each_child_of_node(sram_node, section_node) {
132			match = of_match_node(sunxi_sram_dt_ids, section_node);
133			if (!match)
134				continue;
135			sram_data = match->data;
136
137			section_addr_p = of_get_address(section_node, 0,
138							NULL, NULL);
139
140			seq_printf(s, "\tsection@%04x\t(%s)\n",
141				   be32_to_cpu(*section_addr_p),
142				   sram_data->name);
143
144			val = readl(base + sram_data->reg);
145			val >>= sram_data->offset;
146			val &= GENMASK(sram_data->width - 1, 0);
147
148			for (func = sram_data->func; func->func; func++) {
149				seq_printf(s, "\t\t%s%c\n", func->func,
150					   func->reg_val == val ?
151					   '*' : ' ');
152			}
153		}
154
155		seq_puts(s, "\n");
156	}
157
158	return 0;
159}
160
161DEFINE_SHOW_ATTRIBUTE(sunxi_sram);
162
163static inline struct sunxi_sram_desc *to_sram_desc(const struct sunxi_sram_data *data)
164{
165	return container_of(data, struct sunxi_sram_desc, data);
166}
167
168static const struct sunxi_sram_data *sunxi_sram_of_parse(struct device_node *node,
169							 unsigned int *reg_value)
170{
171	const struct of_device_id *match;
172	const struct sunxi_sram_data *data;
173	struct sunxi_sram_func *func;
174	struct of_phandle_args args;
175	u8 val;
176	int ret;
177
178	ret = of_parse_phandle_with_fixed_args(node, "allwinner,sram", 1, 0,
179					       &args);
180	if (ret)
181		return ERR_PTR(ret);
182
183	if (!of_device_is_available(args.np)) {
184		ret = -EBUSY;
185		goto err;
186	}
187
188	val = args.args[0];
189
190	match = of_match_node(sunxi_sram_dt_ids, args.np);
191	if (!match) {
192		ret = -EINVAL;
193		goto err;
194	}
195
196	data = match->data;
197	if (!data) {
198		ret = -EINVAL;
199		goto err;
200	}
201
202	for (func = data->func; func->func; func++) {
203		if (val == func->val) {
204			if (reg_value)
205				*reg_value = func->reg_val;
206
207			break;
208		}
209	}
210
211	if (!func->func) {
212		ret = -EINVAL;
213		goto err;
214	}
215
216	of_node_put(args.np);
217	return match->data;
218
219err:
220	of_node_put(args.np);
221	return ERR_PTR(ret);
222}
223
224int sunxi_sram_claim(struct device *dev)
225{
226	const struct sunxi_sram_data *sram_data;
227	struct sunxi_sram_desc *sram_desc;
228	unsigned int device;
229	u32 val, mask;
230
231	if (IS_ERR(base))
232		return PTR_ERR(base);
233
234	if (!base)
235		return -EPROBE_DEFER;
236
237	if (!dev || !dev->of_node)
238		return -EINVAL;
239
240	sram_data = sunxi_sram_of_parse(dev->of_node, &device);
241	if (IS_ERR(sram_data))
242		return PTR_ERR(sram_data);
243
244	sram_desc = to_sram_desc(sram_data);
245
246	spin_lock(&sram_lock);
247
248	if (sram_desc->claimed) {
249		spin_unlock(&sram_lock);
250		return -EBUSY;
251	}
252
253	mask = GENMASK(sram_data->offset + sram_data->width - 1,
254		       sram_data->offset);
255	val = readl(base + sram_data->reg);
256	val &= ~mask;
257	writel(val | ((device << sram_data->offset) & mask),
258	       base + sram_data->reg);
259
260	sram_desc->claimed = true;
261	spin_unlock(&sram_lock);
262
263	return 0;
264}
265EXPORT_SYMBOL(sunxi_sram_claim);
266
267void sunxi_sram_release(struct device *dev)
268{
269	const struct sunxi_sram_data *sram_data;
270	struct sunxi_sram_desc *sram_desc;
271
272	if (!dev || !dev->of_node)
273		return;
274
275	sram_data = sunxi_sram_of_parse(dev->of_node, NULL);
276	if (IS_ERR(sram_data))
277		return;
278
279	sram_desc = to_sram_desc(sram_data);
280
281	spin_lock(&sram_lock);
282	sram_desc->claimed = false;
283	spin_unlock(&sram_lock);
284}
285EXPORT_SYMBOL(sunxi_sram_release);
286
287struct sunxi_sramc_variant {
288	int num_emac_clocks;
289	bool has_ldo_ctrl;
290};
291
292static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
293	/* Nothing special */
294};
295
296static const struct sunxi_sramc_variant sun8i_h3_sramc_variant = {
297	.num_emac_clocks = 1,
298};
299
300static const struct sunxi_sramc_variant sun20i_d1_sramc_variant = {
301	.num_emac_clocks = 1,
302	.has_ldo_ctrl = true,
303};
304
305static const struct sunxi_sramc_variant sun50i_a64_sramc_variant = {
306	.num_emac_clocks = 1,
307};
308
309static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = {
310	.num_emac_clocks = 2,
311};
312
313#define SUNXI_SRAM_EMAC_CLOCK_REG	0x30
314#define SUNXI_SYS_LDO_CTRL_REG		0x150
315
316static bool sunxi_sram_regmap_accessible_reg(struct device *dev,
317					     unsigned int reg)
318{
319	const struct sunxi_sramc_variant *variant = dev_get_drvdata(dev);
320
321	if (reg >= SUNXI_SRAM_EMAC_CLOCK_REG &&
322	    reg <  SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4)
323		return true;
324	if (reg == SUNXI_SYS_LDO_CTRL_REG && variant->has_ldo_ctrl)
325		return true;
326
327	return false;
328}
329
330static struct regmap_config sunxi_sram_regmap_config = {
331	.reg_bits       = 32,
332	.val_bits       = 32,
333	.reg_stride     = 4,
334	/* last defined register */
335	.max_register   = SUNXI_SYS_LDO_CTRL_REG,
336	/* other devices have no business accessing other registers */
337	.readable_reg	= sunxi_sram_regmap_accessible_reg,
338	.writeable_reg	= sunxi_sram_regmap_accessible_reg,
339};
340
341static int __init sunxi_sram_probe(struct platform_device *pdev)
342{
343	const struct sunxi_sramc_variant *variant;
344	struct device *dev = &pdev->dev;
345	struct regmap *regmap;
346
347	sram_dev = &pdev->dev;
348
349	variant = of_device_get_match_data(&pdev->dev);
350	if (!variant)
351		return -EINVAL;
352
353	dev_set_drvdata(dev, (struct sunxi_sramc_variant *)variant);
354
355	base = devm_platform_ioremap_resource(pdev, 0);
356	if (IS_ERR(base))
357		return PTR_ERR(base);
358
359	if (variant->num_emac_clocks || variant->has_ldo_ctrl) {
360		regmap = devm_regmap_init_mmio(dev, base, &sunxi_sram_regmap_config);
361		if (IS_ERR(regmap))
362			return PTR_ERR(regmap);
363	}
364
365	of_platform_populate(dev->of_node, NULL, NULL, dev);
366
367	debugfs_create_file("sram", 0444, NULL, NULL, &sunxi_sram_fops);
368
369	return 0;
370}
371
372static const struct of_device_id sunxi_sram_dt_match[] = {
373	{
374		.compatible = "allwinner,sun4i-a10-sram-controller",
375		.data = &sun4i_a10_sramc_variant,
376	},
377	{
378		.compatible = "allwinner,sun4i-a10-system-control",
379		.data = &sun4i_a10_sramc_variant,
380	},
381	{
382		.compatible = "allwinner,sun5i-a13-system-control",
383		.data = &sun4i_a10_sramc_variant,
384	},
385	{
386		.compatible = "allwinner,sun8i-a23-system-control",
387		.data = &sun4i_a10_sramc_variant,
388	},
389	{
390		.compatible = "allwinner,sun8i-h3-system-control",
391		.data = &sun8i_h3_sramc_variant,
392	},
393	{
394		.compatible = "allwinner,sun20i-d1-system-control",
395		.data = &sun20i_d1_sramc_variant,
396	},
397	{
398		.compatible = "allwinner,sun50i-a64-sram-controller",
399		.data = &sun50i_a64_sramc_variant,
400	},
401	{
402		.compatible = "allwinner,sun50i-a64-system-control",
403		.data = &sun50i_a64_sramc_variant,
404	},
405	{
406		.compatible = "allwinner,sun50i-h5-system-control",
407		.data = &sun50i_a64_sramc_variant,
408	},
409	{
410		.compatible = "allwinner,sun50i-h616-system-control",
411		.data = &sun50i_h616_sramc_variant,
412	},
413	{ },
414};
415MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match);
416
417static struct platform_driver sunxi_sram_driver = {
418	.driver = {
419		.name		= "sunxi-sram",
420		.of_match_table	= sunxi_sram_dt_match,
421	},
422};
423builtin_platform_driver_probe(sunxi_sram_driver, sunxi_sram_probe);
424
425MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
426MODULE_DESCRIPTION("Allwinner sunXi SRAM Controller Driver");
427